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Autogen MUL, move FP cases together
llvm-svn: 23512
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@ -820,23 +820,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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Select(N->getOperand(1)));
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return SDOperand(N, 0);
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}
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case ISD::MUL: {
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unsigned Imm, Opc;
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if (isIntImmediate(N->getOperand(1), Imm) && isInt16(Imm)) {
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CurDAG->SelectNodeTo(N, PPC::MULLI, MVT::i32,
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Select(N->getOperand(0)), getI32Imm(Lo16(Imm)));
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return SDOperand(N, 0);
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}
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CurDAG->SelectNodeTo(N, PPC::MULLW, MVT::i32, Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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return SDOperand(N, 0);
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}
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case ISD::FMUL: {
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unsigned Opc = N->getValueType(0) == MVT::f32 ? PPC::FMULS : PPC::FMUL;
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CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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return SDOperand(N, 0);
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}
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case ISD::SDIV: {
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unsigned Imm;
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if (isIntImmediate(N->getOperand(1), Imm)) {
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@ -871,13 +854,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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Select(N->getOperand(1)));
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return SDOperand(N, 0);
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}
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case ISD::FDIV: {
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unsigned Opc = N->getValueType(0) == MVT::f32 ? PPC::FDIVS : PPC::FDIV;
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CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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return SDOperand(N, 0);
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}
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case ISD::UDIV: {
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// If this is a divide by constant, we can emit code using some magic
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// constants to implement it as a multiply instead.
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@ -997,6 +973,18 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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Select(N->getOperand(1)));
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return SDOperand(N, 0);
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}
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case ISD::FMUL: {
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unsigned Opc = N->getValueType(0) == MVT::f32 ? PPC::FMULS : PPC::FMUL;
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CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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return SDOperand(N, 0);
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}
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case ISD::FDIV: {
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unsigned Opc = N->getValueType(0) == MVT::f32 ? PPC::FDIVS : PPC::FDIV;
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CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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return SDOperand(N, 0);
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}
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case ISD::FABS:
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CurDAG->SelectNodeTo(N, PPC::FABS, N->getValueType(0),
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Select(N->getOperand(0)));
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