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Add support for the X86 secure guard extensions instructions in assembler (SGX).
This allows assembling the two new instructions, encls and enclu for the SKX processor model. Note the diffs are a bigger than what might think, but to fit the new MRM_CF and MRM_D7 in things in the right places things had to be renumbered and shuffled down causing a bit more diffs. rdar://16228228 llvm-svn: 214460
This commit is contained in:
Kevin Enderby
parent
d154a413b6
commit
0615385ba4
@ -303,17 +303,18 @@ namespace X86II {
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//// MRM_XX - A mod/rm byte of exactly 0xXX.
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MRM_C0 = 32, MRM_C1 = 33, MRM_C2 = 34, MRM_C3 = 35,
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MRM_C4 = 36, MRM_C8 = 37, MRM_C9 = 38, MRM_CA = 39,
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MRM_CB = 40, MRM_D0 = 41, MRM_D1 = 42, MRM_D4 = 43,
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MRM_D5 = 44, MRM_D6 = 45, MRM_D8 = 46, MRM_D9 = 47,
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MRM_DA = 48, MRM_DB = 49, MRM_DC = 50, MRM_DD = 51,
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MRM_DE = 52, MRM_DF = 53, MRM_E0 = 54, MRM_E1 = 55,
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MRM_E2 = 56, MRM_E3 = 57, MRM_E4 = 58, MRM_E5 = 59,
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MRM_E8 = 60, MRM_E9 = 61, MRM_EA = 62, MRM_EB = 63,
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MRM_EC = 64, MRM_ED = 65, MRM_EE = 66, MRM_F0 = 67,
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MRM_F1 = 68, MRM_F2 = 69, MRM_F3 = 70, MRM_F4 = 71,
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MRM_F5 = 72, MRM_F6 = 73, MRM_F7 = 74, MRM_F8 = 75,
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MRM_F9 = 76, MRM_FA = 77, MRM_FB = 78, MRM_FC = 79,
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MRM_FD = 80, MRM_FE = 81, MRM_FF = 82,
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MRM_CB = 40, MRM_CF = 41, MRM_D0 = 42, MRM_D1 = 43,
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MRM_D4 = 44, MRM_D5 = 45, MRM_D6 = 46, MRM_D7 = 47,
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MRM_D8 = 48, MRM_D9 = 49, MRM_DA = 50, MRM_DB = 51,
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MRM_DC = 52, MRM_DD = 53, MRM_DE = 54, MRM_DF = 55,
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MRM_E0 = 56, MRM_E1 = 57, MRM_E2 = 58, MRM_E3 = 59,
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MRM_E4 = 60, MRM_E5 = 61, MRM_E8 = 62, MRM_E9 = 63,
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MRM_EA = 64, MRM_EB = 65, MRM_EC = 66, MRM_ED = 67,
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MRM_EE = 68, MRM_F0 = 69, MRM_F1 = 70, MRM_F2 = 71,
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MRM_F3 = 72, MRM_F4 = 73, MRM_F5 = 74, MRM_F6 = 75,
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MRM_F7 = 76, MRM_F8 = 77, MRM_F9 = 78, MRM_FA = 79,
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MRM_FB = 80, MRM_FC = 81, MRM_FD = 82, MRM_FE = 83,
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MRM_FF = 84,
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FormMask = 127,
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@ -697,20 +698,21 @@ namespace X86II {
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case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
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case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C8:
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case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
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case X86II::MRM_D0: case X86II::MRM_D1: case X86II::MRM_D4:
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case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8:
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case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB:
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case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE:
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case X86II::MRM_DF: case X86II::MRM_E0: case X86II::MRM_E1:
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case X86II::MRM_E2: case X86II::MRM_E3: case X86II::MRM_E4:
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case X86II::MRM_E5: case X86II::MRM_E8: case X86II::MRM_E9:
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case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
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case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_F0:
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case X86II::MRM_F1: case X86II::MRM_F2: case X86II::MRM_F3:
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case X86II::MRM_F4: case X86II::MRM_F5: case X86II::MRM_F6:
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case X86II::MRM_F7: case X86II::MRM_F8: case X86II::MRM_F9:
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case X86II::MRM_FA: case X86II::MRM_FB: case X86II::MRM_FC:
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case X86II::MRM_FD: case X86II::MRM_FE: case X86II::MRM_FF:
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case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
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case X86II::MRM_D4: case X86II::MRM_D5: case X86II::MRM_D6:
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case X86II::MRM_D7: case X86II::MRM_D8: case X86II::MRM_D9:
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case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC:
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case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DF:
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case X86II::MRM_E0: case X86II::MRM_E1: case X86II::MRM_E2:
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case X86II::MRM_E3: case X86II::MRM_E4: case X86II::MRM_E5:
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case X86II::MRM_E8: case X86II::MRM_E9: case X86II::MRM_EA:
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case X86II::MRM_EB: case X86II::MRM_EC: case X86II::MRM_ED:
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case X86II::MRM_EE: case X86II::MRM_F0: case X86II::MRM_F1:
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case X86II::MRM_F2: case X86II::MRM_F3: case X86II::MRM_F4:
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case X86II::MRM_F5: case X86II::MRM_F6: case X86II::MRM_F7:
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case X86II::MRM_F8: case X86II::MRM_F9: case X86II::MRM_FA:
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case X86II::MRM_FB: case X86II::MRM_FC: case X86II::MRM_FD:
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case X86II::MRM_FE: case X86II::MRM_FF:
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return -1;
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}
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}
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@ -1437,20 +1437,21 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
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case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C8:
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case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
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case X86II::MRM_D0: case X86II::MRM_D1: case X86II::MRM_D4:
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case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8:
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case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB:
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case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE:
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case X86II::MRM_DF: case X86II::MRM_E0: case X86II::MRM_E1:
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case X86II::MRM_E2: case X86II::MRM_E3: case X86II::MRM_E4:
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case X86II::MRM_E5: case X86II::MRM_E8: case X86II::MRM_E9:
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case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
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case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_F0:
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case X86II::MRM_F1: case X86II::MRM_F2: case X86II::MRM_F3:
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case X86II::MRM_F4: case X86II::MRM_F5: case X86II::MRM_F6:
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case X86II::MRM_F7: case X86II::MRM_F8: case X86II::MRM_F9:
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case X86II::MRM_FA: case X86II::MRM_FB: case X86II::MRM_FC:
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case X86II::MRM_FD: case X86II::MRM_FE: case X86II::MRM_FF:
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case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
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case X86II::MRM_D4: case X86II::MRM_D5: case X86II::MRM_D6:
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case X86II::MRM_D7: case X86II::MRM_D8: case X86II::MRM_D9:
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case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC:
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case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DF:
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case X86II::MRM_E0: case X86II::MRM_E1: case X86II::MRM_E2:
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case X86II::MRM_E3: case X86II::MRM_E4: case X86II::MRM_E5:
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case X86II::MRM_E8: case X86II::MRM_E9: case X86II::MRM_EA:
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case X86II::MRM_EB: case X86II::MRM_EC: case X86II::MRM_ED:
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case X86II::MRM_EE: case X86II::MRM_F0: case X86II::MRM_F1:
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case X86II::MRM_F2: case X86II::MRM_F3: case X86II::MRM_F4:
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case X86II::MRM_F5: case X86II::MRM_F6: case X86II::MRM_F7:
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case X86II::MRM_F8: case X86II::MRM_F9: case X86II::MRM_FA:
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case X86II::MRM_FB: case X86II::MRM_FC: case X86II::MRM_FD:
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case X86II::MRM_FE: case X86II::MRM_FF:
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EmitByte(BaseOpcode, CurByte, OS);
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unsigned char MRM;
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@ -1465,11 +1466,13 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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case X86II::MRM_C9: MRM = 0xC9; break;
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case X86II::MRM_CA: MRM = 0xCA; break;
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case X86II::MRM_CB: MRM = 0xCB; break;
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case X86II::MRM_CF: MRM = 0xCF; break;
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case X86II::MRM_D0: MRM = 0xD0; break;
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case X86II::MRM_D1: MRM = 0xD1; break;
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case X86II::MRM_D4: MRM = 0xD4; break;
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case X86II::MRM_D5: MRM = 0xD5; break;
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case X86II::MRM_D6: MRM = 0xD6; break;
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case X86II::MRM_D7: MRM = 0xD7; break;
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case X86II::MRM_D8: MRM = 0xD8; break;
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case X86II::MRM_D9: MRM = 0xD9; break;
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case X86II::MRM_DA: MRM = 0xDA; break;
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@ -157,6 +157,8 @@ def FeatureADX : SubtargetFeature<"adx", "HasADX", "true",
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def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true",
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"Enable SHA instructions",
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[FeatureSSE2]>;
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def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",
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"Support SGX instructions">;
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def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
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"Support PRFCHW instructions">;
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def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
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@ -293,7 +295,7 @@ def : ProcessorModel<"skx", HaswellModel,
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FeatureAES, FeaturePCLMUL, FeatureRDRAND, FeatureF16C,
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FeatureFSGSBase, FeatureMOVBE, FeatureLZCNT, FeatureBMI,
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FeatureBMI2, FeatureFMA, FeatureRTM, FeatureHLE,
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FeatureSlowIncDec]>;
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FeatureSlowIncDec, FeatureSGX]>;
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def : Proc<"k6", [FeatureMMX]>;
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def : Proc<"k6-2", [Feature3DNow]>;
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@ -1385,20 +1385,21 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
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case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
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case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C8:
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case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
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case X86II::MRM_D0: case X86II::MRM_D1: case X86II::MRM_D4:
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case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8:
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case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB:
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case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE:
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case X86II::MRM_DF: case X86II::MRM_E0: case X86II::MRM_E1:
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case X86II::MRM_E2: case X86II::MRM_E3: case X86II::MRM_E4:
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case X86II::MRM_E5: case X86II::MRM_E8: case X86II::MRM_E9:
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case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
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case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_F0:
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case X86II::MRM_F1: case X86II::MRM_F2: case X86II::MRM_F3:
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case X86II::MRM_F4: case X86II::MRM_F5: case X86II::MRM_F6:
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case X86II::MRM_F7: case X86II::MRM_F8: case X86II::MRM_F9:
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case X86II::MRM_FA: case X86II::MRM_FB: case X86II::MRM_FC:
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case X86II::MRM_FD: case X86II::MRM_FE: case X86II::MRM_FF:
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case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1:
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case X86II::MRM_D4: case X86II::MRM_D5: case X86II::MRM_D6:
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case X86II::MRM_D7: case X86II::MRM_D8: case X86II::MRM_D9:
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case X86II::MRM_DA: case X86II::MRM_DB: case X86II::MRM_DC:
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case X86II::MRM_DD: case X86II::MRM_DE: case X86II::MRM_DF:
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case X86II::MRM_E0: case X86II::MRM_E1: case X86II::MRM_E2:
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case X86II::MRM_E3: case X86II::MRM_E4: case X86II::MRM_E5:
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case X86II::MRM_E8: case X86II::MRM_E9: case X86II::MRM_EA:
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case X86II::MRM_EB: case X86II::MRM_EC: case X86II::MRM_ED:
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case X86II::MRM_EE: case X86II::MRM_F0: case X86II::MRM_F1:
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case X86II::MRM_F2: case X86II::MRM_F3: case X86II::MRM_F4:
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case X86II::MRM_F5: case X86II::MRM_F6: case X86II::MRM_F7:
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case X86II::MRM_F8: case X86II::MRM_F9: case X86II::MRM_FA:
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case X86II::MRM_FB: case X86II::MRM_FC: case X86II::MRM_FD:
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case X86II::MRM_FE: case X86II::MRM_FF:
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MCE.emitByte(BaseOpcode);
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unsigned char MRM;
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@ -1413,11 +1414,13 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
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case X86II::MRM_C9: MRM = 0xC9; break;
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case X86II::MRM_CA: MRM = 0xCA; break;
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case X86II::MRM_CB: MRM = 0xCB; break;
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case X86II::MRM_CF: MRM = 0xCF; break;
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case X86II::MRM_D0: MRM = 0xD0; break;
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case X86II::MRM_D1: MRM = 0xD1; break;
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case X86II::MRM_D4: MRM = 0xD4; break;
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case X86II::MRM_D5: MRM = 0xD5; break;
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case X86II::MRM_D6: MRM = 0xD6; break;
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case X86II::MRM_D7: MRM = 0xD7; break;
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case X86II::MRM_D8: MRM = 0xD8; break;
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case X86II::MRM_D9: MRM = 0xD9; break;
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case X86II::MRM_DA: MRM = 0xDA; break;
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@ -36,20 +36,21 @@ def MRM6m : Format<30>; def MRM7m : Format<31>;
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def MRM_C0 : Format<32>; def MRM_C1 : Format<33>; def MRM_C2 : Format<34>;
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def MRM_C3 : Format<35>; def MRM_C4 : Format<36>; def MRM_C8 : Format<37>;
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def MRM_C9 : Format<38>; def MRM_CA : Format<39>; def MRM_CB : Format<40>;
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def MRM_D0 : Format<41>; def MRM_D1 : Format<42>; def MRM_D4 : Format<43>;
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def MRM_D5 : Format<44>; def MRM_D6 : Format<45>; def MRM_D8 : Format<46>;
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def MRM_D9 : Format<47>; def MRM_DA : Format<48>; def MRM_DB : Format<49>;
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def MRM_DC : Format<50>; def MRM_DD : Format<51>; def MRM_DE : Format<52>;
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def MRM_DF : Format<53>; def MRM_E0 : Format<54>; def MRM_E1 : Format<55>;
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def MRM_E2 : Format<56>; def MRM_E3 : Format<57>; def MRM_E4 : Format<58>;
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def MRM_E5 : Format<59>; def MRM_E8 : Format<60>; def MRM_E9 : Format<61>;
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def MRM_EA : Format<62>; def MRM_EB : Format<63>; def MRM_EC : Format<64>;
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def MRM_ED : Format<65>; def MRM_EE : Format<66>; def MRM_F0 : Format<67>;
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def MRM_F1 : Format<68>; def MRM_F2 : Format<69>; def MRM_F3 : Format<70>;
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def MRM_F4 : Format<71>; def MRM_F5 : Format<72>; def MRM_F6 : Format<73>;
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def MRM_F7 : Format<74>; def MRM_F8 : Format<75>; def MRM_F9 : Format<76>;
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def MRM_FA : Format<77>; def MRM_FB : Format<78>; def MRM_FC : Format<79>;
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def MRM_FD : Format<80>; def MRM_FE : Format<81>; def MRM_FF : Format<82>;
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def MRM_CF : Format<41>; def MRM_D0 : Format<42>; def MRM_D1 : Format<43>;
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def MRM_D4 : Format<44>; def MRM_D5 : Format<45>; def MRM_D6 : Format<46>;
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def MRM_D7 : Format<47>; def MRM_D8 : Format<48>; def MRM_D9 : Format<49>;
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def MRM_DA : Format<50>; def MRM_DB : Format<51>; def MRM_DC : Format<52>;
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def MRM_DD : Format<53>; def MRM_DE : Format<54>; def MRM_DF : Format<55>;
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def MRM_E0 : Format<56>; def MRM_E1 : Format<57>; def MRM_E2 : Format<58>;
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def MRM_E3 : Format<59>; def MRM_E4 : Format<60>; def MRM_E5 : Format<61>;
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def MRM_E8 : Format<62>; def MRM_E9 : Format<63>; def MRM_EA : Format<64>;
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def MRM_EB : Format<65>; def MRM_EC : Format<66>; def MRM_ED : Format<67>;
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def MRM_EE : Format<68>; def MRM_F0 : Format<69>; def MRM_F1 : Format<70>;
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def MRM_F2 : Format<71>; def MRM_F3 : Format<72>; def MRM_F4 : Format<73>;
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def MRM_F5 : Format<74>; def MRM_F6 : Format<75>; def MRM_F7 : Format<76>;
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def MRM_F8 : Format<77>; def MRM_F9 : Format<78>; def MRM_FA : Format<79>;
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def MRM_FB : Format<80>; def MRM_FC : Format<81>; def MRM_FD : Format<82>;
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def MRM_FE : Format<83>; def MRM_FF : Format<84>;
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// ImmType - This specifies the immediate type used by an instruction. This is
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// part of the ad-hoc solution used to emit machine instruction encodings by our
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@ -748,6 +748,7 @@ def HasHLE : Predicate<"Subtarget->hasHLE()">;
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def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
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def HasADX : Predicate<"Subtarget->hasADX()">;
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def HasSHA : Predicate<"Subtarget->hasSHA()">;
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def HasSGX : Predicate<"Subtarget->hasSGX()">;
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def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
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def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
|
||||
def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
|
||||
@ -2400,6 +2401,7 @@ include "X86InstrVMX.td"
|
||||
include "X86InstrSVM.td"
|
||||
|
||||
include "X86InstrTSX.td"
|
||||
include "X86InstrSGX.td"
|
||||
|
||||
// System instructions.
|
||||
include "X86InstrSystem.td"
|
||||
|
||||
24
lib/Target/X86/X86InstrSGX.td
Normal file
24
lib/Target/X86/X86InstrSGX.td
Normal file
@ -0,0 +1,24 @@
|
||||
//===-- X86InstrSGX.td - SGX Instruction Set Extension -----*- tablegen -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file describes the instructions that make up the Intel SGX instruction
|
||||
// set.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SGX instructions
|
||||
|
||||
// ENCLS - Execute an Enclave System Function of Specified Leaf Number
|
||||
def ENCLS : I<0x01, MRM_CF, (outs), (ins),
|
||||
"encls", []>, TB, Requires<[HasSGX]>;
|
||||
|
||||
// ENCLU - Execute an Enclave User Function of Specified Leaf Number
|
||||
def ENCLU : I<0x01, MRM_D7, (outs), (ins),
|
||||
"enclu", []>, TB, Requires<[HasSGX]>;
|
||||
@ -277,6 +277,7 @@ void X86Subtarget::initializeEnvironment() {
|
||||
HasVLX = false;
|
||||
HasADX = false;
|
||||
HasSHA = false;
|
||||
HasSGX = false;
|
||||
HasPRFCHW = false;
|
||||
HasRDSEED = false;
|
||||
IsBTMemSlow = false;
|
||||
|
||||
@ -139,6 +139,9 @@ protected:
|
||||
/// HasSHA - Processor has SHA instructions.
|
||||
bool HasSHA;
|
||||
|
||||
/// HasSGX - Processor has SGX instructions.
|
||||
bool HasSGX;
|
||||
|
||||
/// HasPRFCHW - Processor has PRFCHW instructions.
|
||||
bool HasPRFCHW;
|
||||
|
||||
@ -341,6 +344,7 @@ public:
|
||||
bool hasHLE() const { return HasHLE; }
|
||||
bool hasADX() const { return HasADX; }
|
||||
bool hasSHA() const { return HasSHA; }
|
||||
bool hasSGX() const { return HasSGX; }
|
||||
bool hasPRFCHW() const { return HasPRFCHW; }
|
||||
bool hasRDSEED() const { return HasRDSEED; }
|
||||
bool isBTMemSlow() const { return IsBTMemSlow; }
|
||||
|
||||
9
test/MC/X86/sgx-encoding.s
Normal file
9
test/MC/X86/sgx-encoding.s
Normal file
@ -0,0 +1,9 @@
|
||||
// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
|
||||
|
||||
// CHECK: encls
|
||||
// CHECK: encoding: [0x0f,0x01,0xcf]
|
||||
encls
|
||||
|
||||
// CHECK: enclu
|
||||
// CHECK: encoding: [0x0f,0x01,0xd7]
|
||||
enclu
|
||||
@ -32,48 +32,50 @@ using namespace llvm;
|
||||
MAP(C9, 38) \
|
||||
MAP(CA, 39) \
|
||||
MAP(CB, 40) \
|
||||
MAP(D0, 41) \
|
||||
MAP(D1, 42) \
|
||||
MAP(D4, 43) \
|
||||
MAP(D5, 44) \
|
||||
MAP(D6, 45) \
|
||||
MAP(D8, 46) \
|
||||
MAP(D9, 47) \
|
||||
MAP(DA, 48) \
|
||||
MAP(DB, 49) \
|
||||
MAP(DC, 50) \
|
||||
MAP(DD, 51) \
|
||||
MAP(DE, 52) \
|
||||
MAP(DF, 53) \
|
||||
MAP(E0, 54) \
|
||||
MAP(E1, 55) \
|
||||
MAP(E2, 56) \
|
||||
MAP(E3, 57) \
|
||||
MAP(E4, 58) \
|
||||
MAP(E5, 59) \
|
||||
MAP(E8, 60) \
|
||||
MAP(E9, 61) \
|
||||
MAP(EA, 62) \
|
||||
MAP(EB, 63) \
|
||||
MAP(EC, 64) \
|
||||
MAP(ED, 65) \
|
||||
MAP(EE, 66) \
|
||||
MAP(F0, 67) \
|
||||
MAP(F1, 68) \
|
||||
MAP(F2, 69) \
|
||||
MAP(F3, 70) \
|
||||
MAP(F4, 71) \
|
||||
MAP(F5, 72) \
|
||||
MAP(F6, 73) \
|
||||
MAP(F7, 74) \
|
||||
MAP(F8, 75) \
|
||||
MAP(F9, 76) \
|
||||
MAP(FA, 77) \
|
||||
MAP(FB, 78) \
|
||||
MAP(FC, 79) \
|
||||
MAP(FD, 80) \
|
||||
MAP(FE, 81) \
|
||||
MAP(FF, 82)
|
||||
MAP(CF, 41) \
|
||||
MAP(D0, 42) \
|
||||
MAP(D1, 43) \
|
||||
MAP(D4, 44) \
|
||||
MAP(D5, 45) \
|
||||
MAP(D6, 46) \
|
||||
MAP(D7, 47) \
|
||||
MAP(D8, 48) \
|
||||
MAP(D9, 49) \
|
||||
MAP(DA, 50) \
|
||||
MAP(DB, 51) \
|
||||
MAP(DC, 52) \
|
||||
MAP(DD, 53) \
|
||||
MAP(DE, 54) \
|
||||
MAP(DF, 55) \
|
||||
MAP(E0, 56) \
|
||||
MAP(E1, 57) \
|
||||
MAP(E2, 58) \
|
||||
MAP(E3, 59) \
|
||||
MAP(E4, 60) \
|
||||
MAP(E5, 61) \
|
||||
MAP(E8, 62) \
|
||||
MAP(E9, 63) \
|
||||
MAP(EA, 64) \
|
||||
MAP(EB, 65) \
|
||||
MAP(EC, 66) \
|
||||
MAP(ED, 67) \
|
||||
MAP(EE, 68) \
|
||||
MAP(F0, 69) \
|
||||
MAP(F1, 70) \
|
||||
MAP(F2, 71) \
|
||||
MAP(F3, 72) \
|
||||
MAP(F4, 73) \
|
||||
MAP(F5, 74) \
|
||||
MAP(F6, 75) \
|
||||
MAP(F7, 76) \
|
||||
MAP(F8, 77) \
|
||||
MAP(F9, 78) \
|
||||
MAP(FA, 79) \
|
||||
MAP(FB, 80) \
|
||||
MAP(FC, 81) \
|
||||
MAP(FD, 82) \
|
||||
MAP(FE, 83) \
|
||||
MAP(FF, 84)
|
||||
|
||||
// A clone of X86 since we can't depend on something that is generated.
|
||||
namespace X86Local {
|
||||
@ -769,20 +771,21 @@ void RecognizableInstr::emitInstructionSpecifier() {
|
||||
case X86Local::MRM_C0: case X86Local::MRM_C1: case X86Local::MRM_C2:
|
||||
case X86Local::MRM_C3: case X86Local::MRM_C4: case X86Local::MRM_C8:
|
||||
case X86Local::MRM_C9: case X86Local::MRM_CA: case X86Local::MRM_CB:
|
||||
case X86Local::MRM_D0: case X86Local::MRM_D1: case X86Local::MRM_D4:
|
||||
case X86Local::MRM_D5: case X86Local::MRM_D6: case X86Local::MRM_D8:
|
||||
case X86Local::MRM_D9: case X86Local::MRM_DA: case X86Local::MRM_DB:
|
||||
case X86Local::MRM_DC: case X86Local::MRM_DD: case X86Local::MRM_DE:
|
||||
case X86Local::MRM_DF: case X86Local::MRM_E0: case X86Local::MRM_E1:
|
||||
case X86Local::MRM_E2: case X86Local::MRM_E3: case X86Local::MRM_E4:
|
||||
case X86Local::MRM_E5: case X86Local::MRM_E8: case X86Local::MRM_E9:
|
||||
case X86Local::MRM_EA: case X86Local::MRM_EB: case X86Local::MRM_EC:
|
||||
case X86Local::MRM_ED: case X86Local::MRM_EE: case X86Local::MRM_F0:
|
||||
case X86Local::MRM_F1: case X86Local::MRM_F2: case X86Local::MRM_F3:
|
||||
case X86Local::MRM_F4: case X86Local::MRM_F5: case X86Local::MRM_F6:
|
||||
case X86Local::MRM_F7: case X86Local::MRM_F9: case X86Local::MRM_FA:
|
||||
case X86Local::MRM_FB: case X86Local::MRM_FC: case X86Local::MRM_FD:
|
||||
case X86Local::MRM_FE: case X86Local::MRM_FF:
|
||||
case X86Local::MRM_CF: case X86Local::MRM_D0: case X86Local::MRM_D1:
|
||||
case X86Local::MRM_D4: case X86Local::MRM_D5: case X86Local::MRM_D6:
|
||||
case X86Local::MRM_D7: case X86Local::MRM_D8: case X86Local::MRM_D9:
|
||||
case X86Local::MRM_DA: case X86Local::MRM_DB: case X86Local::MRM_DC:
|
||||
case X86Local::MRM_DD: case X86Local::MRM_DE: case X86Local::MRM_DF:
|
||||
case X86Local::MRM_E0: case X86Local::MRM_E1: case X86Local::MRM_E2:
|
||||
case X86Local::MRM_E3: case X86Local::MRM_E4: case X86Local::MRM_E5:
|
||||
case X86Local::MRM_E8: case X86Local::MRM_E9: case X86Local::MRM_EA:
|
||||
case X86Local::MRM_EB: case X86Local::MRM_EC: case X86Local::MRM_ED:
|
||||
case X86Local::MRM_EE: case X86Local::MRM_F0: case X86Local::MRM_F1:
|
||||
case X86Local::MRM_F2: case X86Local::MRM_F3: case X86Local::MRM_F4:
|
||||
case X86Local::MRM_F5: case X86Local::MRM_F6: case X86Local::MRM_F7:
|
||||
case X86Local::MRM_F9: case X86Local::MRM_FA: case X86Local::MRM_FB:
|
||||
case X86Local::MRM_FC: case X86Local::MRM_FD: case X86Local::MRM_FE:
|
||||
case X86Local::MRM_FF:
|
||||
// Ignored.
|
||||
break;
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user