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Add support for undef
llvm-svn: 24839
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@ -243,9 +243,9 @@ void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
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abort();
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}
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} else if (isa<UndefValue>(C)) {
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BuildMI(*MBB, IP, V8::IMPLICIT_DEF, 0, R);
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BuildMI(*MBB, IP, V8::IMPLICIT_DEF_Int, 0, R);
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if (getClassB (C->getType ()) == cLong)
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BuildMI(*MBB, IP, V8::IMPLICIT_DEF, 0, R+1);
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BuildMI(*MBB, IP, V8::IMPLICIT_DEF_Int, 0, R+1);
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return;
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}
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@ -341,15 +341,15 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
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case cShort:
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case cInt:
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case cFloat:
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BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
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BuildMI(BB, V8::IMPLICIT_DEF_Int, 0, IncomingArgRegs[ArgNo]);
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break;
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case cDouble:
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case cLong:
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// Double and Long use register pairs.
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BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
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BuildMI(BB, V8::IMPLICIT_DEF_Int, 0, IncomingArgRegs[ArgNo]);
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++ArgNo;
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if (ArgNo < 6)
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BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgNo]);
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BuildMI(BB, V8::IMPLICIT_DEF_Int, 0, IncomingArgRegs[ArgNo]);
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break;
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default:
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assert (0 && "type not handled");
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@ -111,7 +111,13 @@ def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
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def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt),
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"!ADJCALLSTACKUP $amt",
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[(callseq_end imm:$amt)]>;
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def IMPLICIT_DEF : Pseudo<(ops IntRegs:$dst), "!IMPLICIT_DEF $dst", []>;
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def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst),
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"!IMPLICIT_DEF $dst",
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[(set IntRegs:$dst, (undef))]>;
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def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst",
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[(set FPRegs:$dst, (undef))]>;
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def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst",
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[(set DFPRegs:$dst, (undef))]>;
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def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
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"!FpMOVD", []>; // pseudo 64-bit double move
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