mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-12-21 19:20:28 +00:00
Fix whitespace.
llvm-svn: 124270
This commit is contained in:
NAKAMURA Takumi
parent
a3d094f248
commit
066378440a
@ -69,7 +69,7 @@ static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
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return new X8664_MachoTargetObjectFile();
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return new TargetLoweringObjectFileMachO();
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}
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if (TM.getSubtarget<X86Subtarget>().isTargetELF() ){
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if (is64Bit)
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return new X8664_ELFTargetObjectFile(TM);
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@ -256,7 +256,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::UDIV, VT, Expand);
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setOperationAction(ISD::SREM, VT, Expand);
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setOperationAction(ISD::UREM, VT, Expand);
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// Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
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setOperationAction(ISD::ADDC, VT, Custom);
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setOperationAction(ISD::ADDE, VT, Custom);
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@ -369,7 +369,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
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}
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if (!Subtarget->is64Bit()) {
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setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
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@ -931,7 +931,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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// We want to custom lower some of our intrinsics.
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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// Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
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// handle type legalization for these operations here.
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//
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@ -948,7 +948,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::SMULO, VT, Custom);
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setOperationAction(ISD::UMULO, VT, Custom);
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}
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// There are no 8-bit 3-address imul/mul instructions
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setOperationAction(ISD::SMULO, MVT::i8, Expand);
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setOperationAction(ISD::UMULO, MVT::i8, Expand);
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@ -6198,7 +6198,7 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
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// TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
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MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
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MFI->setAdjustsStack(true);
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// And our return value (tls address) is in the standard call return value
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// location.
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unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
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@ -7047,7 +7047,7 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
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(cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
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cast<ConstantSDNode>(Op1)->isNullValue()) &&
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(CC == ISD::SETEQ || CC == ISD::SETNE)) {
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// If the input is a setcc, then reuse the input setcc or use a new one with
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// the inverted condition.
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if (Op0.getOpcode() == X86ISD::SETCC) {
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@ -7055,7 +7055,7 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
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bool Invert = (CC == ISD::SETNE) ^
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cast<ConstantSDNode>(Op1)->isNullValue();
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if (!Invert) return Op0;
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CCode = X86::GetOppositeBranchCondition(CCode);
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return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
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DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
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@ -7206,7 +7206,7 @@ static bool isX86LogicalCmp(SDValue Op) {
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if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
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return true;
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return false;
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}
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@ -7242,24 +7242,24 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
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isZero(Cond.getOperand(1).getOperand(1))) {
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SDValue Cmp = Cond.getOperand(1);
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unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
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if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
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if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
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(CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
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SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
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SDValue CmpOp0 = Cmp.getOperand(0);
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Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
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CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
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SDValue Res = // Res = 0 or -1.
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DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
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DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
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if (isAllOnes(Op1) != (CondCode == X86::COND_E))
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Res = DAG.getNOT(DL, Res, Res.getValueType());
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ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
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if (N2C == 0 || !N2C->isNullValue())
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Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
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@ -8443,7 +8443,7 @@ SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const {
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Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
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// return pblendv(r, r+r, a);
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R = DAG.getNode(X86ISD::PBLENDVB, dl, VT,
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R = DAG.getNode(X86ISD::PBLENDVB, dl, VT,
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R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
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return R;
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}
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@ -8503,12 +8503,12 @@ SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
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SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
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MVT::i32);
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SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
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SDValue SetCC =
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DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
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DAG.getConstant(X86::COND_O, MVT::i32),
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SDValue(Sum.getNode(), 2));
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DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
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return Sum;
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}
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@ -8663,9 +8663,9 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
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// Let legalize expand this if it isn't a legal type yet.
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if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
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return SDValue();
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SDVTList VTs = DAG.getVTList(VT, MVT::i32);
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unsigned Opc;
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bool ExtraOp = false;
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switch (Op.getOpcode()) {
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@ -8675,7 +8675,7 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
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case ISD::SUBC: Opc = X86ISD::SUB; break;
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case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
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}
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if (!ExtraOp)
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return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
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Op.getOperand(1));
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@ -9555,14 +9555,14 @@ MachineBasicBlock *
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X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
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DebugLoc dl = MI->getDebugLoc();
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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// Address into RAX/EAX, other two args into ECX, EDX.
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unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
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unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
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MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
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for (int i = 0; i < X86::AddrNumOperands; ++i)
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MIB.addOperand(MI->getOperand(i));
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unsigned ValOps = X86::AddrNumOperands;
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BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
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.addReg(MI->getOperand(ValOps).getReg());
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@ -9571,7 +9571,7 @@ X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
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// The instruction doesn't actually take any operands though.
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BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
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MI->eraseFromParent(); // The pseudo is gone now.
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return BB;
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}
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@ -9580,16 +9580,16 @@ MachineBasicBlock *
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X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
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DebugLoc dl = MI->getDebugLoc();
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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// First arg in ECX, the second in EAX.
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BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
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.addReg(MI->getOperand(0).getReg());
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BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
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.addReg(MI->getOperand(1).getReg());
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// The instruction doesn't actually take any operands though.
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BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
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MI->eraseFromParent(); // The pseudo is gone now.
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return BB;
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}
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@ -10195,7 +10195,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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// Thread synchronization.
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case X86::MONITOR:
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return EmitMonitor(MI, BB);
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return EmitMonitor(MI, BB);
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case X86::MWAIT:
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return EmitMwait(MI, BB);
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@ -11116,19 +11116,19 @@ static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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if (DCI.isBeforeLegalizeOps())
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return SDValue();
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// Want to form PANDN nodes, in the hopes of then easily combining them with
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// OR and AND nodes to form PBLEND/PSIGN.
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EVT VT = N->getValueType(0);
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if (VT != MVT::v2i64)
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return SDValue();
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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DebugLoc DL = N->getDebugLoc();
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// Check LHS for vnot
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if (N0.getOpcode() == ISD::XOR &&
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if (N0.getOpcode() == ISD::XOR &&
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ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
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return DAG.getNode(X86ISD::PANDN, DL, VT, N0.getOperand(0), N1);
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@ -11136,7 +11136,7 @@ static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
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if (N1.getOpcode() == ISD::XOR &&
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ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
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return DAG.getNode(X86ISD::PANDN, DL, VT, N1.getOperand(0), N0);
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return SDValue();
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}
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@ -11152,7 +11152,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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// look for psign/blend
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if (Subtarget->hasSSSE3()) {
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if (VT == MVT::v2i64) {
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@ -11168,17 +11168,17 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
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Y = N0.getOperand(1);
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if (N0.getOperand(1) == Mask)
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Y = N0.getOperand(0);
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// Check to see if the mask appeared in both the AND and PANDN and
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if (!Y.getNode())
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return SDValue();
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// Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
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if (Mask.getOpcode() != ISD::BITCAST ||
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X.getOpcode() != ISD::BITCAST ||
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Y.getOpcode() != ISD::BITCAST)
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return SDValue();
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// Look through mask bitcast.
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Mask = Mask.getOperand(0);
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EVT MaskVT = Mask.getValueType();
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@ -11187,7 +11187,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
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// will be an intrinsic.
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if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
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return SDValue();
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// FIXME: what to do for bytes, since there is a psignb/pblendvb, but
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// there is no psrai.b
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switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
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@ -11196,14 +11196,14 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
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break;
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default: return SDValue();
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}
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// Check that the SRA is all signbits.
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SDValue SraC = Mask.getOperand(2);
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unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
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unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
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if ((SraAmt + 1) != EltBits)
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return SDValue();
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DebugLoc DL = N->getDebugLoc();
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// Now we know we at least have a plendvb with the mask val. See if
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@ -11229,7 +11229,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
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// PBLENDVB only available on SSE 4.1
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if (!Subtarget->hasSSE41())
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return SDValue();
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X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
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Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
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Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
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@ -11238,7 +11238,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
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}
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}
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}
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// fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
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if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
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std::swap(N0, N1);
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@ -11290,7 +11290,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
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DAG.getNode(ISD::TRUNCATE, DL,
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MVT::i8, ShAmt0));
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}
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return SDValue();
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}
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@ -11500,7 +11500,7 @@ static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
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unsigned X86CC = N->getConstantOperandVal(0);
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SDValue EFLAG = N->getOperand(1);
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DebugLoc DL = N->getDebugLoc();
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// Materialize "setb reg" as "sbb reg,reg", since it can be extended without
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// a zext and produces an all-ones bit which is more useful than 0/1 in some
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// cases.
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@ -11509,10 +11509,10 @@ static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
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DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
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DAG.getConstant(X86CC, MVT::i8), EFLAG),
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DAG.getConstant(1, MVT::i8));
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return SDValue();
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}
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// Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
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static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
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X86TargetLowering::DAGCombinerInfo &DCI) {
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@ -11544,7 +11544,7 @@ static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
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// (sub (setne X, 0), Y) -> adc -1, Y
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static SDValue OptimizeConditonalInDecrement(SDNode *N, SelectionDAG &DAG) {
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DebugLoc DL = N->getDebugLoc();
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// Look through ZExts.
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SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
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if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
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@ -849,38 +849,38 @@ def : Pat<(X86call (i64 texternalsym:$dst)),
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// tailcall stuff
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def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
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(TCRETURNri GR32_TC:$dst, imm:$off)>,
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Requires<[In32BitMode]>;
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Requires<[In32BitMode]>;
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// FIXME: This is disabled for 32-bit PIC mode because the global base
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// register which is part of the address mode may be assigned a
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// callee-saved register.
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def : Pat<(X86tcret (load addr:$dst), imm:$off),
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(TCRETURNmi addr:$dst, imm:$off)>,
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Requires<[In32BitMode, IsNotPIC]>;
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Requires<[In32BitMode, IsNotPIC]>;
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def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
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(TCRETURNdi texternalsym:$dst, imm:$off)>,
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Requires<[In32BitMode]>;
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Requires<[In32BitMode]>;
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def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
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(TCRETURNdi texternalsym:$dst, imm:$off)>,
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Requires<[In32BitMode]>;
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Requires<[In32BitMode]>;
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def : Pat<(X86tcret GR64_TC:$dst, imm:$off),
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(TCRETURNri64 GR64_TC:$dst, imm:$off)>,
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Requires<[In64BitMode]>;
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Requires<[In64BitMode]>;
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def : Pat<(X86tcret (load addr:$dst), imm:$off),
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(TCRETURNmi64 addr:$dst, imm:$off)>,
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Requires<[In64BitMode]>;
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Requires<[In64BitMode]>;
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def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
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||||
(TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
|
||||
Requires<[In64BitMode]>;
|
||||
Requires<[In64BitMode]>;
|
||||
|
||||
def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
|
||||
(TCRETURNdi64 texternalsym:$dst, imm:$off)>,
|
||||
Requires<[In64BitMode]>;
|
||||
Requires<[In64BitMode]>;
|
||||
|
||||
// Normal calls, with various flavors of addresses.
|
||||
def : Pat<(X86call (i32 tglobaladdr:$dst)),
|
||||
@ -1661,4 +1661,3 @@ def : Pat<(and GR64:$src1, i64immSExt8:$src2),
|
||||
(AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
|
||||
def : Pat<(and GR64:$src1, i64immSExt32:$src2),
|
||||
(AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
|
||||
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
//===- X86InstrControl.td - Control Flow Instructions ------*- tablegen -*-===//
|
||||
//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file describes the X86 jump, return, call, and related instructions.
|
||||
@ -43,7 +43,7 @@ let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
|
||||
"jmp\t$dst", [(br bb:$dst)]>;
|
||||
def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
|
||||
"jmp\t$dst", []>;
|
||||
def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst),
|
||||
def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst),
|
||||
"jmp{q}\t$dst", []>;
|
||||
}
|
||||
|
||||
@ -108,16 +108,16 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
|
||||
def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
|
||||
[(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>;
|
||||
|
||||
def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
|
||||
def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
|
||||
(ins i16imm:$off, i16imm:$seg),
|
||||
"ljmp{w}\t{$seg, $off|$off, $seg}", []>, OpSize;
|
||||
def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
|
||||
(ins i32imm:$off, i16imm:$seg),
|
||||
"ljmp{l}\t{$seg, $off|$off, $seg}", []>;
|
||||
"ljmp{l}\t{$seg, $off|$off, $seg}", []>;
|
||||
def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
|
||||
"ljmp{q}\t{*}$dst", []>;
|
||||
|
||||
def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
|
||||
def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
|
||||
"ljmp{w}\t{*}$dst", []>, OpSize;
|
||||
def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
|
||||
"ljmp{l}\t{*}$dst", []>;
|
||||
@ -152,14 +152,14 @@ let isCall = 1 in
|
||||
def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
|
||||
"call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))]>,
|
||||
Requires<[In32BitMode]>;
|
||||
|
||||
def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
|
||||
|
||||
def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
|
||||
(ins i16imm:$off, i16imm:$seg),
|
||||
"lcall{w}\t{$seg, $off|$off, $seg}", []>, OpSize;
|
||||
def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
|
||||
(ins i32imm:$off, i16imm:$seg),
|
||||
"lcall{l}\t{$seg, $off|$off, $seg}", []>;
|
||||
|
||||
|
||||
def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
|
||||
"lcall{w}\t{*}$dst", []>, OpSize;
|
||||
def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
|
||||
@ -182,12 +182,12 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
|
||||
XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
|
||||
XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
|
||||
Uses = [ESP] in {
|
||||
def TCRETURNdi : PseudoI<(outs),
|
||||
def TCRETURNdi : PseudoI<(outs),
|
||||
(ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops), []>;
|
||||
def TCRETURNri : PseudoI<(outs),
|
||||
def TCRETURNri : PseudoI<(outs),
|
||||
(ins GR32_TC:$dst, i32imm:$offset, variable_ops), []>;
|
||||
let mayLoad = 1 in
|
||||
def TCRETURNmi : PseudoI<(outs),
|
||||
def TCRETURNmi : PseudoI<(outs),
|
||||
(ins i32mem_TC:$dst, i32imm:$offset, variable_ops), []>;
|
||||
|
||||
// FIXME: The should be pseudo instructions that are lowered when going to
|
||||
@ -196,7 +196,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
|
||||
(ins i32imm_pcrel:$dst, variable_ops),
|
||||
"jmp\t$dst # TAILCALL",
|
||||
[]>;
|
||||
def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
|
||||
def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
|
||||
"", []>; // FIXME: Remove encoding when JIT is dead.
|
||||
let mayLoad = 1 in
|
||||
def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
|
||||
@ -218,7 +218,7 @@ let isCall = 1 in
|
||||
XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
|
||||
XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
|
||||
Uses = [RSP] in {
|
||||
|
||||
|
||||
// NOTE: this pattern doesn't match "X86call imm", because we do not know
|
||||
// that the offset between an arbitrary immediate and the call will fit in
|
||||
// the 32-bit pcrel field that we have.
|
||||
@ -232,12 +232,12 @@ let isCall = 1 in
|
||||
def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
|
||||
"call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
|
||||
Requires<[In64BitMode, NotWin64]>;
|
||||
|
||||
|
||||
def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
|
||||
"lcall{q}\t{*}$dst", []>;
|
||||
}
|
||||
|
||||
// FIXME: We need to teach codegen about single list of call-clobbered
|
||||
// FIXME: We need to teach codegen about single list of call-clobbered
|
||||
// registers.
|
||||
let isCall = 1, isCodeGenOnly = 1 in
|
||||
// All calls clobber the non-callee saved registers. RSP is marked as
|
||||
@ -256,10 +256,10 @@ let isCall = 1, isCodeGenOnly = 1 in
|
||||
def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
|
||||
"call{q}\t{*}$dst",
|
||||
[(X86call GR64:$dst)]>, Requires<[IsWin64]>;
|
||||
def WINCALL64m : I<0xFF, MRM2m, (outs),
|
||||
def WINCALL64m : I<0xFF, MRM2m, (outs),
|
||||
(ins i64mem:$dst,variable_ops),
|
||||
"call{q}\t{*}$dst",
|
||||
[(X86call (loadi64 addr:$dst))]>,
|
||||
[(X86call (loadi64 addr:$dst))]>,
|
||||
Requires<[IsWin64]>;
|
||||
}
|
||||
|
||||
@ -278,7 +278,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
|
||||
def TCRETURNri64 : PseudoI<(outs),
|
||||
(ins GR64_TC:$dst, i32imm:$offset, variable_ops), []>;
|
||||
let mayLoad = 1 in
|
||||
def TCRETURNmi64 : PseudoI<(outs),
|
||||
def TCRETURNmi64 : PseudoI<(outs),
|
||||
(ins i64mem_TC:$dst, i32imm:$offset, variable_ops), []>;
|
||||
|
||||
def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs),
|
||||
@ -291,4 +291,3 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
|
||||
def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst, variable_ops),
|
||||
"jmp{q}\t{*}$dst # TAILCALL", []>;
|
||||
}
|
||||
|
||||
|
||||
@ -58,7 +58,7 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
|
||||
TB_NOT_REVERSABLE = 1U << 31,
|
||||
TB_FLAGS = TB_NOT_REVERSABLE
|
||||
};
|
||||
|
||||
|
||||
static const unsigned OpTbl2Addr[][2] = {
|
||||
{ X86::ADC32ri, X86::ADC32mi },
|
||||
{ X86::ADC32ri8, X86::ADC32mi8 },
|
||||
@ -231,16 +231,16 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
|
||||
unsigned MemOp = OpTbl2Addr[i][1] & ~TB_FLAGS;
|
||||
assert(!RegOp2MemOpTable2Addr.count(RegOp) && "Duplicated entries?");
|
||||
RegOp2MemOpTable2Addr[RegOp] = std::make_pair(MemOp, 0U);
|
||||
|
||||
|
||||
// If this is not a reversable operation (because there is a many->one)
|
||||
// mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
|
||||
if (OpTbl2Addr[i][1] & TB_NOT_REVERSABLE)
|
||||
continue;
|
||||
|
||||
|
||||
// Index 0, folded load and store, no alignment requirement.
|
||||
unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
|
||||
|
||||
assert(!MemOp2RegOpTable.count(MemOp) &&
|
||||
|
||||
assert(!MemOp2RegOpTable.count(MemOp) &&
|
||||
"Duplicated entries in unfolding maps?");
|
||||
MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo);
|
||||
}
|
||||
@ -334,12 +334,12 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
|
||||
unsigned Align = OpTbl0[i][3];
|
||||
assert(!RegOp2MemOpTable0.count(RegOp) && "Duplicated entries?");
|
||||
RegOp2MemOpTable0[RegOp] = std::make_pair(MemOp, Align);
|
||||
|
||||
|
||||
// If this is not a reversable operation (because there is a many->one)
|
||||
// mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
|
||||
if (OpTbl0[i][1] & TB_NOT_REVERSABLE)
|
||||
continue;
|
||||
|
||||
|
||||
// Index 0, folded load or store.
|
||||
unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
|
||||
assert(!MemOp2RegOpTable.count(MemOp) && "Duplicated entries?");
|
||||
@ -461,12 +461,12 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
|
||||
unsigned Align = OpTbl1[i][2];
|
||||
assert(!RegOp2MemOpTable1.count(RegOp) && "Duplicate entries");
|
||||
RegOp2MemOpTable1[RegOp] = std::make_pair(MemOp, Align);
|
||||
|
||||
|
||||
// If this is not a reversable operation (because there is a many->one)
|
||||
// mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
|
||||
if (OpTbl1[i][1] & TB_NOT_REVERSABLE)
|
||||
continue;
|
||||
|
||||
|
||||
// Index 1, folded load
|
||||
unsigned AuxInfo = 1 | (1 << 4);
|
||||
assert(!MemOp2RegOpTable.count(MemOp) && "Duplicate entries");
|
||||
@ -678,15 +678,15 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
|
||||
unsigned RegOp = OpTbl2[i][0];
|
||||
unsigned MemOp = OpTbl2[i][1] & ~TB_FLAGS;
|
||||
unsigned Align = OpTbl2[i][2];
|
||||
|
||||
|
||||
assert(!RegOp2MemOpTable2.count(RegOp) && "Duplicate entry!");
|
||||
RegOp2MemOpTable2[RegOp] = std::make_pair(MemOp, Align);
|
||||
|
||||
|
||||
// If this is not a reversable operation (because there is a many->one)
|
||||
// mapping, don't insert the reverse of the operation into MemOp2RegOpTable.
|
||||
if (OpTbl2[i][1] & TB_NOT_REVERSABLE)
|
||||
continue;
|
||||
|
||||
|
||||
// Index 2, folded load
|
||||
unsigned AuxInfo = 2 | (1 << 4);
|
||||
assert(!MemOp2RegOpTable.count(MemOp) &&
|
||||
@ -808,7 +808,7 @@ static bool isFrameStoreOpcode(int Opcode) {
|
||||
return false;
|
||||
}
|
||||
|
||||
unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
|
||||
unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
|
||||
int &FrameIndex) const {
|
||||
if (isFrameLoadOpcode(MI->getOpcode()))
|
||||
if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
|
||||
@ -816,7 +816,7 @@ unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
|
||||
unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
|
||||
int &FrameIndex) const {
|
||||
if (isFrameLoadOpcode(MI->getOpcode())) {
|
||||
unsigned Reg;
|
||||
@ -946,10 +946,10 @@ X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
|
||||
isPICBase = true;
|
||||
}
|
||||
return isPICBase;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
case X86::LEA32r:
|
||||
case X86::LEA64r: {
|
||||
if (MI->getOperand(2).isImm() &&
|
||||
@ -1124,9 +1124,9 @@ X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
|
||||
MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
|
||||
unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
|
||||
unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
|
||||
|
||||
|
||||
// Build and insert into an implicit UNDEF value. This is OK because
|
||||
// well be shifting and then extracting the lower 16-bits.
|
||||
// well be shifting and then extracting the lower 16-bits.
|
||||
// This has the potential to cause partial register stall. e.g.
|
||||
// movw (%rbp,%rcx,2), %dx
|
||||
// leal -65(%rdx), %esi
|
||||
@ -1162,7 +1162,7 @@ X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
|
||||
case X86::ADD16ri8:
|
||||
case X86::ADD16ri_DB:
|
||||
case X86::ADD16ri8_DB:
|
||||
addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
|
||||
addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
|
||||
break;
|
||||
case X86::ADD16rr:
|
||||
case X86::ADD16rr_DB: {
|
||||
@ -1177,7 +1177,7 @@ X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
|
||||
} else {
|
||||
leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
|
||||
// Build and insert into an implicit UNDEF value. This is OK because
|
||||
// well be shifting and then extracting the lower 16-bits.
|
||||
// well be shifting and then extracting the lower 16-bits.
|
||||
BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
|
||||
InsMI2 =
|
||||
BuildMI(*MFI, MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
|
||||
@ -1244,7 +1244,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
|
||||
case X86::SHUFPSrri: {
|
||||
assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
|
||||
if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
|
||||
|
||||
|
||||
unsigned B = MI->getOperand(1).getReg();
|
||||
unsigned C = MI->getOperand(2).getReg();
|
||||
if (B != C) return 0;
|
||||
@ -1392,7 +1392,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
|
||||
RC = X86::GR32_NOSPRegisterClass;
|
||||
}
|
||||
|
||||
|
||||
|
||||
unsigned Src2 = MI->getOperand(2).getReg();
|
||||
bool isKill2 = MI->getOperand(2).isKill();
|
||||
|
||||
@ -1471,7 +1471,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
|
||||
LV->replaceKillInstruction(Dest, MI, NewMI);
|
||||
}
|
||||
|
||||
MFI->insert(MBBI, NewMI); // Insert the new inst
|
||||
MFI->insert(MBBI, NewMI); // Insert the new inst
|
||||
return NewMI;
|
||||
}
|
||||
|
||||
@ -1692,7 +1692,7 @@ X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
|
||||
bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
|
||||
const TargetInstrDesc &TID = MI->getDesc();
|
||||
if (!TID.isTerminator()) return false;
|
||||
|
||||
|
||||
// Conditional branch is a special case.
|
||||
if (TID.isBranch() && !TID.isBarrier())
|
||||
return true;
|
||||
@ -1701,7 +1701,7 @@ bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
|
||||
return !isPredicated(MI);
|
||||
}
|
||||
|
||||
bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
|
||||
bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock *&TBB,
|
||||
MachineBasicBlock *&FBB,
|
||||
SmallVectorImpl<MachineOperand> &Cond,
|
||||
@ -1862,7 +1862,7 @@ unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
|
||||
I = MBB.end();
|
||||
++Count;
|
||||
}
|
||||
|
||||
|
||||
return Count;
|
||||
}
|
||||
|
||||
@ -2177,7 +2177,7 @@ static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
|
||||
MIB.addOperand(MOs[i]);
|
||||
if (NumAddrOps < 4) // FrameIndex only
|
||||
addOffset(MIB, 0);
|
||||
|
||||
|
||||
// Loop over the rest of the ri operands, converting them over.
|
||||
unsigned NumOps = MI->getDesc().getNumOperands()-2;
|
||||
for (unsigned i = 0; i != NumOps; ++i) {
|
||||
@ -2198,7 +2198,7 @@ static MachineInstr *FuseInst(MachineFunction &MF,
|
||||
MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
|
||||
MI->getDebugLoc(), true);
|
||||
MachineInstrBuilder MIB(NewMI);
|
||||
|
||||
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (i == OpNo) {
|
||||
@ -2247,7 +2247,7 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
|
||||
if (isTwoAddr && NumOps >= 2 && i < 2 &&
|
||||
MI->getOperand(0).isReg() &&
|
||||
MI->getOperand(1).isReg() &&
|
||||
MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
|
||||
MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
|
||||
OpcodeTablePtr = &RegOp2MemOpTable2Addr;
|
||||
isTwoAddrFold = true;
|
||||
} else if (i == 0) { // If operand 0
|
||||
@ -2261,14 +2261,14 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
|
||||
NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
|
||||
if (NewMI)
|
||||
return NewMI;
|
||||
|
||||
|
||||
OpcodeTablePtr = &RegOp2MemOpTable0;
|
||||
} else if (i == 1) {
|
||||
OpcodeTablePtr = &RegOp2MemOpTable1;
|
||||
} else if (i == 2) {
|
||||
OpcodeTablePtr = &RegOp2MemOpTable2;
|
||||
}
|
||||
|
||||
|
||||
// If table selected...
|
||||
if (OpcodeTablePtr) {
|
||||
// Find the Opcode to fuse
|
||||
@ -2316,8 +2316,8 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
|
||||
return NewMI;
|
||||
}
|
||||
}
|
||||
|
||||
// No fusion
|
||||
|
||||
// No fusion
|
||||
if (PrintFailedFusing && !MI->isCopy())
|
||||
dbgs() << "We failed to fuse operand " << i << " in " << *MI;
|
||||
return NULL;
|
||||
@ -2328,7 +2328,7 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
|
||||
MachineInstr *MI,
|
||||
const SmallVectorImpl<unsigned> &Ops,
|
||||
int FrameIndex) const {
|
||||
// Check switch flag
|
||||
// Check switch flag
|
||||
if (NoFusing) return NULL;
|
||||
|
||||
if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
|
||||
@ -2380,7 +2380,7 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
|
||||
MachineInstr *MI,
|
||||
const SmallVectorImpl<unsigned> &Ops,
|
||||
MachineInstr *LoadMI) const {
|
||||
// Check switch flag
|
||||
// Check switch flag
|
||||
if (NoFusing) return NULL;
|
||||
|
||||
if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
|
||||
@ -2523,13 +2523,13 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
|
||||
|
||||
bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
|
||||
const SmallVectorImpl<unsigned> &Ops) const {
|
||||
// Check switch flag
|
||||
// Check switch flag
|
||||
if (NoFusing) return 0;
|
||||
|
||||
if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
|
||||
switch (MI->getOpcode()) {
|
||||
default: return false;
|
||||
case X86::TEST8rr:
|
||||
case X86::TEST8rr:
|
||||
case X86::TEST16rr:
|
||||
case X86::TEST32rr:
|
||||
case X86::TEST64rr:
|
||||
@ -2550,7 +2550,7 @@ bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
|
||||
// instruction is different than folding it other places. It requires
|
||||
// replacing the *two* registers with the memory location.
|
||||
const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
|
||||
if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
|
||||
if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
|
||||
OpcodeTablePtr = &RegOp2MemOpTable2Addr;
|
||||
} else if (OpNum == 0) { // If operand 0
|
||||
switch (Opc) {
|
||||
@ -2566,7 +2566,7 @@ bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
|
||||
} else if (OpNum == 2) {
|
||||
OpcodeTablePtr = &RegOp2MemOpTable2;
|
||||
}
|
||||
|
||||
|
||||
if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
|
||||
return true;
|
||||
return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops);
|
||||
@ -2636,7 +2636,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
|
||||
// Emit the data processing instruction.
|
||||
MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
|
||||
MachineInstrBuilder MIB(DataMI);
|
||||
|
||||
|
||||
if (FoldedStore)
|
||||
MIB.addReg(Reg, RegState::Define);
|
||||
for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
|
||||
@ -3156,11 +3156,11 @@ namespace {
|
||||
PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
|
||||
else
|
||||
PC = GlobalBaseReg;
|
||||
|
||||
|
||||
// Operand of MovePCtoStack is completely ignored by asm printer. It's
|
||||
// only used in JIT code emission as displacement to pc.
|
||||
BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
|
||||
|
||||
|
||||
// If we're using vanilla 'GOT' PIC style, we should use relative addressing
|
||||
// not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
|
||||
if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
|
||||
|
||||
@ -36,7 +36,7 @@ def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
|
||||
SDTCisSameAs<0, 3>,
|
||||
SDTCisInt<0>, SDTCisVT<1, i32>]>;
|
||||
|
||||
// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
|
||||
// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
|
||||
def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
|
||||
[SDTCisSameAs<0, 2>,
|
||||
SDTCisSameAs<0, 3>,
|
||||
@ -1612,4 +1612,3 @@ def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>;
|
||||
def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>;
|
||||
def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>;
|
||||
def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;
|
||||
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
//===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
|
||||
//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file describes the X86 Register file, defining the registers themselves,
|
||||
@ -34,8 +34,8 @@ let Namespace = "X86" in {
|
||||
// because the register file generator is smart enough to figure out that
|
||||
// AL aliases AX if we tell it that AX aliased AL (for example).
|
||||
|
||||
// Dwarf numbering is different for 32-bit and 64-bit, and there are
|
||||
// variations by target as well. Currently the first entry is for X86-64,
|
||||
// Dwarf numbering is different for 32-bit and 64-bit, and there are
|
||||
// variations by target as well. Currently the first entry is for X86-64,
|
||||
// second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
|
||||
// and debug information on X86-32/Darwin)
|
||||
|
||||
@ -81,7 +81,7 @@ let Namespace = "X86" in {
|
||||
def SP : RegisterWithSubRegs<"sp", [SPL]>, DwarfRegNum<[7, 5, 4]>;
|
||||
}
|
||||
def IP : Register<"ip">, DwarfRegNum<[16]>;
|
||||
|
||||
|
||||
// X86-64 only
|
||||
let SubRegIndices = [sub_8bit] in {
|
||||
def R8W : RegisterWithSubRegs<"r8w", [R8B]>, DwarfRegNum<[8, -2, -2]>;
|
||||
@ -103,8 +103,8 @@ let Namespace = "X86" in {
|
||||
def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[5, 7, 7]>;
|
||||
def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[6, 4, 5]>;
|
||||
def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[7, 5, 4]>;
|
||||
def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[16, 8, 8]>;
|
||||
|
||||
def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[16, 8, 8]>;
|
||||
|
||||
// X86-64 only
|
||||
def R8D : RegisterWithSubRegs<"r8d", [R8W]>, DwarfRegNum<[8, -2, -2]>;
|
||||
def R9D : RegisterWithSubRegs<"r9d", [R9W]>, DwarfRegNum<[9, -2, -2]>;
|
||||
@ -208,7 +208,7 @@ let Namespace = "X86" in {
|
||||
def ST4 : Register<"st(4)">, DwarfRegNum<[37, 16, 15]>;
|
||||
def ST5 : Register<"st(5)">, DwarfRegNum<[38, 17, 16]>;
|
||||
def ST6 : Register<"st(6)">, DwarfRegNum<[39, 18, 17]>;
|
||||
def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>;
|
||||
def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>;
|
||||
|
||||
// Status flags register
|
||||
def EFLAGS : Register<"flags">;
|
||||
@ -220,7 +220,7 @@ let Namespace = "X86" in {
|
||||
def ES : Register<"es">;
|
||||
def FS : Register<"fs">;
|
||||
def GS : Register<"gs">;
|
||||
|
||||
|
||||
// Debug registers
|
||||
def DR0 : Register<"dr0">;
|
||||
def DR1 : Register<"dr1">;
|
||||
@ -230,7 +230,7 @@ let Namespace = "X86" in {
|
||||
def DR5 : Register<"dr5">;
|
||||
def DR6 : Register<"dr6">;
|
||||
def DR7 : Register<"dr7">;
|
||||
|
||||
|
||||
// Control registers
|
||||
def CR0 : Register<"cr0">;
|
||||
def CR1 : Register<"cr1">;
|
||||
@ -261,10 +261,10 @@ let Namespace = "X86" in {
|
||||
// implicitly defined to be the register allocation order.
|
||||
//
|
||||
|
||||
// List call-clobbered registers before callee-save registers. RBX, RBP, (and
|
||||
// List call-clobbered registers before callee-save registers. RBX, RBP, (and
|
||||
// R12, R13, R14, and R15 for X86-64) are callee-save registers.
|
||||
// In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
|
||||
// R8B, ... R15B.
|
||||
// R8B, ... R15B.
|
||||
// Allocate R12 and R13 last, as these require an extra byte when
|
||||
// encoded in x86_64 instructions.
|
||||
// FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in
|
||||
|
||||
@ -22,4 +22,3 @@ entry:
|
||||
%retval = tail call fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in2,i32 %tmp)
|
||||
ret i32 %retval
|
||||
}
|
||||
|
||||
|
||||
@ -28,15 +28,15 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) {
|
||||
isPredicable = false;
|
||||
hasOptionalDef = false;
|
||||
isVariadic = false;
|
||||
|
||||
|
||||
DagInit *OutDI = R->getValueAsDag("OutOperandList");
|
||||
|
||||
|
||||
if (DefInit *Init = dynamic_cast<DefInit*>(OutDI->getOperator())) {
|
||||
if (Init->getDef()->getName() != "outs")
|
||||
throw R->getName() + ": invalid def name for output list: use 'outs'";
|
||||
} else
|
||||
throw R->getName() + ": invalid output list: use 'outs'";
|
||||
|
||||
|
||||
NumDefs = OutDI->getNumArgs();
|
||||
|
||||
DagInit *InDI = R->getValueAsDag("InOperandList");
|
||||
@ -45,7 +45,7 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) {
|
||||
throw R->getName() + ": invalid def name for input list: use 'ins'";
|
||||
} else
|
||||
throw R->getName() + ": invalid input list: use 'ins'";
|
||||
|
||||
|
||||
unsigned MIOperandNo = 0;
|
||||
std::set<std::string> OperandNames;
|
||||
for (unsigned i = 0, e = InDI->getNumArgs()+OutDI->getNumArgs(); i != e; ++i){
|
||||
@ -58,11 +58,11 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) {
|
||||
ArgInit = InDI->getArg(i-NumDefs);
|
||||
ArgName = InDI->getArgName(i-NumDefs);
|
||||
}
|
||||
|
||||
|
||||
DefInit *Arg = dynamic_cast<DefInit*>(ArgInit);
|
||||
if (!Arg)
|
||||
throw "Illegal operand for the '" + R->getName() + "' instruction!";
|
||||
|
||||
|
||||
Record *Rec = Arg->getDef();
|
||||
std::string PrintMethod = "printOperand";
|
||||
std::string EncoderMethod;
|
||||
@ -73,19 +73,19 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) {
|
||||
// If there is an explicit encoder method, use it.
|
||||
EncoderMethod = Rec->getValueAsString("EncoderMethod");
|
||||
MIOpInfo = Rec->getValueAsDag("MIOperandInfo");
|
||||
|
||||
|
||||
// Verify that MIOpInfo has an 'ops' root value.
|
||||
if (!dynamic_cast<DefInit*>(MIOpInfo->getOperator()) ||
|
||||
dynamic_cast<DefInit*>(MIOpInfo->getOperator())
|
||||
->getDef()->getName() != "ops")
|
||||
throw "Bad value for MIOperandInfo in operand '" + Rec->getName() +
|
||||
"'\n";
|
||||
|
||||
|
||||
// If we have MIOpInfo, then we have #operands equal to number of entries
|
||||
// in MIOperandInfo.
|
||||
if (unsigned NumArgs = MIOpInfo->getNumArgs())
|
||||
NumOps = NumArgs;
|
||||
|
||||
|
||||
if (Rec->isSubClassOf("PredicateOperand"))
|
||||
isPredicable = true;
|
||||
else if (Rec->isSubClassOf("OptionalDefOperand"))
|
||||
@ -97,7 +97,7 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) {
|
||||
Rec->getName() != "ptr_rc" && Rec->getName() != "unknown")
|
||||
throw "Unknown operand class '" + Rec->getName() +
|
||||
"' in '" + R->getName() + "' instruction!";
|
||||
|
||||
|
||||
// Check that the operand has a name and that it's unique.
|
||||
if (ArgName.empty())
|
||||
throw "In instruction '" + R->getName() + "', operand #" + utostr(i) +
|
||||
@ -105,13 +105,13 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) {
|
||||
if (!OperandNames.insert(ArgName).second)
|
||||
throw "In instruction '" + R->getName() + "', operand #" + utostr(i) +
|
||||
" has the same name as a previous operand!";
|
||||
|
||||
|
||||
OperandList.push_back(OperandInfo(Rec, ArgName, PrintMethod, EncoderMethod,
|
||||
MIOperandNo, NumOps, MIOpInfo));
|
||||
MIOperandNo += NumOps;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
// Make sure the constraints list for each operand is large enough to hold
|
||||
// constraint info, even if none is present.
|
||||
for (unsigned i = 0, e = OperandList.size(); i != e; ++i)
|
||||
@ -126,7 +126,7 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) {
|
||||
unsigned CGIOperandList::getOperandNamed(StringRef Name) const {
|
||||
unsigned OpIdx;
|
||||
if (hasOperandNamed(Name, OpIdx)) return OpIdx;
|
||||
throw "'" + TheDef->getName() + "' does not have an operand named '$" +
|
||||
throw "'" + TheDef->getName() + "' does not have an operand named '$" +
|
||||
Name.str() + "'!";
|
||||
}
|
||||
|
||||
@ -147,10 +147,10 @@ std::pair<unsigned,unsigned>
|
||||
CGIOperandList::ParseOperandName(const std::string &Op, bool AllowWholeOp) {
|
||||
if (Op.empty() || Op[0] != '$')
|
||||
throw TheDef->getName() + ": Illegal operand name: '" + Op + "'";
|
||||
|
||||
|
||||
std::string OpName = Op.substr(1);
|
||||
std::string SubOpName;
|
||||
|
||||
|
||||
// Check to see if this is $foo.bar.
|
||||
std::string::size_type DotIdx = OpName.find_first_of(".");
|
||||
if (DotIdx != std::string::npos) {
|
||||
@ -159,30 +159,30 @@ CGIOperandList::ParseOperandName(const std::string &Op, bool AllowWholeOp) {
|
||||
throw TheDef->getName() + ": illegal empty suboperand name in '" +Op +"'";
|
||||
OpName = OpName.substr(0, DotIdx);
|
||||
}
|
||||
|
||||
|
||||
unsigned OpIdx = getOperandNamed(OpName);
|
||||
|
||||
|
||||
if (SubOpName.empty()) { // If no suboperand name was specified:
|
||||
// If one was needed, throw.
|
||||
if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp &&
|
||||
SubOpName.empty())
|
||||
throw TheDef->getName() + ": Illegal to refer to"
|
||||
" whole operand part of complex operand '" + Op + "'";
|
||||
|
||||
|
||||
// Otherwise, return the operand.
|
||||
return std::make_pair(OpIdx, 0U);
|
||||
}
|
||||
|
||||
|
||||
// Find the suboperand number involved.
|
||||
DagInit *MIOpInfo = OperandList[OpIdx].MIOperandInfo;
|
||||
if (MIOpInfo == 0)
|
||||
throw TheDef->getName() + ": unknown suboperand name in '" + Op + "'";
|
||||
|
||||
|
||||
// Find the operand with the right name.
|
||||
for (unsigned i = 0, e = MIOpInfo->getNumArgs(); i != e; ++i)
|
||||
if (MIOpInfo->getArgName(i) == SubOpName)
|
||||
return std::make_pair(OpIdx, i);
|
||||
|
||||
|
||||
// Otherwise, didn't find it!
|
||||
throw TheDef->getName() + ": unknown suboperand name in '" + Op + "'";
|
||||
}
|
||||
@ -199,7 +199,7 @@ static void ParseConstraint(const std::string &CStr, CGIOperandList &Ops) {
|
||||
throw "Illegal format for @earlyclobber constraint: '" + CStr + "'";
|
||||
Name = Name.substr(wpos);
|
||||
std::pair<unsigned,unsigned> Op = Ops.ParseOperandName(Name, false);
|
||||
|
||||
|
||||
// Build the string for the operand
|
||||
if (!Ops[Op.first].Constraints[Op.second].isNone())
|
||||
throw "Operand '" + Name + "' cannot have multiple constraints!";
|
||||
@ -207,33 +207,33 @@ static void ParseConstraint(const std::string &CStr, CGIOperandList &Ops) {
|
||||
CGIOperandList::ConstraintInfo::getEarlyClobber();
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
// Only other constraint is "TIED_TO" for now.
|
||||
std::string::size_type pos = CStr.find_first_of('=');
|
||||
assert(pos != std::string::npos && "Unrecognized constraint");
|
||||
start = CStr.find_first_not_of(" \t");
|
||||
std::string Name = CStr.substr(start, pos - start);
|
||||
|
||||
|
||||
// TIED_TO: $src1 = $dst
|
||||
wpos = Name.find_first_of(" \t");
|
||||
if (wpos == std::string::npos)
|
||||
throw "Illegal format for tied-to constraint: '" + CStr + "'";
|
||||
std::string DestOpName = Name.substr(0, wpos);
|
||||
std::pair<unsigned,unsigned> DestOp = Ops.ParseOperandName(DestOpName, false);
|
||||
|
||||
|
||||
Name = CStr.substr(pos+1);
|
||||
wpos = Name.find_first_not_of(" \t");
|
||||
if (wpos == std::string::npos)
|
||||
throw "Illegal format for tied-to constraint: '" + CStr + "'";
|
||||
|
||||
|
||||
std::pair<unsigned,unsigned> SrcOp =
|
||||
Ops.ParseOperandName(Name.substr(wpos), false);
|
||||
if (SrcOp > DestOp)
|
||||
throw "Illegal tied-to operand constraint '" + CStr + "'";
|
||||
|
||||
|
||||
|
||||
|
||||
unsigned FlatOpNo = Ops.getFlattenedOperandNumber(SrcOp);
|
||||
|
||||
|
||||
if (!Ops[DestOp.first].Constraints[DestOp.second].isNone())
|
||||
throw "Operand '" + DestOpName + "' cannot have multiple constraints!";
|
||||
Ops[DestOp.first].Constraints[DestOp.second] =
|
||||
@ -242,16 +242,16 @@ static void ParseConstraint(const std::string &CStr, CGIOperandList &Ops) {
|
||||
|
||||
static void ParseConstraints(const std::string &CStr, CGIOperandList &Ops) {
|
||||
if (CStr.empty()) return;
|
||||
|
||||
|
||||
const std::string delims(",");
|
||||
std::string::size_type bidx, eidx;
|
||||
|
||||
|
||||
bidx = CStr.find_first_not_of(delims);
|
||||
while (bidx != std::string::npos) {
|
||||
eidx = CStr.find_first_of(delims, bidx);
|
||||
if (eidx == std::string::npos)
|
||||
eidx = CStr.length();
|
||||
|
||||
|
||||
ParseConstraint(CStr.substr(bidx, eidx - bidx), Ops);
|
||||
bidx = CStr.find_first_not_of(delims, eidx);
|
||||
}
|
||||
@ -262,16 +262,16 @@ void CGIOperandList::ProcessDisableEncoding(std::string DisableEncoding) {
|
||||
std::string OpName;
|
||||
tie(OpName, DisableEncoding) = getToken(DisableEncoding, " ,\t");
|
||||
if (OpName.empty()) break;
|
||||
|
||||
|
||||
// Figure out which operand this is.
|
||||
std::pair<unsigned,unsigned> Op = ParseOperandName(OpName, false);
|
||||
|
||||
|
||||
// Mark the operand as not-to-be encoded.
|
||||
if (Op.second >= OperandList[Op.first].DoNotEncode.size())
|
||||
OperandList[Op.first].DoNotEncode.resize(Op.second+1);
|
||||
OperandList[Op.first].DoNotEncode[Op.second] = true;
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -325,11 +325,11 @@ CodeGenInstruction::CodeGenInstruction(Record *R) : TheDef(R), Operands(R) {
|
||||
MVT::SimpleValueType CodeGenInstruction::
|
||||
HasOneImplicitDefWithKnownVT(const CodeGenTarget &TargetInfo) const {
|
||||
if (ImplicitDefs.empty()) return MVT::Other;
|
||||
|
||||
|
||||
// Check to see if the first implicit def has a resolvable type.
|
||||
Record *FirstImplicitDef = ImplicitDefs[0];
|
||||
assert(FirstImplicitDef->isSubClassOf("Register"));
|
||||
const std::vector<MVT::SimpleValueType> &RegVTs =
|
||||
const std::vector<MVT::SimpleValueType> &RegVTs =
|
||||
TargetInfo.getRegisterVTs(FirstImplicitDef);
|
||||
if (RegVTs.size() == 1)
|
||||
return RegVTs[0];
|
||||
@ -342,7 +342,7 @@ HasOneImplicitDefWithKnownVT(const CodeGenTarget &TargetInfo) const {
|
||||
std::string CodeGenInstruction::
|
||||
FlattenAsmStringVariants(StringRef Cur, unsigned Variant) {
|
||||
std::string Res = "";
|
||||
|
||||
|
||||
for (;;) {
|
||||
// Find the start of the next variant string.
|
||||
size_t VariantsStart = 0;
|
||||
@ -351,14 +351,14 @@ FlattenAsmStringVariants(StringRef Cur, unsigned Variant) {
|
||||
(VariantsStart == 0 || (Cur[VariantsStart-1] != '$' &&
|
||||
Cur[VariantsStart-1] != '\\')))
|
||||
break;
|
||||
|
||||
|
||||
// Add the prefix to the result.
|
||||
Res += Cur.slice(0, VariantsStart);
|
||||
if (VariantsStart == Cur.size())
|
||||
break;
|
||||
|
||||
|
||||
++VariantsStart; // Skip the '{'.
|
||||
|
||||
|
||||
// Scan to the end of the variants string.
|
||||
size_t VariantsEnd = VariantsStart;
|
||||
unsigned NestedBraces = 1;
|
||||
@ -369,18 +369,18 @@ FlattenAsmStringVariants(StringRef Cur, unsigned Variant) {
|
||||
} else if (Cur[VariantsEnd] == '{')
|
||||
++NestedBraces;
|
||||
}
|
||||
|
||||
|
||||
// Select the Nth variant (or empty).
|
||||
StringRef Selection = Cur.slice(VariantsStart, VariantsEnd);
|
||||
for (unsigned i = 0; i != Variant; ++i)
|
||||
Selection = Selection.split('|').second;
|
||||
Res += Selection.split('|').first;
|
||||
|
||||
|
||||
assert(VariantsEnd != Cur.size() &&
|
||||
"Unterminated variants in assembly string!");
|
||||
Cur = Cur.substr(VariantsEnd + 1);
|
||||
}
|
||||
|
||||
|
||||
return Res;
|
||||
}
|
||||
|
||||
@ -399,7 +399,7 @@ CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
|
||||
throw TGError(R->getLoc(), "result of inst alias should be an instruction");
|
||||
|
||||
ResultInst = &T.getInstruction(DI->getDef());
|
||||
|
||||
|
||||
// NameClass - If argument names are repeated, we need to verify they have
|
||||
// the same class.
|
||||
StringMap<Record*> NameClass;
|
||||
@ -417,7 +417,7 @@ CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
|
||||
ADI->getDef()->getName() + "!");
|
||||
Entry = ADI->getDef();
|
||||
}
|
||||
|
||||
|
||||
// Decode and validate the arguments of the result.
|
||||
unsigned AliasOpNo = 0;
|
||||
for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
|
||||
@ -430,8 +430,8 @@ CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
|
||||
" arguments, but " + ResultInst->TheDef->getName() +
|
||||
" instruction expects " +
|
||||
utostr(ResultInst->Operands.size()) + " operands!");
|
||||
|
||||
|
||||
|
||||
|
||||
Init *Arg = Result->getArg(AliasOpNo);
|
||||
Record *ResultOpRec = ResultInst->Operands[i].Rec;
|
||||
|
||||
@ -441,16 +441,16 @@ CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
|
||||
if (!Result->getArgName(AliasOpNo).empty())
|
||||
throw TGError(R->getLoc(), "result fixed register argument must "
|
||||
"not have a name!");
|
||||
|
||||
|
||||
if (!ResultOpRec->isSubClassOf("RegisterClass"))
|
||||
throw TGError(R->getLoc(), "result fixed register argument is not "
|
||||
"passed to a RegisterClass operand!");
|
||||
|
||||
|
||||
if (!T.getRegisterClass(ResultOpRec).containsRegister(ADI->getDef()))
|
||||
throw TGError(R->getLoc(), "fixed register " +ADI->getDef()->getName()
|
||||
+ " is not a member of the " + ResultOpRec->getName() +
|
||||
" register class!");
|
||||
|
||||
|
||||
// Now that it is validated, add it.
|
||||
ResultOperands.push_back(ResultOperand(ADI->getDef()));
|
||||
ResultInstOperandIndex.push_back(i);
|
||||
@ -474,7 +474,7 @@ CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// If the operand is a record, it must have a name, and the record type must
|
||||
// match up with the instruction's argument type.
|
||||
if (DefInit *ADI = dynamic_cast<DefInit*>(Arg)) {
|
||||
@ -485,9 +485,9 @@ CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
|
||||
if (ADI->getDef() != ResultOpRec)
|
||||
throw TGError(R->getLoc(), "result argument #" + utostr(AliasOpNo) +
|
||||
" declared with class " + ADI->getDef()->getName() +
|
||||
", instruction operand is class " +
|
||||
", instruction operand is class " +
|
||||
ResultOpRec->getName());
|
||||
|
||||
|
||||
// Now that it is validated, add it.
|
||||
ResultOperands.push_back(ResultOperand(Result->getArgName(AliasOpNo),
|
||||
ADI->getDef()));
|
||||
@ -495,7 +495,7 @@ CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
|
||||
++AliasOpNo;
|
||||
continue;
|
||||
}
|
||||
|
||||
|
||||
if (IntInit *II = dynamic_cast<IntInit*>(Arg)) {
|
||||
// Integer arguments can't have names.
|
||||
if (!Result->getArgName(AliasOpNo).empty())
|
||||
@ -503,7 +503,7 @@ CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
|
||||
" must not have a name!");
|
||||
if (ResultInst->Operands[i].MINumOperands != 1 ||
|
||||
!ResultOpRec->isSubClassOf("Operand"))
|
||||
throw TGError(R->getLoc(), "invalid argument class " +
|
||||
throw TGError(R->getLoc(), "invalid argument class " +
|
||||
ResultOpRec->getName() +
|
||||
" for integer result operand!");
|
||||
ResultOperands.push_back(ResultOperand(II->getValue()));
|
||||
@ -514,7 +514,7 @@ CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
|
||||
|
||||
throw TGError(R->getLoc(), "result of inst alias has unknown operand type");
|
||||
}
|
||||
|
||||
|
||||
if (AliasOpNo != Result->getNumArgs())
|
||||
throw TGError(R->getLoc(), "result has " + utostr(Result->getNumArgs()) +
|
||||
" arguments, but " + ResultInst->TheDef->getName() +
|
||||
|
||||
Loading…
Reference in New Issue
Block a user