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Completely eliminate the isVoid TSFlag, shifting over all other fields
llvm-svn: 7636
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@ -26,10 +26,10 @@ def X86InstrInfo : InstrInfo {
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// Define how we want to layout our TargetSpecific information field... This
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// should be kept up-to-date with the fields in the X86InstrInfo.h file.
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let TSFlagsFields = ["FormBits", "hasOpSizePrefix", "Prefix",
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"TypeBits", "FPFormBits", "printImplicitUses", "Opcode"];
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let TSFlagsShifts = [ 0, 6, 7,
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11, 14, 17, 18];
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let TSFlagsFields = ["FormBits" , "hasOpSizePrefix" , "Prefix", "TypeBits",
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"FPFormBits", "printImplicitUses", "Opcode"];
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let TSFlagsShifts = [ 0, 5, 6, 10,
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13, 16, 17];
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}
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def X86 : Target {
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@ -71,74 +71,75 @@ namespace X86II {
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//===------------------------------------------------------------------===//
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// Actual flags...
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/// Void - Set if this instruction produces no value
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Void = 1 << 5,
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// OpSize - Set if this instruction requires an operand size prefix (0x66),
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// which most often indicates that the instruction operates on 16 bit data
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// instead of 32 bit data.
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OpSize = 1 << 6,
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OpSize = 1 << 5,
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// Op0Mask - There are several prefix bytes that are used to form two byte
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// opcodes. These are currently 0x0F, and 0xD8-0xDF. This mask is used to
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// obtain the setting of this field. If no bits in this field is set, there
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// is no prefix byte for obtaining a multibyte opcode.
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//
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Op0Mask = 0xF << 7,
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Op0Shift = 7,
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Op0Shift = 6,
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Op0Mask = 0xF << Op0Shift,
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// TB - TwoByte - Set if this instruction has a two byte opcode, which
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// starts with a 0x0F byte before the real opcode.
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TB = 1 << 7,
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TB = 1 << Op0Shift,
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// D8-DF - These escape opcodes are used by the floating point unit. These
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// values must remain sequential.
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D8 = 2 << 7, D9 = 3 << 7, DA = 4 << 7, DB = 5 << 7,
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DC = 6 << 7, DD = 7 << 7, DE = 8 << 7, DF = 9 << 7,
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D8 = 2 << Op0Shift, D9 = 3 << Op0Shift,
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DA = 4 << Op0Shift, DB = 5 << Op0Shift,
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DC = 6 << Op0Shift, DD = 7 << Op0Shift,
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DE = 8 << Op0Shift, DF = 9 << Op0Shift,
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//===------------------------------------------------------------------===//
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// This three-bit field describes the size of a memory operand. Zero is
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// unused so that we can tell if we forgot to set a value.
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Arg8 = 1 << 11,
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Arg16 = 2 << 11,
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Arg32 = 3 << 11,
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Arg64 = 4 << 11, // 64 bit int argument for FILD64
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ArgF32 = 5 << 11,
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ArgF64 = 6 << 11,
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ArgF80 = 7 << 11,
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ArgMask = 7 << 11,
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ArgShift = 10,
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ArgMask = 7 << ArgShift,
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Arg8 = 1 << ArgShift,
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Arg16 = 2 << ArgShift,
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Arg32 = 3 << ArgShift,
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Arg64 = 4 << ArgShift, // 64 bit int argument for FILD64
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ArgF32 = 5 << ArgShift,
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ArgF64 = 6 << ArgShift,
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ArgF80 = 7 << ArgShift,
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//===------------------------------------------------------------------===//
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// FP Instruction Classification... Zero is non-fp instruction.
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// FPTypeMask - Mask for all of the FP types...
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FPTypeShift = 13,
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FPTypeMask = 7 << FPTypeShift,
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// ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
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ZeroArgFP = 1 << 14,
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ZeroArgFP = 1 << FPTypeShift,
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// OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
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OneArgFP = 2 << 14,
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OneArgFP = 2 << FPTypeShift,
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// OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
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// result back to ST(0). For example, fcos, fsqrt, etc.
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//
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OneArgFPRW = 3 << 14,
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OneArgFPRW = 3 << FPTypeShift,
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// TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
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// explicit argument, storing the result to either ST(0) or the implicit
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// argument. For example: fadd, fsub, fmul, etc...
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TwoArgFP = 4 << 14,
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TwoArgFP = 4 << FPTypeShift,
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// SpecialFP - Special instruction forms. Dispatch by opcode explicitly.
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SpecialFP = 5 << 14,
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// FPTypeMask - Mask for all of the FP types...
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FPTypeMask = 7 << 14,
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SpecialFP = 5 << FPTypeShift,
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// PrintImplUses - Print out implicit uses in the assembly output.
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PrintImplUses = 1 << 17,
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PrintImplUses = 1 << 16,
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OpcodeMask = 0xFF << 18,
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OpcodeShift = 18,
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// Bits 26 -> 31 are unused
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OpcodeShift = 17,
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OpcodeMask = 0xFF << OpcodeShift,
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// Bits 25 -> 31 are unused
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};
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}
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