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initial code for forming an FGETSIGN node. This is disabled until

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legalizer support goes in.

llvm-svn: 45323
This commit is contained in:
Chris Lattner 2007-12-22 21:35:38 +00:00
parent 24b2a6de5c
commit 084002dcb0
1 changed files with 26 additions and 0 deletions
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26
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -944,6 +944,32 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
KnownZero |= ~InMask & DemandedMask;
break;
}
case ISD::FGETSIGN:
// All bits are zero except the low bit.
KnownZero = MVT::getIntVTBitMask(Op.getValueType()) ^ 1;
break;
case ISD::BIT_CONVERT:
#if 0
// If this is an FP->Int bitcast and if the sign bit is the only thing that
// is demanded, turn this into a FGETSIGN.
if (DemandedMask == MVT::getIntVTSignBit(Op.getValueType()) &&
MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
!MVT::isVector(Op.getOperand(0).getValueType())) {
// Only do this xform if FGETSIGN is valid or if before legalize.
if (!TLO.AfterLegalize ||
isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
// Make a FGETSIGN + SHL to move the sign bit into the appropriate
// place. We expect the SHL to be eliminated by other optimizations.
SDOperand Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
Op.getOperand(0));
unsigned ShVal = MVT::getSizeInBits(Op.getValueType())-1;
SDOperand ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
Sign, ShAmt));
}
}
#endif
break;
case ISD::ADD:
case ISD::SUB:
case ISD::INTRINSIC_WO_CHAIN: