RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-23 12:24:34 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl).

Browse Source 
llvm-svn: 48027
This commit is contained in:
Chris Lattner 2008-03-07 20:18:24 +00:00
parent 2f13ccc181
commit 08ec4919ea
2 changed files with 16 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
lib/Target/PowerPC/PPCInstr64Bit.td
View File

@ -289,13 +289,13 @@ def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2),
def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
"sld $rA, $rS, $rB", IntRotateD,
[(set G8RC:$rA, (shl G8RC:$rS, GPRC:$rB))]>, isPPC64;
[(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64;
def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
"srd $rA, $rS, $rB", IntRotateD,
[(set G8RC:$rA, (srl G8RC:$rS, GPRC:$rB))]>, isPPC64;
[(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64;
def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
"srad $rA, $rS, $rB", IntRotateD,
[(set G8RC:$rA, (sra G8RC:$rS, GPRC:$rB))]>, isPPC64;
[(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64;
def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
"extsb $rA, $rS", IntGeneral,
@ -579,6 +579,16 @@ def : Pat<(extloadi32 iaddr:$src),
def : Pat<(extloadi32 xaddr:$src),
(LWZX8 xaddr:$src)>;
// Standard shifts. These are represented separately from the real shifts above
// so that we can distinguish between shifts that allow 6-bit and 7-bit shift
// amounts.
def : Pat<(sra G8RC:$rS, GPRC:$rB),
(SRAD G8RC:$rS, GPRC:$rB)>;
def : Pat<(srl G8RC:$rS, GPRC:$rB),
(SRD G8RC:$rS, GPRC:$rB)>;
def : Pat<(shl G8RC:$rS, GPRC:$rB),
(SLD G8RC:$rS, GPRC:$rB)>;
// SHL/SRL
def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
(RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;

6
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -81,9 +81,9 @@ def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
// amounts. These nodes are generated by the multi-precision shift code.
def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntBinOp>;
def PPCsra : SDNode<"PPCISD::SRA" , SDTIntBinOp>;
def PPCshl : SDNode<"PPCISD::SHL" , SDTIntBinOp>;
def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,