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Doxygenify method comments.
Try to improve method comments a little. Get rid of some excess whitespace; put braces on previous line when possible. Add stub for method to verify the work of saveState(). llvm-svn: 9385
This commit is contained in:
Brian Gaeke
parent
307255971c
commit
08fc8bcce4
@ -73,18 +73,13 @@ void PhyRegAlloc::getAnalysisUsage(AnalysisUsage &AU) const {
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}
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//----------------------------------------------------------------------------
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// This method initially creates interference graphs (one in each reg class)
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// and IGNodeList (one in each IG). The actual nodes will be pushed later.
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//----------------------------------------------------------------------------
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/// Initialize interference graphs (one in each reg class) and IGNodeLists
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/// (one in each IG). The actual nodes will be pushed later.
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///
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void PhyRegAlloc::createIGNodeListsAndIGs() {
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if (DEBUG_RA >= RA_DEBUG_LiveRanges) std::cerr << "Creating LR lists ...\n";
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// hash map iterator
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LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
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// hash map end
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LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
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for (; HMI != HMIEnd ; ++HMI ) {
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@ -114,15 +109,12 @@ void PhyRegAlloc::createIGNodeListsAndIGs() {
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}
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//----------------------------------------------------------------------------
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// This method will add all interferences at for a given instruction.
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// Interference occurs only if the LR of Def (Inst or Arg) is of the same reg
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// class as that of live var. The live var passed to this function is the
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// LVset AFTER the instruction
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//----------------------------------------------------------------------------
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void PhyRegAlloc::addInterference(const Value *Def,
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const ValueSet *LVSet,
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/// Add all interferences for a given instruction. Interference occurs only
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/// if the LR of Def (Inst or Arg) is of the same reg class as that of live
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/// var. The live var passed to this function is the LVset AFTER the
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/// instruction.
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///
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void PhyRegAlloc::addInterference(const Value *Def, const ValueSet *LVSet,
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bool isCallInst) {
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ValueSet::const_iterator LIt = LVSet->begin();
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@ -153,13 +145,11 @@ void PhyRegAlloc::addInterference(const Value *Def,
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}
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//----------------------------------------------------------------------------
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// For a call instruction, this method sets the CallInterference flag in
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// the LR of each variable live int the Live Variable Set live after the
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// call instruction (except the return value of the call instruction - since
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// the return value does not interfere with that call itself).
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//----------------------------------------------------------------------------
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/// For a call instruction, this method sets the CallInterference flag in
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/// the LR of each variable live in the Live Variable Set live after the
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/// call instruction (except the return value of the call instruction - since
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/// the return value does not interfere with that call itself).
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///
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void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
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const ValueSet *LVSetAft) {
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if (DEBUG_RA >= RA_DEBUG_Interference)
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@ -211,14 +201,11 @@ void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
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}
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//----------------------------------------------------------------------------
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// This method will walk thru code and create interferences in the IG of
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// each RegClass. Also, this method calculates the spill cost of each
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// Live Range (it is done in this method to save another pass over the code).
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//----------------------------------------------------------------------------
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void PhyRegAlloc::buildInterferenceGraphs()
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{
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/// Create interferences in the IG of each RegClass, and calculate the spill
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/// cost of each Live Range (it is done in this method to save another pass
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/// over the code).
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///
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void PhyRegAlloc::buildInterferenceGraphs() {
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if (DEBUG_RA >= RA_DEBUG_Interference)
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std::cerr << "Creating interference graphs ...\n";
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@ -242,7 +229,7 @@ void PhyRegAlloc::buildInterferenceGraphs()
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const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB);
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bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
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if (isCallInst ) {
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if (isCallInst) {
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// set the isCallInterference flag of each live range which extends
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// across this call instruction. This information is used by graph
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// coloring algorithm to avoid allocating volatile colors to live ranges
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@ -261,7 +248,10 @@ void PhyRegAlloc::buildInterferenceGraphs()
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if (LR) LR->addSpillCost(BBLoopDepthCost);
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}
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// if there are multiple defs in this instruction e.g. in SETX
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// Mark all operands of pseudo-instructions as interfering with one
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// another. This must be done because pseudo-instructions may be
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// expanded to multiple instructions by the assembler, so all the
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// operands must get distinct registers.
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if (TM.getInstrInfo().isPseudoInstr(MInst->getOpCode()))
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addInterf4PseudoInstr(MInst);
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@ -285,13 +275,9 @@ void PhyRegAlloc::buildInterferenceGraphs()
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}
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//--------------------------------------------------------------------------
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// Pseudo-instructions may be expanded to multiple instructions by the
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// assembler. Consequently, all the operands must get distinct registers.
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// Therefore, we mark all operands of a pseudo-instruction as interfering
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// with one another.
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//--------------------------------------------------------------------------
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/// Mark all operands of the given MachineInstr as interfering with one
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/// another.
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///
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void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
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bool setInterf = false;
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@ -325,10 +311,8 @@ void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
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}
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//----------------------------------------------------------------------------
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// This method adds interferences for incoming arguments to a function.
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//----------------------------------------------------------------------------
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/// Add interferences for incoming arguments to a function.
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///
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void PhyRegAlloc::addInterferencesForArgs() {
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// get the InSet of root BB
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const ValueSet &InSet = LVI->getInSetOfBB(&Fn->front());
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@ -338,68 +322,51 @@ void PhyRegAlloc::addInterferencesForArgs() {
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addInterference(AI, &InSet, false);
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if (DEBUG_RA >= RA_DEBUG_Interference)
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std::cerr << " - %% adding interference for argument " << RAV(AI) << "\n";
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std::cerr << " - %% adding interference for argument " << RAV(AI) << "\n";
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}
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}
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//----------------------------------------------------------------------------
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// This method is called after register allocation is complete to set the
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// allocated registers in the machine code. This code will add register numbers
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// to MachineOperands that contain a Value. Also it calls target specific
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// methods to produce caller saving instructions. At the end, it adds all
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// additional instructions produced by the register allocator to the
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// instruction stream.
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//----------------------------------------------------------------------------
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/// The following are utility functions used solely by updateMachineCode and
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/// the functions that it calls. They should probably be folded back into
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/// updateMachineCode at some point.
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///
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//-----------------------------
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// Utility functions used below
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//-----------------------------
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inline void
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InsertBefore(MachineInstr* newMI,
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MachineBasicBlock& MBB,
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MachineBasicBlock::iterator& MII)
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{
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// used by: updateMachineCode (1 time), PrependInstructions (1 time)
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inline void InsertBefore(MachineInstr* newMI, MachineBasicBlock& MBB,
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MachineBasicBlock::iterator& MII) {
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MII = MBB.insert(MII, newMI);
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++MII;
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}
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inline void
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InsertAfter(MachineInstr* newMI,
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MachineBasicBlock& MBB,
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MachineBasicBlock::iterator& MII)
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{
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// used by: AppendInstructions (1 time)
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inline void InsertAfter(MachineInstr* newMI, MachineBasicBlock& MBB,
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MachineBasicBlock::iterator& MII) {
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++MII; // insert before the next instruction
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MII = MBB.insert(MII, newMI);
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}
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inline void
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DeleteInstruction(MachineBasicBlock& MBB,
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MachineBasicBlock::iterator& MII)
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{
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// used by: updateMachineCode (1 time)
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inline void DeleteInstruction(MachineBasicBlock& MBB,
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MachineBasicBlock::iterator& MII) {
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MII = MBB.erase(MII);
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}
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inline void
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SubstituteInPlace(MachineInstr* newMI,
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MachineBasicBlock& MBB,
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MachineBasicBlock::iterator MII)
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{
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// used by: updateMachineCode (1 time)
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inline void SubstituteInPlace(MachineInstr* newMI, MachineBasicBlock& MBB,
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MachineBasicBlock::iterator MII) {
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*MII = newMI;
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}
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inline void
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PrependInstructions(std::vector<MachineInstr *> &IBef,
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MachineBasicBlock& MBB,
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MachineBasicBlock::iterator& MII,
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const std::string& msg)
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{
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if (!IBef.empty())
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{
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// used by: updateMachineCode (2 times)
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inline void PrependInstructions(std::vector<MachineInstr *> &IBef,
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MachineBasicBlock& MBB,
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MachineBasicBlock::iterator& MII,
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const std::string& msg) {
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if (!IBef.empty()) {
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MachineInstr* OrigMI = *MII;
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std::vector<MachineInstr *>::iterator AdIt;
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for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt)
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{
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for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt) {
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if (DEBUG_RA) {
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if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
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std::cerr << msg << "PREPENDed instr:\n " << **AdIt << "\n";
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@ -409,18 +376,15 @@ PrependInstructions(std::vector<MachineInstr *> &IBef,
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}
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}
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inline void
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AppendInstructions(std::vector<MachineInstr *> &IAft,
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MachineBasicBlock& MBB,
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MachineBasicBlock::iterator& MII,
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const std::string& msg)
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{
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if (!IAft.empty())
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{
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// used by: updateMachineCode (1 time)
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inline void AppendInstructions(std::vector<MachineInstr *> &IAft,
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MachineBasicBlock& MBB,
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MachineBasicBlock::iterator& MII,
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const std::string& msg) {
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if (!IAft.empty()) {
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MachineInstr* OrigMI = *MII;
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std::vector<MachineInstr *>::iterator AdIt;
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for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt )
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{
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for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
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if (DEBUG_RA) {
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if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
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std::cerr << msg << "APPENDed instr:\n " << **AdIt << "\n";
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@ -430,6 +394,10 @@ AppendInstructions(std::vector<MachineInstr *> &IAft,
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}
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}
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/// Set the registers for operands in the given MachineInstr, if a register was
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/// successfully allocated. Return true if any of its operands has been marked
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/// for spill.
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///
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bool PhyRegAlloc::markAllocatedRegs(MachineInstr* MInst)
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{
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bool instrNeedsSpills = false;
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@ -437,12 +405,10 @@ bool PhyRegAlloc::markAllocatedRegs(MachineInstr* MInst)
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// First, set the registers for operands in the machine instruction
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// if a register was successfully allocated. Do this first because we
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// will need to know which registers are already used by this instr'n.
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for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
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{
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for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
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MachineOperand& Op = MInst->getOperand(OpNum);
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if (Op.getType() == MachineOperand::MO_VirtualRegister ||
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Op.getType() == MachineOperand::MO_CCRegister)
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{
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Op.getType() == MachineOperand::MO_CCRegister) {
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const Value *const Val = Op.getVRegValue();
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if (const LiveRange* LR = LRI->getLiveRangeForValue(Val)) {
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// Remember if any operand needs spilling
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@ -460,9 +426,13 @@ bool PhyRegAlloc::markAllocatedRegs(MachineInstr* MInst)
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return instrNeedsSpills;
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}
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/// Mark allocated registers (using markAllocatedRegs()) on the instruction
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/// that MII points to. Then, if it's a call instruction, insert caller-saving
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/// code before and after it. Finally, insert spill code before and after it,
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/// using insertCode4SpilledLR().
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///
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void PhyRegAlloc::updateInstruction(MachineBasicBlock::iterator& MII,
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MachineBasicBlock &MBB)
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{
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MachineBasicBlock &MBB) {
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MachineInstr* MInst = *MII;
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unsigned Opcode = MInst->getOpCode();
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@ -493,12 +463,10 @@ void PhyRegAlloc::updateInstruction(MachineBasicBlock::iterator& MII,
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// registers. This must be done even for call return instructions
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// since those are not handled by the special code above.
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if (instrNeedsSpills)
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for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
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{
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for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
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MachineOperand& Op = MInst->getOperand(OpNum);
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if (Op.getType() == MachineOperand::MO_VirtualRegister ||
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Op.getType() == MachineOperand::MO_CCRegister)
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{
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Op.getType() == MachineOperand::MO_CCRegister) {
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const Value* Val = Op.getVRegValue();
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if (const LiveRange *LR = LRI->getLiveRangeForValue(Val))
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if (LR->isMarkedForSpill())
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@ -507,6 +475,10 @@ void PhyRegAlloc::updateInstruction(MachineBasicBlock::iterator& MII,
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} // for each operand
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}
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/// Iterate over all the MachineBasicBlocks in the current function and set
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/// the allocated registers for each instruction (using updateInstruction()),
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/// after register allocation is complete. Then move code out of delay slots.
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///
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void PhyRegAlloc::updateMachineCode()
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{
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// Insert any instructions needed at method entry
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@ -519,7 +491,6 @@ void PhyRegAlloc::updateMachineCode()
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for (MachineFunction::iterator BBI = MF->begin(), BBE = MF->end();
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BBI != BBE; ++BBI) {
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MachineBasicBlock &MBB = *BBI;
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// Iterate over all machine instructions in BB and mark operands with
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@ -546,8 +517,7 @@ void PhyRegAlloc::updateMachineCode()
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for (MachineBasicBlock::iterator MII = MBB.begin();
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MII != MBB.end(); ++MII)
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if (unsigned delaySlots =
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TM.getInstrInfo().getNumDelaySlots((*MII)->getOpCode()))
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{
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TM.getInstrInfo().getNumDelaySlots((*MII)->getOpCode())) {
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MachineInstr *MInst = *MII, *DelaySlotMI = *(MII+1);
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// Check the 2 conditions above:
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@ -562,8 +532,7 @@ void PhyRegAlloc::updateMachineCode()
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(AddedInstrMap[DelaySlotMI].InstrnsBefore.size() > 0 ||
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AddedInstrMap[DelaySlotMI].InstrnsAfter.size() > 0));
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if (cond1 || cond2)
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{
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if (cond1 || cond2) {
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assert((MInst->getOpCodeFlags() & AnnulFlag) == 0 &&
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"FIXME: Moving an annulled delay slot instruction!");
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assert(delaySlots==1 &&
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@ -646,15 +615,13 @@ void PhyRegAlloc::updateMachineCode()
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}
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//----------------------------------------------------------------------------
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// This method inserts spill code for AN operand whose LR was spilled.
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// This method may be called several times for a single machine instruction
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// if it contains many spilled operands. Each time it is called, it finds
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// a register which is not live at that instruction and also which is not
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// used by other spilled operands of the same instruction. Then it uses
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// this register temporarily to accommodate the spilled value.
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//----------------------------------------------------------------------------
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/// Insert spill code for AN operand whose LR was spilled. May be called
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/// repeatedly for a single MachineInstr if it has many spilled operands. On
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/// each call, it finds a register which is not live at that instruction and
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/// also which is not used by other spilled operands of the same
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/// instruction. Then it uses this register temporarily to accommodate the
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/// spilled value.
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///
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void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
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MachineBasicBlock::iterator& MII,
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MachineBasicBlock &MBB,
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@ -690,7 +657,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
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}
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#endif
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MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType) );
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MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
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std::vector<MachineInstr*> MIBef, MIAft;
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std::vector<MachineInstr*> AdIMid;
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@ -716,8 +683,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
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// for the copy and not used across MInst.
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int scratchRegType = -1;
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int scratchReg = -1;
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if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
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{
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if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType)) {
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scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
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MInst, MIBef, MIAft);
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assert(scratchReg != MRI.getInvalidRegNum());
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@ -761,23 +727,15 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
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}
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//----------------------------------------------------------------------------
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// This method inserts caller saving/restoring instructions before/after
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// a call machine instruction. The caller saving/restoring instructions are
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// inserted like:
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// ** caller saving instructions
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// other instructions inserted for the call by ColorCallArg
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// CALL instruction
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// other instructions inserted for the call ColorCallArg
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// ** caller restoring instructions
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//----------------------------------------------------------------------------
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/// Insert caller saving/restoring instructions before/after a call machine
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/// instruction (before or after any other instructions that were inserted for
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/// the call).
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///
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void
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PhyRegAlloc::insertCallerSavingCode(std::vector<MachineInstr*> &instrnsBefore,
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std::vector<MachineInstr*> &instrnsAfter,
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MachineInstr *CallMI,
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const BasicBlock *BB)
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{
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const BasicBlock *BB) {
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assert(TM.getInstrInfo().isCall(CallMI->getOpCode()));
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// hash set to record which registers were saved/restored
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@ -827,8 +785,8 @@ PhyRegAlloc::insertCallerSavingCode(std::vector<MachineInstr*> &instrnsBefore,
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// LR can be null if it is a const since a const
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// doesn't have a dominating def - see Assumptions above
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if( LR ) {
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if(! LR->isMarkedForSpill()) {
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if (LR) {
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if (! LR->isMarkedForSpill()) {
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assert(LR->hasColor() && "LR is neither spilled nor colored?");
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unsigned RCID = LR->getRegClassID();
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unsigned Color = LR->getColor();
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@ -933,15 +891,11 @@ PhyRegAlloc::insertCallerSavingCode(std::vector<MachineInstr*> &instrnsBefore,
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}
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||||
|
||||
//----------------------------------------------------------------------------
|
||||
// We can use the following method to get a temporary register to be used
|
||||
// BEFORE any given machine instruction. If there is a register available,
|
||||
// this method will simply return that register and set MIBef = MIAft = NULL.
|
||||
// Otherwise, it will return a register and MIAft and MIBef will contain
|
||||
// two instructions used to free up this returned register.
|
||||
// Returned register number is the UNIFIED register number
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
/// Returns the unified register number of a temporary register to be used
|
||||
/// BEFORE MInst. If no register is available, it will pick one and modify
|
||||
/// MIBef and MIAft to contain instructions used to free up this returned
|
||||
/// register.
|
||||
///
|
||||
int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
|
||||
const ValueSet *LVSetBef,
|
||||
MachineInstr *MInst,
|
||||
@ -949,7 +903,7 @@ int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
|
||||
std::vector<MachineInstr*>& MIAft) {
|
||||
RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
|
||||
|
||||
int RegU = getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
|
||||
int RegU = getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
|
||||
|
||||
if (RegU == -1) {
|
||||
// we couldn't find an unused register. Generate code to free up a reg by
|
||||
@ -961,8 +915,7 @@ int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
|
||||
|
||||
// Check if we need a scratch register to copy this register to memory.
|
||||
int scratchRegType = -1;
|
||||
if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
|
||||
{
|
||||
if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType)) {
|
||||
int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
|
||||
MInst, MIBef, MIAft);
|
||||
assert(scratchReg != MRI.getInvalidRegNum());
|
||||
@ -974,29 +927,23 @@ int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
|
||||
ScratchRegsUsed.insert(std::make_pair(MInst, scratchReg));
|
||||
MRI.cpReg2RegMI(MIBef, RegU, scratchReg, RegType);
|
||||
MRI.cpReg2RegMI(MIAft, scratchReg, RegU, RegType);
|
||||
}
|
||||
else
|
||||
{ // the register can be copied directly to/from memory so do it.
|
||||
} else { // the register can be copied directly to/from memory so do it.
|
||||
MRI.cpReg2MemMI(MIBef, RegU, MRI.getFramePointer(), TmpOff, RegType);
|
||||
MRI.cpMem2RegMI(MIAft, MRI.getFramePointer(), TmpOff, RegU, RegType);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return RegU;
|
||||
}
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// This method is called to get a new unused register that can be used
|
||||
// to accommodate a temporary value. This method may be called several times
|
||||
// for a single machine instruction. Each time it is called, it finds a
|
||||
// register which is not live at that instruction and also which is not used
|
||||
// by other spilled operands of the same instruction. Return register number
|
||||
// is relative to the register class, NOT the unified number.
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC,
|
||||
const int RegType,
|
||||
/// Returns the register-class register number of a new unused register that
|
||||
/// can be used to accommodate a temporary value. May be called repeatedly
|
||||
/// for a single MachineInstr. On each call, it finds a register which is not
|
||||
/// live at that instruction and which is not used by any spilled operands of
|
||||
/// that instruction.
|
||||
///
|
||||
int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC, const int RegType,
|
||||
const MachineInstr *MInst,
|
||||
const ValueSet* LVSetBef) {
|
||||
RC->clearColorsUsed(); // Reset array
|
||||
@ -1033,11 +980,9 @@ int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC,
|
||||
}
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Get any other register in a register class, other than what is used
|
||||
// by operands of a machine instruction. Returns the unified reg number.
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
/// Return the unified register number of a register in class RC which is not
|
||||
/// used by any operands of MInst.
|
||||
///
|
||||
int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
|
||||
const int RegType,
|
||||
const MachineInstr *MInst) {
|
||||
@ -1054,12 +999,10 @@ int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
|
||||
}
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// This method modifies the IsColorUsedArr of the register class passed to it.
|
||||
// It sets the bits corresponding to the registers used by this machine
|
||||
// instructions. Both explicit and implicit operands are set.
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
/// Modify the IsColorUsedArr of register class RC, by setting the bits
|
||||
/// corresponding to register RegNo. This is a helper method of
|
||||
/// setRelRegsUsedByThisInst().
|
||||
///
|
||||
static void markRegisterUsed(int RegNo, RegClass *RC, int RegType,
|
||||
const TargetRegInfo &TRI) {
|
||||
unsigned classId = 0;
|
||||
@ -1069,13 +1012,13 @@ static void markRegisterUsed(int RegNo, RegClass *RC, int RegType,
|
||||
}
|
||||
|
||||
void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC, int RegType,
|
||||
const MachineInstr *MI)
|
||||
{
|
||||
const MachineInstr *MI) {
|
||||
assert(OperandsColoredMap[MI] == true &&
|
||||
"Illegal to call setRelRegsUsedByThisInst() until colored operands "
|
||||
"are marked for an instruction.");
|
||||
|
||||
// Add the registers already marked as used by the instruction.
|
||||
// Add the registers already marked as used by the instruction. Both
|
||||
// explicit and implicit operands are set.
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
|
||||
if (MI->getOperand(i).hasAllocatedReg())
|
||||
markRegisterUsed(MI->getOperand(i).getAllocatedRegNum(), RC, RegType,MRI);
|
||||
@ -1103,13 +1046,11 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC, int RegType,
|
||||
}
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// If there are delay slots for an instruction, the instructions
|
||||
// added after it must really go after the delayed instruction(s).
|
||||
// So, we move the InstrAfter of that instruction to the
|
||||
// corresponding delayed instruction using the following method.
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
/// If there are delay slots for an instruction, the instructions added after
|
||||
/// it must really go after the delayed instruction(s). So, we Move the
|
||||
/// InstrAfter of that instruction to the corresponding delayed instruction
|
||||
/// using the following method.
|
||||
///
|
||||
void PhyRegAlloc::move2DelayedInstr(const MachineInstr *OrigMI,
|
||||
const MachineInstr *DelayedMI)
|
||||
{
|
||||
@ -1141,13 +1082,11 @@ void PhyRegAlloc::colorIncomingArgs()
|
||||
}
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// This method determines whether the suggested color of each live range
|
||||
// is really usable, and then calls its setSuggestedColorUsable() method to
|
||||
// record the answer. A suggested color is NOT usable when the suggested color
|
||||
// is volatile AND when there are call interferences.
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
/// Determine whether the suggested color of each live range is really usable,
|
||||
/// and then call its setSuggestedColorUsable() method to record the answer. A
|
||||
/// suggested color is NOT usable when the suggested color is volatile AND
|
||||
/// when there are call interferences.
|
||||
///
|
||||
void PhyRegAlloc::markUnusableSugColors()
|
||||
{
|
||||
LiveRangeMapType::const_iterator HMI = (LRI->getLiveRangeMap())->begin();
|
||||
@ -1165,13 +1104,10 @@ void PhyRegAlloc::markUnusableSugColors()
|
||||
}
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// The following method will set the stack offsets of the live ranges that
|
||||
// are decided to be spilled. This must be called just after coloring the
|
||||
// LRs using the graph coloring algo. For each live range that is spilled,
|
||||
// this method allocate a new spill position on the stack.
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
/// For each live range that is spilled, allocates a new spill position on the
|
||||
/// stack, and set the stack offsets of the live range that will be spilled to
|
||||
/// that position. This must be called just after coloring the LRs.
|
||||
///
|
||||
void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
|
||||
if (DEBUG_RA) std::cerr << "\nSetting LR stack offsets for spills...\n";
|
||||
|
||||
@ -1235,8 +1171,11 @@ namespace {
|
||||
};
|
||||
}
|
||||
|
||||
void PhyRegAlloc::saveState ()
|
||||
{
|
||||
/// Save the global register allocation decisions made by the register
|
||||
/// allocator so that they can be accessed later (sort of like "poor man's
|
||||
/// debug info").
|
||||
///
|
||||
void PhyRegAlloc::saveState () {
|
||||
std::vector<Constant *> state;
|
||||
unsigned Insn = 0;
|
||||
LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap ()->end ();
|
||||
@ -1284,6 +1223,12 @@ void PhyRegAlloc::saveState ()
|
||||
FnAllocState[Fn] = S;
|
||||
}
|
||||
|
||||
/// Check the saved state filled in by saveState(), and abort if it looks
|
||||
/// wrong. Only used when debugging.
|
||||
///
|
||||
void PhyRegAlloc::verifySavedState () {
|
||||
/// not yet implemented
|
||||
}
|
||||
|
||||
bool PhyRegAlloc::doFinalization (Module &M) {
|
||||
if (!SaveRegAllocState)
|
||||
@ -1332,10 +1277,9 @@ bool PhyRegAlloc::doFinalization (Module &M) {
|
||||
}
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// The entry point to Register Allocation
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
/// Allocate registers for the machine code previously generated for F using
|
||||
/// the graph-coloring algorithm.
|
||||
///
|
||||
bool PhyRegAlloc::runOnFunction (Function &F) {
|
||||
if (DEBUG_RA)
|
||||
std::cerr << "\n********* Function "<< F.getName () << " ***********\n";
|
||||
@ -1406,6 +1350,9 @@ bool PhyRegAlloc::runOnFunction (Function &F) {
|
||||
// Save register allocation state for this function in a Constant.
|
||||
if (SaveRegAllocState)
|
||||
saveState();
|
||||
if (DEBUG_RA) { // Check our work.
|
||||
verifySavedState ();
|
||||
}
|
||||
|
||||
// Now update the machine code with register names and add any
|
||||
// additional code inserted by the register allocator to the instruction
|
||||
|
||||
Loading…
Reference in New Issue
Block a user