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ldmxcsr and stmxcsr.
llvm-svn: 27506
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@ -1538,9 +1538,13 @@ def MASKMOVQ : I<0xF7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
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def SFENCE : I<0xAE, MRM7m, (ops),
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def SFENCE : I<0xAE, MRM7m, (ops),
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"sfence", []>, TB, Requires<[HasSSE1]>;
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"sfence", []>, TB, Requires<[HasSSE1]>;
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// Load MXCSR register
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// MXCSR register
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def LDMXCSR : I<0xAE, MRM2m, (ops i32mem:$src),
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def LDMXCSR : I<0xAE, MRM2m, (ops i32mem:$src),
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"ldmxcsr {$src|$src}", []>, TB, Requires<[HasSSE1]>;
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"ldmxcsr $src",
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[(int_x86_sse_ldmxcsr addr:$src)]>, TB, Requires<[HasSSE1]>;
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def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst),
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"stmxcsr $dst",
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[(int_x86_sse_stmxcsr addr:$dst)]>, TB, Requires<[HasSSE1]>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Alias Instructions
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// Alias Instructions
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