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[PowerPC] Correct P7 dispatch unit allocation for vector instructions
llvm-svn: 205222
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@ -339,36 +339,28 @@ def P7Itineraries : ProcessorItineraries<
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P7_DU3, P7_DU4], 0>,
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InstrStage<1, [P7_VS1, P7_VS2]>],
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[5, 1, 1]>,
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InstrItinData<IIC_VecGeneral , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrItinData<IIC_VecGeneral , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_VS1]>],
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[2, 1, 1]>,
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InstrItinData<IIC_VecVSL , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrItinData<IIC_VecVSL , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_VS1]>],
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[2, 1, 1]>,
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InstrItinData<IIC_VecVSR , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrItinData<IIC_VecVSR , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_VS1]>],
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[2, 1, 1]>,
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InstrItinData<IIC_VecFP , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrItinData<IIC_VecFP , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_VS1, P7_VS2]>],
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[6, 1, 1]>,
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InstrItinData<IIC_VecFPCompare, [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrItinData<IIC_VecFPCompare, [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_VS1, P7_VS2]>],
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[6, 1, 1]>,
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InstrItinData<IIC_VecFPRound , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrItinData<IIC_VecFPRound , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_VS1, P7_VS2]>],
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[6, 1, 1]>,
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InstrItinData<IIC_VecComplex , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrItinData<IIC_VecComplex , [InstrStage<1, [P7_DU1], 0>,
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InstrStage<1, [P7_VS1]>],
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[7, 1, 1]>,
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InstrItinData<IIC_VecPerm , [InstrStage<1, [P7_DU1, P7_DU2,
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P7_DU3, P7_DU4], 0>,
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InstrItinData<IIC_VecPerm , [InstrStage<1, [P7_DU1, P7_DU2], 0>,
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InstrStage<1, [P7_VS2]>],
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[3, 1, 1]>
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]>;
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