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[PowerPC] Mark zext of a small scalar load as free

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This initial implementation of PPCTargetLowering::isZExtFree marks as free
zexts of small scalar loads (that are not sign-extending). This callback is
used by SelectionDAGBuilder's RegsForValue::getCopyToRegs, and thus to
determine whether a zext or an anyext is used to lower illegally-typed PHIs.
Because later truncates of zero-extended values are nops, this allows for the
elimination of later unnecessary truncations.

Fixes the initial complaint associated with PR22120.

llvm-svn: 225584
This commit is contained in:
Hal Finkel 2015-01-10 08:21:59 +00:00
parent e74c9aa59c
commit 0a750c5cd8
3 changed files with 59 additions and 0 deletions
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20
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -9780,6 +9780,26 @@ bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
return NumBits1 == 64 && NumBits2 == 32;
}
bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
// Generally speaking, zexts are not free, but they are free when they can be
// folded with other operations.
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
EVT MemVT = LD->getMemoryVT();
if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
(Subtarget.isPPC64() && MemVT == MVT::i32)) &&
(LD->getExtensionType() == ISD::NON_EXTLOAD ||
LD->getExtensionType() == ISD::ZEXTLOAD))
return true;
}
// FIXME: Add other cases...
// - 32-bit shifts with a zext to i64
// - zext after ctlz, bswap, etc.
// - zext after and by a constant mask
return TargetLowering::isZExtFree(Val, VT2);
}
bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
return isInt<16>(Imm) || isUInt<16>(Imm);
}

2
lib/Target/PowerPC/PPCISelLowering.h
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@ -526,6 +526,8 @@ namespace llvm {
bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
bool isTruncateFree(EVT VT1, EVT VT2) const override;
bool isZExtFree(SDValue Val, EVT VT2) const override;
/// \brief Returns true if it is beneficial to convert a load of a constant
/// to just the constant itself.
bool shouldConvertConstantLoadToIntImm(const APInt &Imm,

37
test/CodeGen/PowerPC/zext-free.ll Normal file
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@ -0,0 +1,37 @@
; RUN: llc -mcpu=ppc64 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: noreturn nounwind
define signext i32 @_Z1fRPc(i8** nocapture dereferenceable(8) %p) #0 {
entry:
%.pre = load i8** %p, align 8
br label %loop
loop: ; preds = %loop.backedge, %entry
%0 = phi i8* [ %.pre, %entry ], [ %.be, %loop.backedge ]
%1 = load i8* %0, align 1
%tobool = icmp eq i8 %1, 0
%incdec.ptr = getelementptr inbounds i8* %0, i64 1
store i8* %incdec.ptr, i8** %p, align 8
%2 = load i8* %incdec.ptr, align 1
%tobool2 = icmp ne i8 %2, 0
%or.cond = and i1 %tobool, %tobool2
br i1 %or.cond, label %if.then3, label %loop.backedge
if.then3: ; preds = %loop
%incdec.ptr4 = getelementptr inbounds i8* %0, i64 2
store i8* %incdec.ptr4, i8** %p, align 8
br label %loop.backedge
loop.backedge: ; preds = %if.then3, %loop
%.be = phi i8* [ %incdec.ptr4, %if.then3 ], [ %incdec.ptr, %loop ]
br label %loop
; CHECK-LABEL: @_Z1fRPc
; CHECK-NOT: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31
; CHECK-NOT: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
}
attributes #0 = { noreturn nounwind }