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https://github.com/RPCS3/llvm-mirror.git
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Significant changes to correctly spill CC registers and to correctly
handle conditional move instructions: -- cpMem<->Reg functions now support CC registers (int and FP) correctly. -- Scratch registers must be explicitly provided to cpMem<->Reg when needed, since CC regs need one to be copied to/from memory. -- CC regs are saved to a scratch register instead of stack. -- All regs used by a instruction are now recorded in MachineInstr::regsUsed, since regs used to save values *across* an instruction are not obvious either from the operands or from the LiveVar sets. -- An (explicit or implicit) operand may now be both a def and a use. This is needed for conditional move operations. So an operand may need spill code both before and after the instruction. -- class MachineCodeForBasicBlock is now an annotation on BasicBlock. llvm-svn: 2833
This commit is contained in:
Vikram S. Adve
parent
a8c7633d5b
commit
0b32273208
@ -13,6 +13,7 @@
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#include "llvm/CodeGen/PhyRegAlloc.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrAnnot.h"
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#include "llvm/CodeGen/MachineCodeForBasicBlock.h"
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#include "llvm/CodeGen/MachineCodeForMethod.h"
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#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"
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#include "llvm/Analysis/LoopInfo.h"
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@ -24,6 +25,7 @@
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#include "llvm/iOther.h"
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#include "llvm/CodeGen/RegAllocCommon.h"
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#include "Support/CommandLine.h"
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#include "Support/STLExtras.h"
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#include <iostream>
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#include <math.h>
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using std::cerr;
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@ -172,7 +174,7 @@ void PhyRegAlloc::addInterference(const Value *Def,
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//
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for ( ; LIt != LVSet->end(); ++LIt) {
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if (DEBUG_RA > 1)
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if (DEBUG_RA >= RA_DEBUG_Verbose)
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cerr << "< Def=" << RAV(Def) << ", Lvar=" << RAV(*LIt) << "> ";
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// get the live range corresponding to live var
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@ -190,7 +192,7 @@ void PhyRegAlloc::addInterference(const Value *Def,
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//
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if (RCOfDef == LROfVar->getRegClass()) {
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RCOfDef->setInterference( LROfDef, LROfVar);
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} else if (DEBUG_RA > 1) {
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} else if (DEBUG_RA >= RA_DEBUG_Verbose) {
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// we will not have LRs for values not explicitly allocated in the
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// instruction stream (e.g., constants)
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cerr << " warning: no live range for " << RAV(*LIt) << "\n";
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@ -289,7 +291,7 @@ void PhyRegAlloc::buildInterferenceGraphs()
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// get the iterator for machine instructions
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//
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const MachineCodeForBasicBlock& MIVec = BBI->getMachineInstrVec();
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const MachineCodeForBasicBlock& MIVec = MachineCodeForBasicBlock::get(BBI);
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MachineCodeForBasicBlock::const_iterator MII = MIVec.begin();
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// iterate over all the machine instructions in BB
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@ -414,7 +416,7 @@ void PhyRegAlloc::addInterferencesForArgs() {
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// add interferences between args and LVars at start
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addInterference(AI, &InSet, false);
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if (DEBUG_RA > 1)
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if (DEBUG_RA >= RA_DEBUG_Verbose)
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cerr << " - %% adding interference for argument " << RAV(AI) << "\n";
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}
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}
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@ -479,7 +481,7 @@ AppendInstructions(std::vector<MachineInstr *> &IAft,
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void PhyRegAlloc::updateMachineCode()
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{
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MachineCodeForBasicBlock& MIVec = Meth->getEntryNode().getMachineInstrVec();
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MachineCodeForBasicBlock& MIVec = MachineCodeForBasicBlock::get(&Meth->getEntryNode());
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// Insert any instructions needed at method entry
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MachineCodeForBasicBlock::iterator MII = MIVec.begin();
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@ -493,7 +495,7 @@ void PhyRegAlloc::updateMachineCode()
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BBI != BBE; ++BBI) {
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// iterate over all the machine instructions in BB
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MachineCodeForBasicBlock &MIVec = BBI->getMachineInstrVec();
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MachineCodeForBasicBlock &MIVec = MachineCodeForBasicBlock::get(BBI);
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for (MachineCodeForBasicBlock::iterator MII = MIVec.begin();
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MII != MIVec.end(); ++MII) {
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@ -505,6 +507,9 @@ void PhyRegAlloc::updateMachineCode()
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if (TM.getInstrInfo().isDummyPhiInstr(Opcode))
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continue;
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// Reset tmp stack positions so they can be reused for each machine instr.
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mcInfo.popAllTempValues(TM);
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// Now insert speical instructions (if necessary) for call/return
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// instructions.
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//
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@ -513,94 +518,44 @@ void PhyRegAlloc::updateMachineCode()
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AddedInstrns &AI = AddedInstrMap[MInst];
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// Tmp stack poistions are needed by some calls that have spilled args
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// So reset it before we call each such method
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//
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mcInfo.popAllTempValues(TM);
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if (TM.getInstrInfo().isCall(Opcode))
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MRI.colorCallArgs(MInst, LRI, &AI, *this, BBI);
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else if (TM.getInstrInfo().isReturn(Opcode))
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MRI.colorRetValue(MInst, LRI, &AI);
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}
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/* -- Using above code instead of this
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// if this machine instr is call, insert caller saving code
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if ((TM.getInstrInfo()).isCall( MInst->getOpCode()) )
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MRI.insertCallerSavingCode(MInst, *BBI, *this );
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*/
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// reset the stack offset for temporary variables since we may
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// need that to spill
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// mcInfo.popAllTempValues(TM);
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// TODO ** : do later
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//for (MachineInstr::val_const_op_iterator OpI(MInst);!OpI.done();++OpI) {
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// Now replace set the registers for operands in the machine instruction
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//
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for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
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MachineOperand& Op = MInst->getOperand(OpNum);
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if (Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
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Op.getOperandType() == MachineOperand::MO_CCRegister) {
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const Value *const Val = Op.getVRegValue();
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// delete this condition checking later (must assert if Val is null)
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if (!Val) {
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if (DEBUG_RA)
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cerr << "Warning: NULL Value found for operand\n";
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continue;
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}
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assert( Val && "Value is NULL");
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LiveRange *const LR = LRI.getLiveRangeForValue(Val);
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if (!LR ) {
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// nothing to worry if it's a const or a label
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if (DEBUG_RA) {
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cerr << "*NO LR for operand : " << Op ;
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cerr << " [reg:" << Op.getAllocatedRegNum() << "]";
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cerr << " in inst:\t" << *MInst << "\n";
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// Set the registers for operands in the machine instruction
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// if a register was successfully allocated. If not, insert
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// code to spill the register value.
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//
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for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
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{
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MachineOperand& Op = MInst->getOperand(OpNum);
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if (Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
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Op.getOperandType() == MachineOperand::MO_CCRegister)
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{
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const Value *const Val = Op.getVRegValue();
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LiveRange *const LR = LRI.getLiveRangeForValue(Val);
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if (!LR) // consts or labels will have no live range
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{
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// if register is not allocated, mark register as invalid
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if (Op.getAllocatedRegNum() == -1)
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MInst->SetRegForOperand(OpNum, MRI.getInvalidRegNum());
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continue;
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}
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if (LR->hasColor() )
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MInst->SetRegForOperand(OpNum,
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MRI.getUnifiedRegNum(LR->getRegClass()->getID(),
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LR->getColor()));
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else
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// LR did NOT receive a color (register). Insert spill code.
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insertCode4SpilledLR(LR, MInst, BBI, OpNum );
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}
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// if register is not allocated, mark register as invalid
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if (Op.getAllocatedRegNum() == -1)
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Op.setRegForValue( MRI.getInvalidRegNum());
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continue;
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}
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unsigned RCID = (LR->getRegClass())->getID();
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if (LR->hasColor() ) {
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Op.setRegForValue( MRI.getUnifiedRegNum(RCID, LR->getColor()) );
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}
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else {
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// LR did NOT receive a color (register). Now, insert spill code
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// for spilled opeands in this machine instruction
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//assert(0 && "LR must be spilled");
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insertCode4SpilledLR(LR, MInst, BBI, OpNum );
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}
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}
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} // for each operand
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} // for each operand
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// Now add instructions that the register allocator inserts before/after
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// this machine instructions (done only for calls/rets/incoming args)
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// We do this here, to ensure that spill for an instruction is inserted
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@ -626,16 +581,12 @@ void PhyRegAlloc::updateMachineCode()
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unsigned delay;
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if ((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){
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move2DelayedInstr(MInst, *(MII+delay) );
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if (DEBUG_RA) cerr<< "\nMoved an added instr after the delay slot";
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}
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else {
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// Here we can add the "instructions after" to the current
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// instruction since there are no delay slots for this instruction
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AppendInstructions(AddedInstrMap[MInst].InstrnsAfter, MIVec, MII,"");
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} // if not delay
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}
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} // for each machine instruction
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@ -663,6 +614,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
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MachineOperand& Op = MInst->getOperand(OpNum);
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bool isDef = MInst->operandIsDefined(OpNum);
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bool isDefAndUse = MInst->operandIsDefinedAndUsed(OpNum);
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unsigned RegType = MRI.getRegType( LR );
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int SpillOff = LR->getSpillOffFromFP();
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RegClass *RC = LR->getRegClass();
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@ -670,63 +622,72 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
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mcInfo.pushTempValue(TM, MRI.getSpilledRegSize(RegType) );
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MachineInstr *MIBef=NULL, *MIAft=NULL;
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vector<MachineInstr*> MIBef, MIAft;
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vector<MachineInstr*> AdIMid;
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int TmpRegU = getUsableUniRegAtMI(RC, RegType, MInst,&LVSetBef, MIBef, MIAft);
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// Choose a register to hold the spilled value. This may insert code
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// before and after MInst to free up the value. If so, this code should
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// be first and last in the spill sequence before/after MInst.
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int TmpRegU = getUsableUniRegAtMI(RegType, &LVSetBef, MInst, MIBef, MIAft);
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// get the added instructions for this instruciton
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// Set the operand first so that it this register does not get used
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// as a scratch register for later calls to getUsableUniRegAtMI below
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MInst->SetRegForOperand(OpNum, TmpRegU);
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// get the added instructions for this instruction
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AddedInstrns &AI = AddedInstrMap[MInst];
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if (!isDef) {
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// We may need a scratch register to copy the spilled value to/from memory.
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// This may itself have to insert code to free up a scratch register.
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// Any such code should go before (after) the spill code for a load (store).
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int scratchRegType = -1;
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int scratchReg = -1;
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if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
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{
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scratchReg = this->getUsableUniRegAtMI(scratchRegType, &LVSetBef,
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MInst, MIBef, MIAft);
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assert(scratchReg != MRI.getInvalidRegNum());
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MInst->getRegsUsed().insert(scratchReg);
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}
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if (!isDef || isDefAndUse) {
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// for a USE, we have to load the value of LR from stack to a TmpReg
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// and use the TmpReg as one operand of instruction
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// actual loading instruction
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MRI.cpMem2RegMI(MRI.getFramePointer(), SpillOff, TmpRegU,RegType, AdIMid);
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AI.InstrnsBefore.insert(AI.InstrnsBefore.end(),
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AdIMid.begin(), AdIMid.end());
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if (MIBef)
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AI.InstrnsBefore.push_back(MIBef);
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if (MIAft)
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AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(), MIAft);
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// actual loading instruction(s)
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MRI.cpMem2RegMI(AdIMid, MRI.getFramePointer(), SpillOff, TmpRegU, RegType,
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scratchReg);
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} else { // if this is a Def
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// the actual load should be after the instructions to free up TmpRegU
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MIBef.insert(MIBef.end(), AdIMid.begin(), AdIMid.end());
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AdIMid.clear();
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}
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if (isDef) { // if this is a Def
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// for a DEF, we have to store the value produced by this instruction
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// on the stack position allocated for this LR
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// actual storing instruction
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MRI.cpReg2MemMI(TmpRegU, MRI.getFramePointer(), SpillOff,RegType, AdIMid);
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if (MIBef)
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AI.InstrnsBefore.push_back(MIBef);
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// actual storing instruction(s)
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MRI.cpReg2MemMI(AdIMid, TmpRegU, MRI.getFramePointer(), SpillOff, RegType,
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scratchReg);
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AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(),
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AdIMid.begin(), AdIMid.end());
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if (MIAft)
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AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(), MIAft);
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MIAft.insert(MIAft.begin(), AdIMid.begin(), AdIMid.end());
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} // if !DEF
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// Finally, insert the entire spill code sequences before/after MInst
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AI.InstrnsBefore.insert(AI.InstrnsBefore.end(), MIBef.begin(), MIBef.end());
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AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(), MIAft.begin(), MIAft.end());
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if (DEBUG_RA) {
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cerr << "\nFor Inst " << *MInst;
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cerr << " - SPILLED LR: "; printSet(*LR);
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cerr << "\n - Added Instructions:";
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if (MIBef) cerr << *MIBef;
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for (vector<MachineInstr*>::const_iterator II=AdIMid.begin();
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II != AdIMid.end(); ++II)
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cerr << **II;
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if (MIAft) cerr << *MIAft;
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for_each(MIBef.begin(), MIBef.end(), mem_fun(&MachineInstr::dump));
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for_each(MIAft.begin(), MIAft.end(), mem_fun(&MachineInstr::dump));
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}
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Op.setRegForValue(TmpRegU); // set the opearnd
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}
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//----------------------------------------------------------------------------
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// We can use the following method to get a temporary register to be used
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// BEFORE any given machine instruction. If there is a register available,
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@ -736,39 +697,47 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
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// Returned register number is the UNIFIED register number
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//----------------------------------------------------------------------------
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int PhyRegAlloc::getUsableUniRegAtMI(RegClass *RC,
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const int RegType,
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const MachineInstr *MInst,
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const ValueSet *LVSetBef,
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MachineInstr *&MIBef,
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MachineInstr *&MIAft) {
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int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
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const ValueSet *LVSetBef,
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MachineInstr *MInst,
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std::vector<MachineInstr*>& MIBef,
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std::vector<MachineInstr*>& MIAft) {
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RegClass* RC = this->getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
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int RegU = getUnusedUniRegAtMI(RC, MInst, LVSetBef);
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if (RegU != -1) {
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// we found an unused register, so we can simply use it
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MIBef = MIAft = NULL;
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}
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else {
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if (RegU == -1) {
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// we couldn't find an unused register. Generate code to free up a reg by
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// saving it on stack and restoring after the instruction
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int TmpOff = mcInfo.pushTempValue(TM, MRI.getSpilledRegSize(RegType) );
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RegU = getUniRegNotUsedByThisInst(RC, MInst);
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vector<MachineInstr*> mvec;
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MRI.cpReg2MemMI(RegU, MRI.getFramePointer(), TmpOff, RegType, mvec);
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assert(mvec.size() == 1 && "Need to return a vector here too");
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MIBef = * mvec.begin();
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MRI.cpMem2RegMI(MRI.getFramePointer(), TmpOff, RegU, RegType, mvec);
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assert(mvec.size() == 1 && "Need to return a vector here too");
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MIAft = * mvec.begin();
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// Check if we need a scratch register to copy this register to memory.
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int scratchRegType = -1;
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if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
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{
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int scratchReg = this->getUsableUniRegAtMI(scratchRegType, LVSetBef,
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MInst, MIBef, MIAft);
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assert(scratchReg != MRI.getInvalidRegNum());
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// We may as well hold the value in the scratch register instead
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// of copying it to memory and back. But we have to mark the
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// register as used by this instruction, so it does not get used
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// as a scratch reg. by another operand or anyone else.
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MInst->getRegsUsed().insert(scratchReg);
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MRI.cpReg2RegMI(MIBef, RegU, scratchReg, RegType);
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MRI.cpReg2RegMI(MIAft, scratchReg, RegU, RegType);
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}
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else
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{ // the register can be copied directly to/from memory so do it.
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MRI.cpReg2MemMI(MIBef, RegU, MRI.getFramePointer(), TmpOff, RegType);
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MRI.cpMem2RegMI(MIAft, MRI.getFramePointer(), TmpOff, RegU, RegType);
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}
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}
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return RegU;
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}
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@ -816,7 +785,7 @@ int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC,
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for (unsigned c=0; c < NumAvailRegs; c++) // find first unused color
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if (!IsColorUsedArr[c])
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return MRI.getUnifiedRegNum(RC->getID(), c);
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return -1;
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}
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@ -831,7 +800,6 @@ int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
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vector<bool> &IsColorUsedArr = RC->getIsColorUsedArr();
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unsigned NumAvailRegs = RC->getNumOfAvailRegs();
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for (unsigned i=0; i < NumAvailRegs ; i++) // Reset array
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IsColorUsedArr[i] = false;
|
||||
|
||||
@ -852,62 +820,55 @@ int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
|
||||
// instructions. Both explicit and implicit operands are set.
|
||||
//----------------------------------------------------------------------------
|
||||
void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC,
|
||||
const MachineInstr *MInst ) {
|
||||
const MachineInstr *MInst ) {
|
||||
|
||||
vector<bool> &IsColorUsedArr = RC->getIsColorUsedArr();
|
||||
vector<bool> &IsColorUsedArr = RC->getIsColorUsedArr();
|
||||
|
||||
for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
|
||||
|
||||
const MachineOperand& Op = MInst->getOperand(OpNum);
|
||||
|
||||
if (Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
||||
Op.getOperandType() == MachineOperand::MO_CCRegister ) {
|
||||
|
||||
const Value *const Val = Op.getVRegValue();
|
||||
|
||||
if (Val )
|
||||
if (MRI.getRegClassIDOfValue(Val) == RC->getID() ) {
|
||||
int Reg;
|
||||
if ((Reg=Op.getAllocatedRegNum()) != -1) {
|
||||
IsColorUsedArr[Reg] = true;
|
||||
}
|
||||
else {
|
||||
// it is possilbe that this operand still is not marked with
|
||||
// a register but it has a LR and that received a color
|
||||
|
||||
LiveRange *LROfVal = LRI.getLiveRangeForValue(Val);
|
||||
if (LROfVal)
|
||||
if (LROfVal->hasColor() )
|
||||
IsColorUsedArr[LROfVal->getColor()] = true;
|
||||
}
|
||||
|
||||
} // if reg classes are the same
|
||||
// Add the registers already marked as used by the instruction.
|
||||
// This should include any scratch registers that are used to save
|
||||
// values across the instruction (e.g., for saving state register values).
|
||||
const hash_set<int>& regsUsed = MInst->getRegsUsed();
|
||||
for (hash_set<int>::const_iterator SI=regsUsed.begin(), SE=regsUsed.end();
|
||||
SI != SE; ++SI)
|
||||
{
|
||||
unsigned classId = 0;
|
||||
int classRegNum = MRI.getClassRegNum(*SI, classId);
|
||||
if (RC->getID() == classId)
|
||||
{
|
||||
assert(classRegNum < (int) IsColorUsedArr.size() &&
|
||||
"Illegal register number for this reg class?");
|
||||
IsColorUsedArr[classRegNum] = true;
|
||||
}
|
||||
}
|
||||
else if (Op.getOperandType() == MachineOperand::MO_MachineRegister) {
|
||||
assert((unsigned)Op.getMachineRegNum() < IsColorUsedArr.size());
|
||||
IsColorUsedArr[Op.getMachineRegNum()] = true;
|
||||
|
||||
// Now add registers allocated to the live ranges of values used in
|
||||
// the instruction. These are not yet recorded in the instruction.
|
||||
for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
|
||||
{
|
||||
const MachineOperand& Op = MInst->getOperand(OpNum);
|
||||
|
||||
if (Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
|
||||
Op.getOperandType() == MachineOperand::MO_CCRegister)
|
||||
if (const Value* Val = Op.getVRegValue())
|
||||
if (MRI.getRegClassIDOfValue(Val) == RC->getID())
|
||||
if (Op.getAllocatedRegNum() == -1)
|
||||
if (LiveRange *LROfVal = LRI.getLiveRangeForValue(Val))
|
||||
if (LROfVal->hasColor() )
|
||||
// this operand is in a LR that received a color
|
||||
IsColorUsedArr[LROfVal->getColor()] = true;
|
||||
}
|
||||
}
|
||||
|
||||
// If there are implicit references, mark them as well
|
||||
|
||||
for (unsigned z=0; z < MInst->getNumImplicitRefs(); z++) {
|
||||
|
||||
LiveRange *const LRofImpRef =
|
||||
LRI.getLiveRangeForValue( MInst->getImplicitRef(z) );
|
||||
|
||||
if (LRofImpRef && LRofImpRef->hasColor())
|
||||
IsColorUsedArr[LRofImpRef->getColor()] = true;
|
||||
}
|
||||
|
||||
// If there are implicit references, mark their allocated regs as well
|
||||
//
|
||||
for (unsigned z=0; z < MInst->getNumImplicitRefs(); z++)
|
||||
if (const LiveRange*
|
||||
LRofImpRef = LRI.getLiveRangeForValue(MInst->getImplicitRef(z)))
|
||||
if (LRofImpRef->hasColor())
|
||||
// this implicit reference is in a LR that received a color
|
||||
IsColorUsedArr[LRofImpRef->getColor()] = true;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// If there are delay slots for an instruction, the instructions
|
||||
// added after it must really go after the delayed instruction(s).
|
||||
@ -951,7 +912,7 @@ void PhyRegAlloc::printMachineCode()
|
||||
cerr << "\n"; printLabel(BBI); cerr << ": ";
|
||||
|
||||
// get the iterator for machine instructions
|
||||
MachineCodeForBasicBlock& MIVec = BBI->getMachineInstrVec();
|
||||
MachineCodeForBasicBlock& MIVec = MachineCodeForBasicBlock::get(BBI);
|
||||
MachineCodeForBasicBlock::iterator MII = MIVec.begin();
|
||||
|
||||
// iterate over all the machine instructions in BB
|
||||
@ -1026,49 +987,13 @@ void PhyRegAlloc::printMachineCode()
|
||||
}
|
||||
|
||||
|
||||
#if 0
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
void PhyRegAlloc::colorCallRetArgs()
|
||||
{
|
||||
|
||||
CallRetInstrListType &CallRetInstList = LRI.getCallRetInstrList();
|
||||
CallRetInstrListType::const_iterator It = CallRetInstList.begin();
|
||||
|
||||
for ( ; It != CallRetInstList.end(); ++It ) {
|
||||
|
||||
const MachineInstr *const CRMI = *It;
|
||||
unsigned OpCode = CRMI->getOpCode();
|
||||
|
||||
// get the added instructions for this Call/Ret instruciton
|
||||
AddedInstrns &AI = AddedInstrMap[CRMI];
|
||||
|
||||
// Tmp stack positions are needed by some calls that have spilled args
|
||||
// So reset it before we call each such method
|
||||
//mcInfo.popAllTempValues(TM);
|
||||
|
||||
|
||||
if (TM.getInstrInfo().isCall(OpCode))
|
||||
MRI.colorCallArgs(CRMI, LRI, &AI, *this);
|
||||
else if (TM.getInstrInfo().isReturn(OpCode))
|
||||
MRI.colorRetValue(CRMI, LRI, &AI);
|
||||
else
|
||||
assert(0 && "Non Call/Ret instrn in CallRetInstrList\n");
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
void PhyRegAlloc::colorIncomingArgs()
|
||||
{
|
||||
const BasicBlock &FirstBB = Meth->front();
|
||||
const MachineInstr *FirstMI = FirstBB.getMachineInstrVec().front();
|
||||
const MachineInstr *FirstMI = MachineCodeForBasicBlock::get(&FirstBB).front();
|
||||
assert(FirstMI && "No machine instruction in entry BB");
|
||||
|
||||
MRI.colorMethodArgs(Meth, LRI, &AddedInstrAtEntry);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user