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Add PowerPC e500(v2) core scheduler and directives.
Differential Revision: https://reviews.llvm.org/D44828 llvm-svn: 337345
This commit is contained in:
Justin Hibbits
parent
49e6d8258d
commit
0b463af2f1
@ -35,6 +35,8 @@ def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
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def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
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def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
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def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
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def DirectiveE500 : SubtargetFeature<"", "DarwinDirective",
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"PPC::DIR_E500", "">;
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def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
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"PPC::DIR_E500mc", "">;
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def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
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@ -358,6 +360,10 @@ def : ProcessorModel<"g5", G5Model,
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FeatureFRES, FeatureFRSQRTE,
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Feature64Bit /*, Feature64BitRegs */,
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FeatureMFTB, DeprecatedDST]>;
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def : ProcessorModel<"e500", PPCE500Model,
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[DirectiveE500,
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FeatureICBT, FeatureBookE,
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FeatureISEL, FeatureMFTB]>;
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def : ProcessorModel<"e500mc", PPCE500mcModel,
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[DirectiveE500mc,
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FeatureSTFIWX, FeatureICBT, FeatureBookE,
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@ -1486,6 +1486,7 @@ void PPCDarwinAsmPrinter::EmitStartOfAsmFile(Module &M) {
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"ppc750",
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"ppc970",
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"ppcA2",
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"ppce500",
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"ppce500mc",
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"ppce5500",
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"power3",
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@ -1104,6 +1104,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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default: break;
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case PPC::DIR_970:
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case PPC::DIR_A2:
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case PPC::DIR_E500:
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case PPC::DIR_E500mc:
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case PPC::DIR_E5500:
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case PPC::DIR_PWR4:
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@ -10822,6 +10823,7 @@ unsigned PPCTargetLowering::combineRepeatedFPDivisors() const {
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return 3;
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case PPC::DIR_440:
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case PPC::DIR_A2:
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case PPC::DIR_E500:
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case PPC::DIR_E500mc:
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case PPC::DIR_E5500:
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return 2;
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@ -133,5 +133,6 @@ include "PPCScheduleP7.td"
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include "PPCScheduleP8.td"
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include "PPCScheduleP9.td"
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include "PPCScheduleA2.td"
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include "PPCScheduleE500.td"
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include "PPCScheduleE500mc.td"
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include "PPCScheduleE5500.td"
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266
lib/Target/PowerPC/PPCScheduleE500.td
Normal file
266
lib/Target/PowerPC/PPCScheduleE500.td
Normal file
@ -0,0 +1,266 @@
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//===-- PPCScheduleE500.td - e500 Scheduling Defs ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the Freescale e500 32-bit
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// Power processor.
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//
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// All information is derived from the "e500 Core Reference Manual",
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// Freescale Document Number E500MCRM, Rev. 1, 03/2012.
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//
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//===----------------------------------------------------------------------===//
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// Relevant functional units in the Freescale e500 core:
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//
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// * Decode & Dispatch
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// Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
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// queues (GIQx) or Branch issue queue (BIQ).
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def E500_DIS0 : FuncUnit; // Dispatch stage - insn 1
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def E500_DIS1 : FuncUnit; // Dispatch stage - insn 2
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// * Execute
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// 6 pipelined execution units: SU0, SU1, BU, LSU, MU.
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// Some instructions can only execute in SU0 but not SU1.
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def E500_SU0 : FuncUnit; // Simple unit 0
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def E500_SU1 : FuncUnit; // Simple unit 1
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def E500_BU : FuncUnit; // Branch unit
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def E500_MU : FuncUnit; // MU pipeline
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def E500_LSU_0 : FuncUnit; // LSU pipeline
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def E500_GPR_Bypass : Bypass;
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def E500_CR_Bypass : Bypass;
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def E500_DivBypass : Bypass;
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def PPCE500Itineraries : ProcessorItineraries<
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[E500_DIS0, E500_DIS1, E500_SU0, E500_SU1, E500_BU,
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E500_MU, E500_LSU_0],
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[E500_CR_Bypass, E500_GPR_Bypass, E500_DivBypass], [
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InstrItinData<IIC_IntSimple, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1]>],
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[4, 1, 1], // Latency = 1
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[E500_GPR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1]>],
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[4, 1, 1], // Latency = 1
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[E500_GPR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_IntISEL, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1]>],
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[4, 1, 1, 1], // Latency = 1
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[E500_GPR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass,
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E500_CR_Bypass]>,
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InstrItinData<IIC_IntCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1]>],
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[5, 1, 1], // Latency = 1 or 2
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[E500_CR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_IntDivW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_MU], 0>,
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InstrStage<14, [E500_MU]>],
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[17, 1, 1], // Latency=4..35, Repeat= 4..35
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[E500_GPR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<4, [E500_MU]>],
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[7, 1, 1], // Latency = 4, Repeat rate = 1
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[E500_GPR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<4, [E500_MU]>],
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[7, 1, 1], // Latency = 4, Repeat rate = 1
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[E500_GPR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<4, [E500_MU]>],
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[7, 1, 1], // Latency = 4, Repeat rate = 1
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[E500_GPR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_IntRotate, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1]>],
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[4, 1, 1], // Latency = 1
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[E500_GPR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_IntShift, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1]>],
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[4, 1, 1], // Latency = 1
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[E500_GPR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<2, [E500_SU0]>],
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[5, 1], // Latency = 2, Repeat rate = 2
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_BrB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_BU]>],
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[4, 1], // Latency = 1
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[NoBypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_BrCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_BU]>],
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[4, 1, 1], // Latency = 1
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[E500_CR_Bypass,
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E500_CR_Bypass, E500_CR_Bypass]>,
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InstrItinData<IIC_BrMCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_BU]>],
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[4, 1], // Latency = 1
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[E500_CR_Bypass, E500_CR_Bypass]>,
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InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1]>],
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[4, 1, 1], // Latency = 1
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[E500_CR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3, Repeat rate = 1
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStLoad, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[E500_GPR_Bypass, E500_GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[E500_GPR_Bypass, E500_GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<IIC_LdStStore, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[NoBypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[NoBypass, E500_GPR_Bypass],
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2>, // 2 micro-ops
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InstrItinData<IIC_LdStICBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[NoBypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[7, 1], // Latency = r+3
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[NoBypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<3, [E500_LSU_0]>],
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[6, 1, 1], // Latency = 3, Repeat rate = 3
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[E500_GPR_Bypass,
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E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0]>],
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[6, 1], // Latency = 3
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[NoBypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_LdStSync, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0]>]>,
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InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<4, [E500_SU0]>],
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[7, 1],
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<2, [E500_SU0, E500_SU1]>],
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[5, 1], // Latency = 2, Repeat rate = 4
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0]>],
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[5, 1],
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[NoBypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_LSU_0], 0>]>,
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InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<5, [E500_SU0]>],
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[8, 1],
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[E500_GPR_Bypass, E500_CR_Bypass]>,
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InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<5, [E500_SU0]>],
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[8, 1],
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[E500_GPR_Bypass, E500_CR_Bypass]>,
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InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<4, [E500_SU0]>],
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[7, 1], // Latency = 4, Repeat rate = 4
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<4, [E500_SU0]>],
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[7, 1], // Latency = 4, Repeat rate = 4
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[E500_GPR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1]>],
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[4, 1], // Latency = 1, Repeat rate = 1
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[E500_GPR_Bypass, E500_CR_Bypass]>,
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InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0]>],
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[4, 1], // Latency = 1, Repeat rate = 1
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[E500_CR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<4, [E500_SU0]>],
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[7, 1], // Latency = 4, Repeat rate = 4
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[NoBypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0, E500_SU1]>],
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[4, 1], // Latency = 1, Repeat rate = 1
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[E500_CR_Bypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0]>],
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[4, 1],
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[NoBypass, E500_GPR_Bypass]>,
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InstrItinData<IIC_FPDivD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<32, [E500_MU]>],
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[35, 1, 1], // Latency = 32, Repeat rate = 32
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[E500_DivBypass]>,
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InstrItinData<IIC_FPDivS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<29, [E500_MU]>],
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[32, 1, 1], // Latency = 29, Repeat rate = 29
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[E500_DivBypass]>,
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InstrItinData<IIC_VecGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<1, [E500_SU0]>],
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[4, 1, 1], // Latency = 1, Repeat rate = 1
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[NoBypass]>,
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InstrItinData<IIC_VecComplex, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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InstrStage<4, [E500_MU]>],
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[7, 1, 1], // Latency = 4, Repeat rate = 1
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[NoBypass]>
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]>;
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// ===---------------------------------------------------------------------===//
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// e500 machine model for scheduling and other instruction cost heuristics.
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||||
|
||||
def PPCE500Model : SchedMachineModel {
|
||||
let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
|
||||
let LoadLatency = 5; // Optimistic load latency assuming bypass.
|
||||
// This is overriden by OperandCycles if the
|
||||
// Itineraries are queried instead.
|
||||
|
||||
let CompleteModel = 0;
|
||||
|
||||
let Itineraries = PPCE500Itineraries;
|
||||
}
|
||||
@ -19,299 +19,299 @@
|
||||
// * Decode & Dispatch
|
||||
// Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
|
||||
// queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).
|
||||
def E500_DIS0 : FuncUnit; // Dispatch stage - insn 1
|
||||
def E500_DIS1 : FuncUnit; // Dispatch stage - insn 2
|
||||
def E500mc_DIS0 : FuncUnit; // Dispatch stage - insn 1
|
||||
def E500mc_DIS1 : FuncUnit; // Dispatch stage - insn 2
|
||||
|
||||
// * Execute
|
||||
// 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
|
||||
// Some instructions can only execute in SFX0 but not SFX1.
|
||||
// The CFX has a bypass path, allowing non-divide instructions to execute
|
||||
// while a divide instruction is executed.
|
||||
def E500_SFX0 : FuncUnit; // Simple unit 0
|
||||
def E500_SFX1 : FuncUnit; // Simple unit 1
|
||||
def E500_BU : FuncUnit; // Branch unit
|
||||
def E500_CFX_DivBypass
|
||||
def E500mc_SFX0 : FuncUnit; // Simple unit 0
|
||||
def E500mc_SFX1 : FuncUnit; // Simple unit 1
|
||||
def E500mc_BU : FuncUnit; // Branch unit
|
||||
def E500mc_CFX_DivBypass
|
||||
: FuncUnit; // CFX divide bypass path
|
||||
def E500_CFX_0 : FuncUnit; // CFX pipeline
|
||||
def E500_LSU_0 : FuncUnit; // LSU pipeline
|
||||
def E500_FPU_0 : FuncUnit; // FPU pipeline
|
||||
def E500mc_CFX_0 : FuncUnit; // CFX pipeline
|
||||
def E500mc_LSU_0 : FuncUnit; // LSU pipeline
|
||||
def E500mc_FPU_0 : FuncUnit; // FPU pipeline
|
||||
|
||||
def E500_GPR_Bypass : Bypass;
|
||||
def E500_FPR_Bypass : Bypass;
|
||||
def E500_CR_Bypass : Bypass;
|
||||
def E500mc_GPR_Bypass : Bypass;
|
||||
def E500mc_FPR_Bypass : Bypass;
|
||||
def E500mc_CR_Bypass : Bypass;
|
||||
|
||||
def PPCE500mcItineraries : ProcessorItineraries<
|
||||
[E500_DIS0, E500_DIS1, E500_SFX0, E500_SFX1, E500_BU, E500_CFX_DivBypass,
|
||||
E500_CFX_0, E500_LSU_0, E500_FPU_0],
|
||||
[E500_CR_Bypass, E500_GPR_Bypass, E500_FPR_Bypass], [
|
||||
InstrItinData<IIC_IntSimple, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0, E500_SFX1]>],
|
||||
[E500mc_DIS0, E500mc_DIS1, E500mc_SFX0, E500mc_SFX1, E500mc_BU, E500mc_CFX_DivBypass,
|
||||
E500mc_CFX_0, E500mc_LSU_0, E500mc_FPU_0],
|
||||
[E500mc_CR_Bypass, E500mc_GPR_Bypass, E500mc_FPR_Bypass], [
|
||||
InstrItinData<IIC_IntSimple, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
|
||||
[4, 1, 1], // Latency = 1
|
||||
[E500_GPR_Bypass,
|
||||
E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0, E500_SFX1]>],
|
||||
[E500mc_GPR_Bypass,
|
||||
E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
|
||||
[4, 1, 1], // Latency = 1
|
||||
[E500_GPR_Bypass,
|
||||
E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_IntISEL, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0, E500_SFX1]>],
|
||||
[E500mc_GPR_Bypass,
|
||||
E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_IntISEL, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
|
||||
[4, 1, 1, 1], // Latency = 1
|
||||
[E500_GPR_Bypass,
|
||||
E500_GPR_Bypass, E500_GPR_Bypass,
|
||||
E500_CR_Bypass]>,
|
||||
InstrItinData<IIC_IntCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0, E500_SFX1]>],
|
||||
[E500mc_GPR_Bypass,
|
||||
E500mc_GPR_Bypass, E500mc_GPR_Bypass,
|
||||
E500mc_CR_Bypass]>,
|
||||
InstrItinData<IIC_IntCompare, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
|
||||
[5, 1, 1], // Latency = 1 or 2
|
||||
[E500_CR_Bypass,
|
||||
E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_IntDivW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_CFX_0], 0>,
|
||||
InstrStage<14, [E500_CFX_DivBypass]>],
|
||||
[E500mc_CR_Bypass,
|
||||
E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_IntDivW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_CFX_0], 0>,
|
||||
InstrStage<14, [E500mc_CFX_DivBypass]>],
|
||||
[17, 1, 1], // Latency=4..35, Repeat= 4..35
|
||||
[E500_GPR_Bypass,
|
||||
E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_IntMFFS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<8, [E500_FPU_0]>],
|
||||
[E500mc_GPR_Bypass,
|
||||
E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_IntMFFS, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<8, [E500mc_FPU_0]>],
|
||||
[11], // Latency = 8
|
||||
[E500_FPR_Bypass]>,
|
||||
InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<8, [E500_FPU_0]>],
|
||||
[E500mc_FPR_Bypass]>,
|
||||
InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<8, [E500mc_FPU_0]>],
|
||||
[11, 1, 1], // Latency = 8
|
||||
[NoBypass, NoBypass, NoBypass]>,
|
||||
InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_CFX_0]>],
|
||||
InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_CFX_0]>],
|
||||
[7, 1, 1], // Latency = 4, Repeat rate = 1
|
||||
[E500_GPR_Bypass,
|
||||
E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_CFX_0]>],
|
||||
[E500mc_GPR_Bypass,
|
||||
E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_CFX_0]>],
|
||||
[7, 1, 1], // Latency = 4, Repeat rate = 1
|
||||
[E500_GPR_Bypass,
|
||||
E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_CFX_0]>],
|
||||
[E500mc_GPR_Bypass,
|
||||
E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_CFX_0]>],
|
||||
[7, 1, 1], // Latency = 4, Repeat rate = 1
|
||||
[E500_GPR_Bypass,
|
||||
E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_IntRotate, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0, E500_SFX1]>],
|
||||
[E500mc_GPR_Bypass,
|
||||
E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_IntRotate, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
|
||||
[4, 1, 1], // Latency = 1
|
||||
[E500_GPR_Bypass,
|
||||
E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_IntShift, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0, E500_SFX1]>],
|
||||
[E500mc_GPR_Bypass,
|
||||
E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_IntShift, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
|
||||
[4, 1, 1], // Latency = 1
|
||||
[E500_GPR_Bypass,
|
||||
E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<2, [E500_SFX0]>],
|
||||
[E500mc_GPR_Bypass,
|
||||
E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<2, [E500mc_SFX0]>],
|
||||
[5, 1], // Latency = 2, Repeat rate = 2
|
||||
[E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_BrB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_BU]>],
|
||||
[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_BrB, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_BU]>],
|
||||
[4, 1], // Latency = 1
|
||||
[NoBypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_BrCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_BU]>],
|
||||
[NoBypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_BrCR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_BU]>],
|
||||
[4, 1, 1], // Latency = 1
|
||||
[E500_CR_Bypass,
|
||||
E500_CR_Bypass, E500_CR_Bypass]>,
|
||||
InstrItinData<IIC_BrMCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_BU]>],
|
||||
[E500mc_CR_Bypass,
|
||||
E500mc_CR_Bypass, E500mc_CR_Bypass]>,
|
||||
InstrItinData<IIC_BrMCR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_BU]>],
|
||||
[4, 1], // Latency = 1
|
||||
[E500_CR_Bypass, E500_CR_Bypass]>,
|
||||
InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0, E500_SFX1]>],
|
||||
[E500mc_CR_Bypass, E500mc_CR_Bypass]>,
|
||||
InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
|
||||
[4, 1, 1], // Latency = 1
|
||||
[E500_CR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
[E500mc_CR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0]>],
|
||||
[6, 1], // Latency = 3, Repeat rate = 1
|
||||
[E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0]>],
|
||||
[6, 1], // Latency = 3
|
||||
[E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0]>],
|
||||
[6, 1], // Latency = 3
|
||||
[E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStLoad, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStLoad, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0]>],
|
||||
[6, 1], // Latency = 3
|
||||
[E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0]>],
|
||||
[6, 1], // Latency = 3
|
||||
[E500_GPR_Bypass, E500_GPR_Bypass],
|
||||
[E500mc_GPR_Bypass, E500mc_GPR_Bypass],
|
||||
2>, // 2 micro-ops
|
||||
InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0]>],
|
||||
[6, 1], // Latency = 3
|
||||
[E500_GPR_Bypass, E500_GPR_Bypass],
|
||||
[E500mc_GPR_Bypass, E500mc_GPR_Bypass],
|
||||
2>, // 2 micro-ops
|
||||
InstrItinData<IIC_LdStStore, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
InstrItinData<IIC_LdStStore, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0]>],
|
||||
[6, 1], // Latency = 3
|
||||
[NoBypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
[NoBypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0]>],
|
||||
[6, 1], // Latency = 3
|
||||
[NoBypass, E500_GPR_Bypass],
|
||||
[NoBypass, E500mc_GPR_Bypass],
|
||||
2>, // 2 micro-ops
|
||||
InstrItinData<IIC_LdStICBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
InstrItinData<IIC_LdStICBI, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0]>],
|
||||
[6, 1], // Latency = 3
|
||||
[NoBypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStSTFD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
[NoBypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStSTFD, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0]>],
|
||||
[6, 1, 1], // Latency = 3
|
||||
[E500_GPR_Bypass,
|
||||
E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
[E500mc_GPR_Bypass,
|
||||
E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0]>],
|
||||
[6, 1, 1], // Latency = 3
|
||||
[E500_GPR_Bypass,
|
||||
E500_GPR_Bypass, E500_GPR_Bypass],
|
||||
[E500mc_GPR_Bypass,
|
||||
E500mc_GPR_Bypass, E500mc_GPR_Bypass],
|
||||
2>, // 2 micro-ops
|
||||
InstrItinData<IIC_LdStLFD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
InstrItinData<IIC_LdStLFD, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0]>],
|
||||
[7, 1, 1], // Latency = 4
|
||||
[E500_FPR_Bypass,
|
||||
E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStLFDU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
[E500mc_FPR_Bypass,
|
||||
E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStLFDU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0]>],
|
||||
[7, 1, 1], // Latency = 4
|
||||
[E500_FPR_Bypass,
|
||||
E500_GPR_Bypass, E500_GPR_Bypass],
|
||||
[E500mc_FPR_Bypass,
|
||||
E500mc_GPR_Bypass, E500mc_GPR_Bypass],
|
||||
2>, // 2 micro-ops
|
||||
InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0]>],
|
||||
[7, 1, 1], // Latency = 4
|
||||
[E500_FPR_Bypass,
|
||||
E500_GPR_Bypass, E500_GPR_Bypass],
|
||||
[E500mc_FPR_Bypass,
|
||||
E500mc_GPR_Bypass, E500mc_GPR_Bypass],
|
||||
2>, // 2 micro-ops
|
||||
InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0]>],
|
||||
[6, 1], // Latency = 3
|
||||
[E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0]>],
|
||||
[6, 1], // Latency = 3
|
||||
[E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_SFX0, E500mc_SFX1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0]>],
|
||||
[6, 1], // Latency = 3
|
||||
[E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0]>],
|
||||
[7, 1], // Latency = r+3
|
||||
[NoBypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<3, [E500_LSU_0]>],
|
||||
[NoBypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<3, [E500mc_LSU_0]>],
|
||||
[6, 1, 1], // Latency = 3, Repeat rate = 3
|
||||
[E500_GPR_Bypass,
|
||||
E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>],
|
||||
[E500mc_GPR_Bypass,
|
||||
E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0]>],
|
||||
[6, 1], // Latency = 3
|
||||
[NoBypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStSync, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_LSU_0]>]>,
|
||||
InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<4, [E500_SFX0]>],
|
||||
[NoBypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_LdStSync, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0]>]>,
|
||||
InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<4, [E500mc_SFX0]>],
|
||||
[7, 1],
|
||||
[E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<2, [E500_SFX0, E500_SFX1]>],
|
||||
[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<2, [E500mc_SFX0, E500mc_SFX1]>],
|
||||
[5, 1], // Latency = 2, Repeat rate = 4
|
||||
[E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0]>],
|
||||
[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_SFX0]>],
|
||||
[5, 1],
|
||||
[NoBypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_LSU_0], 0>]>,
|
||||
InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<5, [E500_SFX0]>],
|
||||
[NoBypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_LSU_0], 0>]>,
|
||||
InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<5, [E500mc_SFX0]>],
|
||||
[8, 1],
|
||||
[E500_GPR_Bypass, E500_CR_Bypass]>,
|
||||
InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<5, [E500_SFX0]>],
|
||||
[E500mc_GPR_Bypass, E500mc_CR_Bypass]>,
|
||||
InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<5, [E500mc_SFX0]>],
|
||||
[8, 1],
|
||||
[E500_GPR_Bypass, E500_CR_Bypass]>,
|
||||
InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<4, [E500_SFX0]>],
|
||||
[E500mc_GPR_Bypass, E500mc_CR_Bypass]>,
|
||||
InstrItinData<IIC_SprMFPMR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<4, [E500mc_SFX0]>],
|
||||
[7, 1], // Latency = 4, Repeat rate = 4
|
||||
[E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<4, [E500_SFX0]>],
|
||||
[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<4, [E500mc_SFX0]>],
|
||||
[7, 1], // Latency = 4, Repeat rate = 4
|
||||
[E500_GPR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0, E500_SFX1]>],
|
||||
[E500mc_GPR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
|
||||
[4, 1], // Latency = 1, Repeat rate = 1
|
||||
[E500_GPR_Bypass, E500_CR_Bypass]>,
|
||||
InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0]>],
|
||||
[E500mc_GPR_Bypass, E500mc_CR_Bypass]>,
|
||||
InstrItinData<IIC_SprMTPMR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_SFX0]>],
|
||||
[4, 1], // Latency = 1, Repeat rate = 1
|
||||
[E500_CR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<4, [E500_SFX0]>],
|
||||
[E500mc_CR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<4, [E500mc_SFX0]>],
|
||||
[7, 1], // Latency = 4, Repeat rate = 4
|
||||
[NoBypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0, E500_SFX1]>],
|
||||
[NoBypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_SFX0, E500mc_SFX1]>],
|
||||
[4, 1], // Latency = 1, Repeat rate = 1
|
||||
[E500_CR_Bypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<1, [E500_SFX0]>],
|
||||
[E500mc_CR_Bypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<1, [E500mc_SFX0]>],
|
||||
[4, 1],
|
||||
[NoBypass, E500_GPR_Bypass]>,
|
||||
InstrItinData<IIC_FPGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<2, [E500_FPU_0]>],
|
||||
[NoBypass, E500mc_GPR_Bypass]>,
|
||||
InstrItinData<IIC_FPGeneral, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<2, [E500mc_FPU_0]>],
|
||||
[11, 1, 1], // Latency = 8, Repeat rate = 2
|
||||
[E500_FPR_Bypass,
|
||||
E500_FPR_Bypass, E500_FPR_Bypass]>,
|
||||
InstrItinData<IIC_FPAddSub, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<4, [E500_FPU_0]>],
|
||||
[E500mc_FPR_Bypass,
|
||||
E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,
|
||||
InstrItinData<IIC_FPAddSub, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<4, [E500mc_FPU_0]>],
|
||||
[13, 1, 1], // Latency = 10, Repeat rate = 4
|
||||
[E500_FPR_Bypass,
|
||||
E500_FPR_Bypass, E500_FPR_Bypass]>,
|
||||
InstrItinData<IIC_FPCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<2, [E500_FPU_0]>],
|
||||
[E500mc_FPR_Bypass,
|
||||
E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,
|
||||
InstrItinData<IIC_FPCompare, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<2, [E500mc_FPU_0]>],
|
||||
[11, 1, 1], // Latency = 8, Repeat rate = 2
|
||||
[E500_CR_Bypass,
|
||||
E500_FPR_Bypass, E500_FPR_Bypass]>,
|
||||
InstrItinData<IIC_FPDivD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<68, [E500_FPU_0]>],
|
||||
[E500mc_CR_Bypass,
|
||||
E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,
|
||||
InstrItinData<IIC_FPDivD, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<68, [E500mc_FPU_0]>],
|
||||
[71, 1, 1], // Latency = 68, Repeat rate = 68
|
||||
[E500_FPR_Bypass,
|
||||
E500_FPR_Bypass, E500_FPR_Bypass]>,
|
||||
InstrItinData<IIC_FPDivS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<38, [E500_FPU_0]>],
|
||||
[E500mc_FPR_Bypass,
|
||||
E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,
|
||||
InstrItinData<IIC_FPDivS, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<38, [E500mc_FPU_0]>],
|
||||
[41, 1, 1], // Latency = 38, Repeat rate = 38
|
||||
[E500_FPR_Bypass,
|
||||
E500_FPR_Bypass, E500_FPR_Bypass]>,
|
||||
InstrItinData<IIC_FPFused, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<4, [E500_FPU_0]>],
|
||||
[E500mc_FPR_Bypass,
|
||||
E500mc_FPR_Bypass, E500mc_FPR_Bypass]>,
|
||||
InstrItinData<IIC_FPFused, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<4, [E500mc_FPU_0]>],
|
||||
[13, 1, 1, 1], // Latency = 10, Repeat rate = 4
|
||||
[E500_FPR_Bypass,
|
||||
E500_FPR_Bypass, E500_FPR_Bypass,
|
||||
E500_FPR_Bypass]>,
|
||||
InstrItinData<IIC_FPRes, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
|
||||
InstrStage<38, [E500_FPU_0]>],
|
||||
[E500mc_FPR_Bypass,
|
||||
E500mc_FPR_Bypass, E500mc_FPR_Bypass,
|
||||
E500mc_FPR_Bypass]>,
|
||||
InstrItinData<IIC_FPRes, [InstrStage<1, [E500mc_DIS0, E500mc_DIS1], 0>,
|
||||
InstrStage<38, [E500mc_FPU_0]>],
|
||||
[41, 1], // Latency = 38, Repeat rate = 38
|
||||
[E500_FPR_Bypass, E500_FPR_Bypass]>
|
||||
[E500mc_FPR_Bypass, E500mc_FPR_Bypass]>
|
||||
]>;
|
||||
|
||||
// ===---------------------------------------------------------------------===//
|
||||
|
||||
@ -46,6 +46,7 @@ namespace PPC {
|
||||
DIR_750,
|
||||
DIR_970,
|
||||
DIR_A2,
|
||||
DIR_E500,
|
||||
DIR_E500mc,
|
||||
DIR_E5500,
|
||||
DIR_PWR3,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user