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Do not preset the cc register, the instructions actually use it.

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llvm-svn: 6637
This commit is contained in:
Misha Brukman 2003-06-05 23:30:27 +00:00
parent de307f15d4
commit 0c06cc4fb9
1 changed files with 17 additions and 20 deletions
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5
lib/Target/Sparc/SparcV9.td
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@ -77,10 +77,8 @@ set isDeprecated = 1 in {
}
#endif
// These instructions are hacked to really represent A.5 instructions,
// but with cc hardcoded to be %fcc0. Hence, they behave like FBPfcc instrs.
// We now make these same opcodes represent the FBPfcc instructions
set op2 = 0b101 in {
set cc = 0b00 in {
def FBA : F2_3<0b1000, "fba">; // Branch always
def FBN : F2_3<0b0000, "fbn">; // Branch never
def FBU : F2_3<0b0111, "fbu">; // Branch on unordered
@ -97,7 +95,6 @@ set op2 = 0b101 in {
def FBLE : F2_3<0b1101, "fble">; // Branch < or ==
def FBULE : F2_3<0b1110, "fbule">; // Branch unord or < or ==
def FBO : F2_3<0b1111, "fbo">; // Branch on ordered
}
}
// Section A.5: Branch on FP condition codes with prediction - p143