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MachineLICM CSE should match destination register classes; avoid hoisting implicit_def's.

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llvm-svn: 65592
This commit is contained in:
Evan Cheng 2009-02-27 00:02:22 +00:00
parent 971ec3c55c
commit 0ca6e3dba5
2 changed files with 60 additions and 3 deletions
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16
lib/CodeGen/MachineLICM.cpp
View File

@ -288,6 +288,9 @@ static bool HasPHIUses(unsigned Reg, MachineRegisterInfo *RegInfo) {
/// IsProfitableToHoist - Return true if it is potentially profitable to hoist
/// the given loop invariant.
bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
if (MI.getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
return false;
const TargetInstrDesc &TID = MI.getDesc();
// FIXME: For now, only hoist re-materilizable instructions. LICM will
@ -312,7 +315,8 @@ bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
}
static const MachineInstr *LookForDuplicate(const MachineInstr *MI,
std::vector<const MachineInstr*> &PrevMIs) {
std::vector<const MachineInstr*> &PrevMIs,
MachineRegisterInfo *RegInfo) {
unsigned NumOps = MI->getNumOperands();
for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) {
const MachineInstr *PrevMI = PrevMIs[i];
@ -322,8 +326,14 @@ static const MachineInstr *LookForDuplicate(const MachineInstr *MI,
bool IsSame = true;
for (unsigned j = 0; j != NumOps; ++j) {
const MachineOperand &MO = MI->getOperand(j);
if (MO.isReg() && MO.isDef())
if (MO.isReg() && MO.isDef()) {
if (RegInfo->getRegClass(MO.getReg()) !=
RegInfo->getRegClass(PrevMI->getOperand(j).getReg())) {
IsSame = false;
break;
}
continue;
}
if (!MO.isIdenticalTo(PrevMI->getOperand(j))) {
IsSame = false;
break;
@ -362,7 +372,7 @@ void MachineLICM::Hoist(MachineInstr &MI) {
std::vector<const MachineInstr*> >::iterator CI = CSEMap.find(BBOpcPair);
bool DoneCSE = false;
if (CI != CSEMap.end()) {
const MachineInstr *Dup = LookForDuplicate(&MI, CI->second);
const MachineInstr *Dup = LookForDuplicate(&MI, CI->second, RegInfo);
if (Dup) {
DOUT << "CSEing " << MI;
DOUT << " with " << *Dup;

47
test/CodeGen/X86/2009-02-26-MachineLICMBug.ll Normal file
View File

@ -0,0 +1,47 @@
; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse3 -stats |& not grep {machine-licm}
; rdar://6627786
target triple = "x86_64-apple-darwin10.0"
%struct.Key = type { i64 }
%struct.__Rec = type opaque
%struct.__vv = type { }
define %struct.__vv* @t(%struct.Key* %desc) nounwind ssp {
entry:
br label %bb4
bb4: ; preds = %bb.i, %bb26, %bb4, %entry
%0 = call i32 (...)* @xxGetOffsetForCode(i32 undef) nounwind ; <i32> [#uses=0]
%ins = or i64 0, 0 ; <i64> [#uses=1]
%1 = call i32 (...)* @xxCalculateMidType(%struct.Key* %desc, i32 0) nounwind ; <i32> [#uses=1]
%cond = icmp eq i32 %1, 1 ; <i1> [#uses=1]
br i1 %cond, label %bb26, label %bb4
bb26: ; preds = %bb4
%2 = and i64 %ins, 15728640 ; <i64> [#uses=1]
%cond.i = icmp eq i64 %2, 1048576 ; <i1> [#uses=1]
br i1 %cond.i, label %bb.i, label %bb4
bb.i: ; preds = %bb26
%3 = load i32* null, align 4 ; <i32> [#uses=1]
%4 = uitofp i32 %3 to float ; <float> [#uses=1]
%.sum13.i = add i64 0, 4 ; <i64> [#uses=1]
%5 = getelementptr i8* null, i64 %.sum13.i ; <i8*> [#uses=1]
%6 = bitcast i8* %5 to i32* ; <i32*> [#uses=1]
%7 = load i32* %6, align 4 ; <i32> [#uses=1]
%8 = uitofp i32 %7 to float ; <float> [#uses=1]
%.sum.i = add i64 0, 8 ; <i64> [#uses=1]
%9 = getelementptr i8* null, i64 %.sum.i ; <i8*> [#uses=1]
%10 = bitcast i8* %9 to i32* ; <i32*> [#uses=1]
%11 = load i32* %10, align 4 ; <i32> [#uses=1]
%12 = uitofp i32 %11 to float ; <float> [#uses=1]
%13 = insertelement <4 x float> undef, float %4, i32 0 ; <<4 x float>> [#uses=1]
%14 = insertelement <4 x float> %13, float %8, i32 1 ; <<4 x float>> [#uses=1]
%15 = insertelement <4 x float> %14, float %12, i32 2 ; <<4 x float>> [#uses=1]
store <4 x float> %15, <4 x float>* null, align 16
br label %bb4
}
declare i32 @xxGetOffsetForCode(...)
declare i32 @xxCalculateMidType(...)