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Fix vector sign extend to put the source and destination types in the
correct places. llvm-svn: 124601
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@ -1167,7 +1167,7 @@ class XSHWRegInst<RegisterClass rclass>:
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[(set rclass:$rDest, (sext R16C:$rSrc))]>;
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multiclass ExtendHalfwordWord {
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def v4i32: XSHWVecInst<v4i32, v8i16>;
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def v4i32: XSHWVecInst<v8i16, v4i32>;
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def r16: XSHWRegInst<R32C>;
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