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[AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsics
Now we have vec3 MVTs, this commit implements dwordx3 variants of the buffer intrinsics. On gfx6, a dwordx3 buffer load intrinsic is implemented as a dwordx4 instruction, and a dwordx3 buffer store intrinsic is not supported. We need to support the dwordx3 load intrinsic because it is generated by subtarget-unaware code in InstCombine. Differential Revision: https://reviews.llvm.org/D58904 Change-Id: I016729d8557b98a52f529638ae97c340a5922a4e llvm-svn: 356755
This commit is contained in:
Tim Renouf
parent
0fb5431a56
commit
0e8face627
@ -4295,7 +4295,6 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
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NODE_NAME_CASE(STORE_MSKOR)
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NODE_NAME_CASE(LOAD_CONSTANT)
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NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
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NODE_NAME_CASE(TBUFFER_STORE_FORMAT_X3)
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NODE_NAME_CASE(TBUFFER_STORE_FORMAT_D16)
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NODE_NAME_CASE(TBUFFER_LOAD_FORMAT)
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NODE_NAME_CASE(TBUFFER_LOAD_FORMAT_D16)
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@ -494,7 +494,6 @@ enum NodeType : unsigned {
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STORE_MSKOR,
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LOAD_CONSTANT,
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TBUFFER_STORE_FORMAT,
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TBUFFER_STORE_FORMAT_X3,
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TBUFFER_STORE_FORMAT_D16,
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TBUFFER_LOAD_FORMAT,
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TBUFFER_LOAD_FORMAT_D16,
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@ -1011,11 +1011,11 @@ def BUFFER_WBINVL1 : MUBUF_Invalidate <"buffer_wbinvl1",
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defm TBUFFER_LOAD_FORMAT_X : MTBUF_Pseudo_Loads <"tbuffer_load_format_x", VGPR_32>;
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defm TBUFFER_LOAD_FORMAT_XY : MTBUF_Pseudo_Loads <"tbuffer_load_format_xy", VReg_64>;
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defm TBUFFER_LOAD_FORMAT_XYZ : MTBUF_Pseudo_Loads <"tbuffer_load_format_xyz", VReg_128>;
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defm TBUFFER_LOAD_FORMAT_XYZ : MTBUF_Pseudo_Loads <"tbuffer_load_format_xyz", VReg_96>;
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defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Pseudo_Loads <"tbuffer_load_format_xyzw", VReg_128>;
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defm TBUFFER_STORE_FORMAT_X : MTBUF_Pseudo_Stores <"tbuffer_store_format_x", VGPR_32>;
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defm TBUFFER_STORE_FORMAT_XY : MTBUF_Pseudo_Stores <"tbuffer_store_format_xy", VReg_64>;
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defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Pseudo_Stores <"tbuffer_store_format_xyz", VReg_128>;
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defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Pseudo_Stores <"tbuffer_store_format_xyz", VReg_96>;
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defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Pseudo_Stores <"tbuffer_store_format_xyzw", VReg_128>;
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let SubtargetPredicate = HasUnpackedD16VMem, D16Buf = 1 in {
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@ -1104,6 +1104,8 @@ defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, f32, "BUFFER_LOAD_FORMAT_X">
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, i32, "BUFFER_LOAD_FORMAT_X">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v2f32, "BUFFER_LOAD_FORMAT_XY">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v2i32, "BUFFER_LOAD_FORMAT_XY">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v3f32, "BUFFER_LOAD_FORMAT_XYZ">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v3i32, "BUFFER_LOAD_FORMAT_XYZ">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v4f32, "BUFFER_LOAD_FORMAT_XYZW">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_format, v4i32, "BUFFER_LOAD_FORMAT_XYZW">;
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@ -1127,6 +1129,8 @@ defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, f32, "BUFFER_LOAD_DWORD">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, i32, "BUFFER_LOAD_DWORD">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v2f32, "BUFFER_LOAD_DWORDX2">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v2i32, "BUFFER_LOAD_DWORDX2">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v3f32, "BUFFER_LOAD_DWORDX3">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v3i32, "BUFFER_LOAD_DWORDX3">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v4f32, "BUFFER_LOAD_DWORDX4">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load, v4i32, "BUFFER_LOAD_DWORDX4">;
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defm : MUBUF_LoadIntrinsicPat<SIbuffer_load_byte, i32, "BUFFER_LOAD_SBYTE">;
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@ -1172,6 +1176,8 @@ defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, f32, "BUFFER_STORE_FORMAT_
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defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, i32, "BUFFER_STORE_FORMAT_X">;
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defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v2f32, "BUFFER_STORE_FORMAT_XY">;
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defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v2i32, "BUFFER_STORE_FORMAT_XY">;
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defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v3f32, "BUFFER_STORE_FORMAT_XYZ">;
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defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v3i32, "BUFFER_STORE_FORMAT_XYZ">;
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defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v4f32, "BUFFER_STORE_FORMAT_XYZW">;
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defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_format, v4i32, "BUFFER_STORE_FORMAT_XYZW">;
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@ -1195,6 +1201,8 @@ defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, f32, "BUFFER_STORE_DWORD">;
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defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, i32, "BUFFER_STORE_DWORD">;
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defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, v2f32, "BUFFER_STORE_DWORDX2">;
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defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, v2i32, "BUFFER_STORE_DWORDX2">;
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defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, v3f32, "BUFFER_STORE_DWORDX3">;
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defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, v3i32, "BUFFER_STORE_DWORDX3">;
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defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, v4f32, "BUFFER_STORE_DWORDX4">;
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defm : MUBUF_StoreIntrinsicPat<SIbuffer_store, v4i32, "BUFFER_STORE_DWORDX4">;
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defm : MUBUF_StoreIntrinsicPat<SIbuffer_store_byte, i32, "BUFFER_STORE_BYTE">;
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@ -1535,9 +1543,11 @@ multiclass MTBUF_LoadIntrinsicPat<SDPatternOperator name, ValueType vt,
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defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, i32, "TBUFFER_LOAD_FORMAT_X">;
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defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v2i32, "TBUFFER_LOAD_FORMAT_XY">;
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defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v3i32, "TBUFFER_LOAD_FORMAT_XYZ">;
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defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v4i32, "TBUFFER_LOAD_FORMAT_XYZW">;
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defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, f32, "TBUFFER_LOAD_FORMAT_X">;
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defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v2f32, "TBUFFER_LOAD_FORMAT_XY">;
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defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v3f32, "TBUFFER_LOAD_FORMAT_XYZ">;
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defm : MTBUF_LoadIntrinsicPat<SItbuffer_load, v4f32, "TBUFFER_LOAD_FORMAT_XYZW">;
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let SubtargetPredicate = HasUnpackedD16VMem in {
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@ -1591,11 +1601,11 @@ multiclass MTBUF_StoreIntrinsicPat<SDPatternOperator name, ValueType vt,
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defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, i32, "TBUFFER_STORE_FORMAT_X">;
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defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v2i32, "TBUFFER_STORE_FORMAT_XY">;
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defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_x3, v4i32, "TBUFFER_STORE_FORMAT_XYZ">;
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defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v3i32, "TBUFFER_STORE_FORMAT_XYZ">;
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defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v4i32, "TBUFFER_STORE_FORMAT_XYZW">;
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defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, f32, "TBUFFER_STORE_FORMAT_X">;
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defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v2f32, "TBUFFER_STORE_FORMAT_XY">;
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defm : MTBUF_StoreIntrinsicPat<SItbuffer_store_x3, v4f32, "TBUFFER_STORE_FORMAT_XYZ">;
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defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v3f32, "TBUFFER_STORE_FORMAT_XYZ">;
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defm : MTBUF_StoreIntrinsicPat<SItbuffer_store, v4f32, "TBUFFER_STORE_FORMAT_XYZW">;
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let SubtargetPredicate = HasUnpackedD16VMem in {
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@ -5625,8 +5625,8 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
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LoadVT.getScalarType() == MVT::i16)
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return handleByteShortBufferLoads(DAG, LoadVT, DL, Ops, M);
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return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops, IntVT,
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M->getMemOperand());
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return getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops, IntVT,
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M->getMemOperand(), DAG);
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}
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case Intrinsic::amdgcn_raw_buffer_load:
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case Intrinsic::amdgcn_raw_buffer_load_format: {
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@ -5659,8 +5659,8 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
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LoadVT.getScalarType() == MVT::i16)
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return handleByteShortBufferLoads(DAG, LoadVT, DL, Ops, M);
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return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops, IntVT,
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M->getMemOperand());
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return getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops, IntVT,
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M->getMemOperand(), DAG);
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}
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case Intrinsic::amdgcn_struct_buffer_load:
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case Intrinsic::amdgcn_struct_buffer_load_format: {
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@ -5693,8 +5693,8 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
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LoadVT.getScalarType() == MVT::i16)
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return handleByteShortBufferLoads(DAG, LoadVT, DL, Ops, M);
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return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops, IntVT,
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M->getMemOperand());
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return getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops, IntVT,
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M->getMemOperand(), DAG);
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}
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case Intrinsic::amdgcn_tbuffer_load: {
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MemSDNode *M = cast<MemSDNode>(Op);
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@ -5722,9 +5722,9 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
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if (LoadVT.getScalarType() == MVT::f16)
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return adjustLoadValueType(AMDGPUISD::TBUFFER_LOAD_FORMAT_D16,
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M, DAG, Ops);
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return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_LOAD_FORMAT, DL,
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Op->getVTList(), Ops, LoadVT,
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M->getMemOperand());
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return getMemIntrinsicNode(AMDGPUISD::TBUFFER_LOAD_FORMAT, DL,
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Op->getVTList(), Ops, LoadVT, M->getMemOperand(),
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DAG);
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}
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case Intrinsic::amdgcn_raw_tbuffer_load: {
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MemSDNode *M = cast<MemSDNode>(Op);
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@ -5746,9 +5746,9 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
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if (LoadVT.getScalarType() == MVT::f16)
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return adjustLoadValueType(AMDGPUISD::TBUFFER_LOAD_FORMAT_D16,
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M, DAG, Ops);
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return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_LOAD_FORMAT, DL,
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Op->getVTList(), Ops, LoadVT,
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M->getMemOperand());
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return getMemIntrinsicNode(AMDGPUISD::TBUFFER_LOAD_FORMAT, DL,
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Op->getVTList(), Ops, LoadVT, M->getMemOperand(),
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DAG);
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}
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case Intrinsic::amdgcn_struct_tbuffer_load: {
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MemSDNode *M = cast<MemSDNode>(Op);
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@ -5770,9 +5770,9 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
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if (LoadVT.getScalarType() == MVT::f16)
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return adjustLoadValueType(AMDGPUISD::TBUFFER_LOAD_FORMAT_D16,
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M, DAG, Ops);
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return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_LOAD_FORMAT, DL,
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Op->getVTList(), Ops, LoadVT,
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M->getMemOperand());
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return getMemIntrinsicNode(AMDGPUISD::TBUFFER_LOAD_FORMAT, DL,
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Op->getVTList(), Ops, LoadVT, M->getMemOperand(),
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DAG);
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}
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case Intrinsic::amdgcn_buffer_atomic_swap:
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case Intrinsic::amdgcn_buffer_atomic_add:
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@ -6047,6 +6047,39 @@ SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
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}
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}
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// Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to
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// dwordx4 if on SI.
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SDValue SITargetLowering::getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL,
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SDVTList VTList,
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ArrayRef<SDValue> Ops, EVT MemVT,
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MachineMemOperand *MMO,
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SelectionDAG &DAG) const {
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EVT VT = VTList.VTs[0];
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EVT WidenedVT = VT;
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EVT WidenedMemVT = MemVT;
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if (!Subtarget->hasDwordx3LoadStores() &&
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(WidenedVT == MVT::v3i32 || WidenedVT == MVT::v3f32)) {
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WidenedVT = EVT::getVectorVT(*DAG.getContext(),
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WidenedVT.getVectorElementType(), 4);
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WidenedMemVT = EVT::getVectorVT(*DAG.getContext(),
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WidenedMemVT.getVectorElementType(), 4);
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MMO = DAG.getMachineFunction().getMachineMemOperand(MMO, 0, 16);
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}
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assert(VTList.NumVTs == 2);
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SDVTList WidenedVTList = DAG.getVTList(WidenedVT, VTList.VTs[1]);
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auto NewOp = DAG.getMemIntrinsicNode(Opcode, DL, WidenedVTList, Ops,
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WidenedMemVT, MMO);
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if (WidenedVT != VT) {
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auto Extract = DAG.getNode(
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ISD::EXTRACT_SUBVECTOR, DL, VT, NewOp,
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DAG.getConstant(0, DL, getVectorIdxTy(DAG.getDataLayout())));
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NewOp = DAG.getMergeValues({ Extract, SDValue(NewOp.getNode(), 1) }, DL);
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}
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return NewOp;
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}
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SDValue SITargetLowering::handleD16VData(SDValue VData,
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SelectionDAG &DAG) const {
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EVT StoreVT = VData.getValueType();
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@ -94,6 +94,12 @@ private:
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SelectionDAG &DAG, ArrayRef<SDValue> Ops,
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bool IsIntrinsic = false) const;
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// Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to
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// dwordx4 if on SI.
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SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
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ArrayRef<SDValue> Ops, EVT MemVT,
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MachineMemOperand *MMO, SelectionDAG &DAG) const;
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SDValue handleD16VData(SDValue VData, SelectionDAG &DAG) const;
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/// Converts \p Op, which must be of floating point type, to the
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@ -108,9 +108,6 @@ def SDTtbuffer_store : SDTypeProfile<0, 9,
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def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT", SDTtbuffer_store,
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[SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
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def SItbuffer_store_x3 : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT_X3",
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SDTtbuffer_store,
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[SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
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def SItbuffer_store_d16 : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT_D16",
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SDTtbuffer_store,
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[SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
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60
test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.dwordx3.ll
Normal file
60
test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.dwordx3.ll
Normal file
@ -0,0 +1,60 @@
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;RUN: llc < %s -march=amdgcn -mcpu=gfx600 -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,SI
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;RUN: llc < %s -march=amdgcn -mcpu=gfx700 -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,GCNX3
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;CHECK-LABEL: {{^}}buffer_load_format_immoffs_x3:
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;SI: buffer_load_format_xyzw v[0:3], off, s[0:3], 0 offset:42
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;GCNX3: buffer_load_format_xyz v[0:2], off, s[0:3], 0 offset:42
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;CHECK: s_waitcnt
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define amdgpu_ps <3 x float> @buffer_load_format_immoffs_x3(<4 x i32> inreg) {
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main_body:
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%data = call <3 x float> @llvm.amdgcn.buffer.load.format.v3f32(<4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
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ret <3 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_load_immoffs_x3:
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;SI: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:40
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;GCNX3: buffer_load_dwordx3 v[0:2], off, s[0:3], 0 offset:40
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;CHECK: s_waitcnt
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define amdgpu_ps <3 x float> @buffer_load_immoffs_x3(<4 x i32> inreg) {
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main_body:
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%data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %0, i32 0, i32 40, i1 0, i1 0)
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ret <3 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_raw_load_immoffs_x3:
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;SI: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:40
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;GCNX3: buffer_load_dwordx3 v[0:2], off, s[0:3], 0 offset:40
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;CHECK: s_waitcnt
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define amdgpu_ps <3 x float> @buffer_raw_load_immoffs_x3(<4 x i32> inreg) {
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main_body:
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%data = call <3 x float> @llvm.amdgcn.raw.buffer.load.v3f32(<4 x i32> %0, i32 40, i32 0, i32 0)
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ret <3 x float> %data
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}
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;CHECK-LABEL: {{^}}buffer_struct_load_format_immoffs_x3:
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;SI: buffer_load_format_xyzw v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:42
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;GCNX3: buffer_load_format_xyz v[0:2], {{v[0-9]+}}, s[0:3], 0 idxen offset:42
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;CHECK: s_waitcnt
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define amdgpu_ps <3 x float> @buffer_struct_load_format_immoffs_x3(<4 x i32> inreg) {
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main_body:
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%data = call <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32> %0, i32 0, i32 42, i32 0, i32 0)
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ret <3 x float> %data
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}
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;CHECK-LABEL: {{^}}struct_buffer_load_immoffs_x3:
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;SI: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:40
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;GCNX3: buffer_load_dwordx3 v[0:2], {{v[0-9]+}}, s[0:3], 0 idxen offset:40
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;CHECK: s_waitcnt
|
||||
define amdgpu_ps <3 x float> @struct_buffer_load_immoffs_x3(<4 x i32> inreg) {
|
||||
main_body:
|
||||
%data = call <3 x float> @llvm.amdgcn.struct.buffer.load.v3f32(<4 x i32> %0, i32 0, i32 40, i32 0, i32 0)
|
||||
ret <3 x float> %data
|
||||
}
|
||||
|
||||
declare <3 x float> @llvm.amdgcn.buffer.load.format.v3f32(<4 x i32>, i32, i32, i1, i1) #0
|
||||
declare <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32>, i32, i32, i1, i1) #0
|
||||
declare <3 x float> @llvm.amdgcn.raw.buffer.load.format.v3f32(<4 x i32>, i32, i32, i32) #0
|
||||
declare <3 x float> @llvm.amdgcn.raw.buffer.load.v3f32(<4 x i32>, i32, i32, i32) #0
|
||||
declare <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32>, i32, i32, i32, i32) #0
|
||||
declare <3 x float> @llvm.amdgcn.struct.buffer.load.v3f32(<4 x i32>, i32, i32, i32, i32) #0
|
||||
|
||||
53
test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.dwordx3.ll
Normal file
53
test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.dwordx3.ll
Normal file
@ -0,0 +1,53 @@
|
||||
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK
|
||||
|
||||
;CHECK-LABEL: {{^}}buffer_store_format_immoffs_x3:
|
||||
;CHECK-NOT: s_waitcnt
|
||||
;CHECK: buffer_store_format_xyz v[0:2], off, s[0:3], 0 offset:42
|
||||
define amdgpu_ps void @buffer_store_format_immoffs_x3(<4 x i32> inreg, <3 x float>) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.buffer.store.format.v3f32(<3 x float> %1, <4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}buffer_store_immoffs_x3:
|
||||
;CHECK-NOT: s_waitcnt
|
||||
;CHECK: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 offset:42
|
||||
define amdgpu_ps void @buffer_store_immoffs_x3(<4 x i32> inreg, <3 x float>) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.buffer.store.v3f32(<3 x float> %1, <4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}raw_buffer_store_format_immoffs_x3:
|
||||
;CHECK-NOT: s_waitcnt
|
||||
;CHECK: buffer_store_format_xyz v[0:2], off, s[0:3], 0 offset:42
|
||||
define amdgpu_ps void @raw_buffer_store_format_immoffs_x3(<4 x i32> inreg, <3 x float>) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.raw.buffer.store.format.v3f32(<3 x float> %1, <4 x i32> %0, i32 42, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}raw_buffer_store_immoffs_x3:
|
||||
;CHECK-NOT: s_waitcnt
|
||||
;CHECK: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 offset:42
|
||||
define amdgpu_ps void @raw_buffer_store_immoffs_x3(<4 x i32> inreg, <3 x float>) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.raw.buffer.store.v3f32(<3 x float> %1, <4 x i32> %0, i32 42, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}struct_buffer_store_immoffs_x3:
|
||||
;CHECK-NOT: s_waitcnt
|
||||
;CHECK: buffer_store_dwordx3 v[0:2], {{v[0-9]+}}, s[0:3], 0 idxen offset:42
|
||||
define amdgpu_ps void @struct_buffer_store_immoffs_x3(<4 x i32> inreg, <3 x float>) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.struct.buffer.store.v3f32(<3 x float> %1, <4 x i32> %0, i32 0, i32 42, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.amdgcn.buffer.store.v3f32(<3 x float>, <4 x i32>, i32, i32, i1, i1) #0
|
||||
declare void @llvm.amdgcn.buffer.store.format.v3f32(<3 x float>, <4 x i32>, i32, i32, i1, i1) #0
|
||||
declare void @llvm.amdgcn.raw.buffer.store.format.v3f32(<3 x float>, <4 x i32>, i32, i32, i32) #0
|
||||
declare void @llvm.amdgcn.raw.buffer.store.v3f32(<3 x float>, <4 x i32>, i32, i32, i32) #0
|
||||
declare void @llvm.amdgcn.struct.buffer.store.format.v3f32(<3 x float>, <4 x i32>, i32, i32, i32, i32) #0
|
||||
declare void @llvm.amdgcn.struct.buffer.store.v3f32(<3 x float>, <4 x i32>, i32, i32, i32, i32) #0
|
||||
40
test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.dwordx3.ll
Normal file
40
test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.dwordx3.ll
Normal file
@ -0,0 +1,40 @@
|
||||
;RUN: llc < %s -march=amdgcn -mcpu=gfx600 -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,SI
|
||||
;RUN: llc < %s -march=amdgcn -mcpu=gfx700 -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,GCNX3
|
||||
|
||||
; GCN-LABEL: {{^}}tbuffer_raw_load_immoffs_x3:
|
||||
; SI: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offset:42
|
||||
; GCNX3: tbuffer_load_format_xyz {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offset:42
|
||||
define amdgpu_vs <3 x float> @tbuffer_raw_load_immoffs_x3(<4 x i32> inreg) {
|
||||
main_body:
|
||||
%vdata = call <3 x i32> @llvm.amdgcn.raw.tbuffer.load.v3i32(<4 x i32> %0, i32 42, i32 0, i32 78, i32 0)
|
||||
%vdata.f = bitcast <3 x i32> %vdata to <3 x float>
|
||||
ret <3 x float> %vdata.f
|
||||
}
|
||||
|
||||
|
||||
; GCN-LABEL: {{^}}tbuffer_struct_load_immoffs_x3:
|
||||
; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0
|
||||
; SI: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 idxen offset:42
|
||||
; GCNX3: tbuffer_load_format_xyz {{v\[[0-9]+:[0-9]+\]}}, [[ZEROREG]], {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 idxen offset:42
|
||||
define amdgpu_vs <3 x float> @tbuffer_struct_load_immoffs_x3(<4 x i32> inreg) {
|
||||
main_body:
|
||||
%vdata = call <3 x i32> @llvm.amdgcn.struct.tbuffer.load.v3i32(<4 x i32> %0, i32 0, i32 42, i32 0, i32 78, i32 0)
|
||||
%vdata.f = bitcast <3 x i32> %vdata to <3 x float>
|
||||
ret <3 x float> %vdata.f
|
||||
}
|
||||
|
||||
|
||||
; GCN-LABEL: {{^}}tbuffer_load_format_immoffs_x3:
|
||||
; SI: tbuffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offset:42
|
||||
; GCNX3: tbuffer_load_format_xyz {{v\[[0-9]+:[0-9]+\]}}, off, {{s\[[0-9]+:[0-9]+\]}}, dfmt:14, nfmt:4, 0 offset:42
|
||||
define amdgpu_vs <3 x float> @tbuffer_load_format_immoffs_x3(<4 x i32> inreg) {
|
||||
main_body:
|
||||
%vdata = call <3 x i32> @llvm.amdgcn.tbuffer.load.v3i32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 42, i32 14, i32 4, i1 0, i1 0)
|
||||
%vdata.f = bitcast <3 x i32> %vdata to <3 x float>
|
||||
ret <3 x float> %vdata.f
|
||||
}
|
||||
|
||||
declare <3 x i32> @llvm.amdgcn.raw.tbuffer.load.v3i32(<4 x i32>, i32, i32, i32, i32)
|
||||
declare <3 x i32> @llvm.amdgcn.struct.tbuffer.load.v3i32(<4 x i32>, i32, i32, i32, i32, i32)
|
||||
declare <3 x i32> @llvm.amdgcn.tbuffer.load.v3i32(<4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)
|
||||
|
||||
35
test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.dwordx3.ll
Normal file
35
test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.dwordx3.ll
Normal file
@ -0,0 +1,35 @@
|
||||
;RUN: llc < %s -march=amdgcn -mcpu=gfx700 -verify-machineinstrs | FileCheck %s -check-prefixes=GCN
|
||||
|
||||
; GCN-LABEL: {{^}}tbuffer_raw_store_immoffs_x3:
|
||||
; GCN: tbuffer_store_format_xyz v[0:2], off, s[0:3], dfmt:5, nfmt:7, 0 offset:42
|
||||
define amdgpu_ps void @tbuffer_raw_store_immoffs_x3(<4 x i32> inreg, <3 x float>) {
|
||||
main_body:
|
||||
%in1 = bitcast <3 x float> %1 to <3 x i32>
|
||||
call void @llvm.amdgcn.raw.tbuffer.store.v3i32(<3 x i32> %in1, <4 x i32> %0, i32 42, i32 0, i32 117, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
; GCN-LABEL: {{^}}tbuffer_struct_store_immoffs_x3:
|
||||
; GCN: v_mov_b32_e32 [[ZEROREG:v[0-9]+]], 0
|
||||
; GCN: tbuffer_store_format_xyz v[0:2], [[ZEROREG]], s[0:3], dfmt:5, nfmt:7, 0 idxen offset:42
|
||||
define amdgpu_ps void @tbuffer_struct_store_immoffs_x3(<4 x i32> inreg, <3 x float>) {
|
||||
main_body:
|
||||
%in1 = bitcast <3 x float> %1 to <3 x i32>
|
||||
call void @llvm.amdgcn.struct.tbuffer.store.v3i32(<3 x i32> %in1, <4 x i32> %0, i32 0, i32 42, i32 0, i32 117, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}tbuffer_store_immoffs_x3:
|
||||
; GCN: tbuffer_store_format_xyz v[0:2], off, s[0:3], dfmt:5, nfmt:7, 0 offset:42
|
||||
define amdgpu_ps void @tbuffer_store_immoffs_x3(<4 x i32> inreg, <3 x float>) {
|
||||
main_body:
|
||||
%in1 = bitcast <3 x float> %1 to <3 x i32>
|
||||
call void @llvm.amdgcn.tbuffer.store.v3i32(<3 x i32> %in1, <4 x i32> %0, i32 0, i32 0, i32 0, i32 42, i32 5, i32 7, i1 0, i1 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.amdgcn.raw.tbuffer.store.v3i32(<3 x i32>, <4 x i32>, i32, i32, i32, i32) #0
|
||||
declare void @llvm.amdgcn.struct.tbuffer.store.v3i32(<3 x i32>, <4 x i32>, i32, i32, i32, i32, i32) #0
|
||||
declare void @llvm.amdgcn.tbuffer.store.v3i32(<3 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) #0
|
||||
|
||||
@ -14,9 +14,9 @@ tbuffer_load_format_xy v[1:2], off, s[4:7], dfmt:15, nfmt:2, s1
|
||||
// SICI: tbuffer_load_format_xy v[1:2], off, s[4:7], dfmt:15, nfmt:2, s1 ; encoding: [0x00,0x00,0x79,0xe9,0x00,0x01,0x01,0x01]
|
||||
// VI: tbuffer_load_format_xy v[1:2], off, s[4:7], dfmt:15, nfmt:2, s1 ; encoding: [0x00,0x80,0x78,0xe9,0x00,0x01,0x01,0x01]
|
||||
|
||||
tbuffer_load_format_xyz v[1:4], off, s[4:7], dfmt:15, nfmt:2, s1
|
||||
// SICI: tbuffer_load_format_xyz v[1:4], off, s[4:7], dfmt:15, nfmt:2, s1 ; encoding: [0x00,0x00,0x7a,0xe9,0x00,0x01,0x01,0x01]
|
||||
// VI: tbuffer_load_format_xyz v[1:4], off, s[4:7], dfmt:15, nfmt:2, s1 ; encoding: [0x00,0x00,0x79,0xe9,0x00,0x01,0x01,0x01]
|
||||
tbuffer_load_format_xyz v[1:3], off, s[4:7], dfmt:15, nfmt:2, s1
|
||||
// SICI: tbuffer_load_format_xyz v[1:3], off, s[4:7], dfmt:15, nfmt:2, s1 ; encoding: [0x00,0x00,0x7a,0xe9,0x00,0x01,0x01,0x01]
|
||||
// VI: tbuffer_load_format_xyz v[1:3], off, s[4:7], dfmt:15, nfmt:2, s1 ; encoding: [0x00,0x00,0x79,0xe9,0x00,0x01,0x01,0x01]
|
||||
|
||||
tbuffer_load_format_xyzw v[1:4], off, s[4:7], dfmt:15, nfmt:2, s1
|
||||
// SICI: tbuffer_load_format_xyzw v[1:4], off, s[4:7], dfmt:15, nfmt:2, s1 ; encoding: [0x00,0x00,0x7b,0xe9,0x00,0x01,0x01,0x01]
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user