mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-02-09 13:55:22 +00:00
AMDGPU/GlobalISel: Legalize GEP for other 32-bit address spaces
llvm-svn: 366621
This commit is contained in:
Matt Arsenault
parent
1ace6d5780
commit
0e9abc2fbd
@ -151,7 +151,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
|
||||
|
||||
const LLT GlobalPtr = GetAddrSpacePtr(AMDGPUAS::GLOBAL_ADDRESS);
|
||||
const LLT ConstantPtr = GetAddrSpacePtr(AMDGPUAS::CONSTANT_ADDRESS);
|
||||
const LLT Constant32Ptr = GetAddrSpacePtr(AMDGPUAS::CONSTANT_ADDRESS_32BIT);
|
||||
const LLT LocalPtr = GetAddrSpacePtr(AMDGPUAS::LOCAL_ADDRESS);
|
||||
const LLT RegionPtr = GetAddrSpacePtr(AMDGPUAS::REGION_ADDRESS);
|
||||
const LLT FlatPtr = GetAddrSpacePtr(AMDGPUAS::FLAT_ADDRESS);
|
||||
const LLT PrivatePtr = GetAddrSpacePtr(AMDGPUAS::PRIVATE_ADDRESS);
|
||||
|
||||
@ -162,7 +164,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
|
||||
};
|
||||
|
||||
const std::initializer_list<LLT> AddrSpaces32 = {
|
||||
LocalPtr, PrivatePtr
|
||||
LocalPtr, PrivatePtr, Constant32Ptr, RegionPtr
|
||||
};
|
||||
|
||||
const std::initializer_list<LLT> FPTypesBase = {
|
||||
|
||||
@ -352,3 +352,89 @@ body: |
|
||||
S_ENDPGM 0, implicit %2
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: gep_p6_sgpr_sgpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
; GFX6-LABEL: name: gep_p6_sgpr_sgpr
|
||||
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX6: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX6: S_ENDPGM 0, implicit [[S_ADD_U32_]]
|
||||
; GFX8-LABEL: name: gep_p6_sgpr_sgpr
|
||||
; GFX8: $vcc_hi = IMPLICIT_DEF
|
||||
; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX8: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX8: S_ENDPGM 0, implicit [[S_ADD_U32_]]
|
||||
; GFX9-LABEL: name: gep_p6_sgpr_sgpr
|
||||
; GFX9: $vcc_hi = IMPLICIT_DEF
|
||||
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX9: S_ENDPGM 0, implicit [[S_ADD_U32_]]
|
||||
; GFX10-WAVE64-LABEL: name: gep_p6_sgpr_sgpr
|
||||
; GFX10-WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX10-WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX10-WAVE64: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX10-WAVE64: S_ENDPGM 0, implicit [[S_ADD_U32_]]
|
||||
; GFX10-WAVE32-LABEL: name: gep_p6_sgpr_sgpr
|
||||
; GFX10-WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; GFX10-WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX10-WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX10-WAVE32: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX10-WAVE32: S_ENDPGM 0, implicit [[S_ADD_U32_]]
|
||||
%0:sgpr(p6) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:sgpr(p6) = G_GEP %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: gep_p2_sgpr_sgpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
; GFX6-LABEL: name: gep_p2_sgpr_sgpr
|
||||
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX6: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX6: S_ENDPGM 0, implicit [[S_ADD_U32_]]
|
||||
; GFX8-LABEL: name: gep_p2_sgpr_sgpr
|
||||
; GFX8: $vcc_hi = IMPLICIT_DEF
|
||||
; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX8: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX8: S_ENDPGM 0, implicit [[S_ADD_U32_]]
|
||||
; GFX9-LABEL: name: gep_p2_sgpr_sgpr
|
||||
; GFX9: $vcc_hi = IMPLICIT_DEF
|
||||
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX9: S_ENDPGM 0, implicit [[S_ADD_U32_]]
|
||||
; GFX10-WAVE64-LABEL: name: gep_p2_sgpr_sgpr
|
||||
; GFX10-WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX10-WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX10-WAVE64: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX10-WAVE64: S_ENDPGM 0, implicit [[S_ADD_U32_]]
|
||||
; GFX10-WAVE32-LABEL: name: gep_p2_sgpr_sgpr
|
||||
; GFX10-WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; GFX10-WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX10-WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX10-WAVE32: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
|
||||
; GFX10-WAVE32: S_ENDPGM 0, implicit [[S_ADD_U32_]]
|
||||
%0:sgpr(p2) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:sgpr(p2) = G_GEP %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
|
||||
...
|
||||
|
||||
@ -90,3 +90,39 @@ body: |
|
||||
|
||||
$vgpr0 = COPY %2
|
||||
...
|
||||
|
||||
---
|
||||
name: test_gep_constant32_i32_idx
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
|
||||
; CHECK-LABEL: name: test_gep_constant32_i32_idx
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
|
||||
; CHECK: [[GEP:%[0-9]+]]:_(p6) = G_GEP [[COPY]], [[COPY1]](s32)
|
||||
; CHECK: $sgpr0 = COPY [[GEP]](p6)
|
||||
%0:_(p6) = COPY $sgpr0
|
||||
%1:_(s32) = COPY $sgpr1
|
||||
%2:_(p6) = G_GEP %0, %1
|
||||
|
||||
$sgpr0 = COPY %2
|
||||
...
|
||||
|
||||
---
|
||||
name: test_gep_region_i32_idx
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
; CHECK-LABEL: name: test_gep_region_i32_idx
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(p2) = COPY $vgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; CHECK: [[GEP:%[0-9]+]]:_(p2) = G_GEP [[COPY]], [[COPY1]](s32)
|
||||
; CHECK: $vgpr0 = COPY [[GEP]](p2)
|
||||
%0:_(p2) = COPY $vgpr0
|
||||
%1:_(s32) = COPY $vgpr1
|
||||
%2:_(p2) = G_GEP %0, %1
|
||||
|
||||
$vgpr0 = COPY %2
|
||||
...
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user