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[mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled.
Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 llvm-svn: 230235
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Daniel Sanders
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4d72fc7a63
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0eca0162a3
@ -398,6 +398,8 @@ def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128,
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(sequence "W%u", 0, 31)>;
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def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128,
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(sequence "W%u", 0, 31)>;
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def MSA128WEvens: RegisterClass<"Mips", [v4i32, v4f32], 128,
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(decimate (sequence "W%u", 0, 31), 2)>;
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def MSACtrl: RegisterClass<"Mips", [i32], 32, (add
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MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>;
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@ -2878,10 +2878,21 @@ emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
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unsigned Ws = MI->getOperand(1).getReg();
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unsigned Lane = MI->getOperand(2).getImm();
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if (Lane == 0)
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BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo);
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else {
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unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
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if (Lane == 0) {
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unsigned Wt = Ws;
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if (!Subtarget.useOddSPReg()) {
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// We must copy to an even-numbered MSA register so that the
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// single-precision sub-register is also guaranteed to be even-numbered.
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Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
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BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
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}
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BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
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} else {
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unsigned Wt = RegInfo.createVirtualRegister(
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Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
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&Mips::MSA128WEvensRegClass);
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BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
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BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
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@ -2941,7 +2952,9 @@ MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI,
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unsigned Wd_in = MI->getOperand(1).getReg();
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unsigned Lane = MI->getOperand(2).getImm();
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unsigned Fs = MI->getOperand(3).getReg();
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unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
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unsigned Wt = RegInfo.createVirtualRegister(
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Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
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&Mips::MSA128WEvensRegClass);
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BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
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.addImm(0)
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131
test/CodeGen/Mips/no-odd-spreg-msa.ll
Normal file
131
test/CodeGen/Mips/no-odd-spreg-msa.ll
Normal file
@ -0,0 +1,131 @@
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; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+fp64,+msa,-nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=ODDSPREG
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; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+fp64,+msa,+nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOODDSPREG
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@v4f32 = global <4 x float> zeroinitializer
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define void @msa_insert_0(float %a) {
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entry:
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; Force the float into an odd-numbered register using named registers and
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; load the vector.
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%b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a)
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%0 = load volatile <4 x float>* @v4f32
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; Clobber all except $f12/$w12 and $f13
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;
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; The intention is that if odd single precision registers are permitted, the
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; allocator will choose $f12/$w12 for the vector and $f13 for the float to
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; avoid the spill/reload.
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;
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; On the other hand, if odd single precision registers are not permitted, it
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; must copy $f13 to an even-numbered register before inserting into the
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; vector.
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call void asm sideeffect "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
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%1 = insertelement <4 x float> %0, float %b, i32 0
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store <4 x float> %1, <4 x float>* @v4f32
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ret void
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}
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; ALL-LABEL: msa_insert_0:
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; ALL: mov.s $f13, $f12
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; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(
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; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]])
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; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13
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; NOODDSPREG: insve.w $w[[W0]][0], $w[[F0]][0]
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; ODDSPREG: insve.w $w[[W0]][0], $w13[0]
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; ALL: # Clobber
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; ALL-NOT: sdc1
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; ALL-NOT: ldc1
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; ALL: st.w $w[[W0]], 0($[[R0]])
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define void @msa_insert_1(float %a) {
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entry:
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; Force the float into an odd-numbered register using named registers and
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; load the vector.
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%b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a)
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%0 = load volatile <4 x float>* @v4f32
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; Clobber all except $f12/$w12 and $f13
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;
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; The intention is that if odd single precision registers are permitted, the
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; allocator will choose $f12/$w12 for the vector and $f13 for the float to
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; avoid the spill/reload.
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;
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; On the other hand, if odd single precision registers are not permitted, it
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; must copy $f13 to an even-numbered register before inserting into the
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; vector.
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call void asm sideeffect "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
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%1 = insertelement <4 x float> %0, float %b, i32 1
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store <4 x float> %1, <4 x float>* @v4f32
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ret void
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}
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; ALL-LABEL: msa_insert_1:
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; ALL: mov.s $f13, $f12
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; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(
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; ALL: ld.w $w[[W0:[0-9]+]], 0($[[R0]])
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; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13
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; NOODDSPREG: insve.w $w[[W0]][1], $w[[F0]][0]
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; ODDSPREG: insve.w $w[[W0]][1], $w13[0]
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; ALL: # Clobber
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; ALL-NOT: sdc1
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; ALL-NOT: ldc1
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; ALL: st.w $w[[W0]], 0($[[R0]])
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define float @msa_extract_0() {
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entry:
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%0 = load volatile <4 x float>* @v4f32
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%1 = call <4 x float> asm sideeffect "move.v $0, $1", "={$w13},{$w12}" (<4 x float> %0)
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; Clobber all except $f12, and $f13
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;
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; The intention is that if odd single precision registers are permitted, the
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; allocator will choose $f13/$w13 for the vector since that saves on moves.
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;
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; On the other hand, if odd single precision registers are not permitted, it
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; must move it to $f12/$w12.
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call void asm sideeffect "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
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%2 = extractelement <4 x float> %1, i32 0
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ret float %2
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}
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; ALL-LABEL: msa_extract_0:
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; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(
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; ALL: ld.w $w12, 0($[[R0]])
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; ALL: move.v $w[[W0:13]], $w12
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; NOODDSPREG: move.v $w[[W0:12]], $w13
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; ALL: # Clobber
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; ALL-NOT: st.w
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; ALL-NOT: ld.w
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; ALL: mov.s $f0, $f[[W0]]
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define float @msa_extract_1() {
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entry:
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%0 = load volatile <4 x float>* @v4f32
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%1 = call <4 x float> asm sideeffect "move.v $0, $1", "={$w13},{$w12}" (<4 x float> %0)
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; Clobber all except $f13
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;
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; The intention is that if odd single precision registers are permitted, the
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; allocator will choose $f13/$w13 for the vector since that saves on moves.
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;
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; On the other hand, if odd single precision registers are not permitted, it
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; must be spilled.
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call void asm sideeffect "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f12},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
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%2 = extractelement <4 x float> %1, i32 1
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ret float %2
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}
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; ALL-LABEL: msa_extract_1:
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; ALL: lw $[[R0:[0-9]+]], %got(v4f32)(
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; ALL: ld.w $w12, 0($[[R0]])
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; ALL: splati.w $w[[W0:[0-9]+]], $w13[1]
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; NOODDSPREG: st.w $w[[W0]], 0($sp)
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; ODDSPREG-NOT: st.w
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; ODDSPREG-NOT: ld.w
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; ALL: # Clobber
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; ODDSPREG-NOT: st.w
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; ODDSPREG-NOT: ld.w
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; NOODDSPREG: ld.w $w0, 0($sp)
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; ODDSPREG: mov.s $f0, $f[[W0]]
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