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https://github.com/RPCS3/llvm-mirror.git
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Remove trailing spaces.
llvm-svn: 63540
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36c3f0b6d8
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0ecadc3e36
@ -851,7 +851,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FDIV(SDNode *N, SDValue &Lo,
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RTLIB::DIV_F64,
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RTLIB::DIV_F80,
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RTLIB::DIV_PPCF128),
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N->getValueType(0), Ops, 2, false,
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N->getValueType(0), Ops, 2, false,
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N->getDebugLoc());
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assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR &&
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"Call lowered wrongly!");
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@ -932,7 +932,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FMUL(SDNode *N, SDValue &Lo,
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RTLIB::MUL_F64,
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RTLIB::MUL_F80,
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RTLIB::MUL_PPCF128),
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N->getValueType(0), Ops, 2, false,
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N->getValueType(0), Ops, 2, false,
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N->getDebugLoc());
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assert(Call.getNode()->getOpcode() == ISD::BUILD_PAIR &&
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"Call lowered wrongly!");
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@ -1148,7 +1148,7 @@ void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
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Lo = DAG.getNode(ISD::FADD, dl, VT, Hi,
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DAG.getConstantFP(APFloat(APInt(128, 2, Parts)),
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MVT::ppcf128));
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Lo = DAG.getNode(ISD::SELECT_CC, dl, VT, Src, DAG.getConstant(0, SrcVT),
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Lo = DAG.getNode(ISD::SELECT_CC, dl, VT, Src, DAG.getConstant(0, SrcVT),
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Lo, Hi, DAG.getCondCode(ISD::SETLT));
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Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Lo, DAG.getIntPtrConstant(1));
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Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Lo, DAG.getIntPtrConstant(0));
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@ -1275,7 +1275,7 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) {
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SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) {
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MVT RVT = N->getValueType(0);
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DebugLoc dl = N->getDebugLoc();
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// Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
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// PPC (the libcall is not available). FIXME: Do this in a less hacky way.
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if (RVT == MVT::i32) {
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@ -1283,7 +1283,7 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) {
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"Logic only correct for ppcf128!");
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SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
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N->getOperand(0), DAG.getValueType(MVT::f64));
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Res = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Res,
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Res = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Res,
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DAG.getIntPtrConstant(1));
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return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res);
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}
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@ -137,7 +137,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
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SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
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SDValue Op2 = GetPromotedInteger(N->getOperand(2));
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SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
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SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
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N->getMemoryVT(),
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N->getChain(), N->getBasePtr(),
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Op2, N->getSrcValue(), N->getAlignment());
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@ -176,7 +176,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
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case PromoteInteger:
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if (NOutVT.bitsEq(NInVT))
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// The input promotes to the same size. Convert the promoted value.
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return DAG.getNode(ISD::BIT_CONVERT, dl,
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return DAG.getNode(ISD::BIT_CONVERT, dl,
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NOutVT, GetPromotedInteger(InOp));
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break;
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case SoftenFloat:
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@ -1047,7 +1047,7 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
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Lo = Hi = DAG.getConstant(0, NVT);
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} else if (Amt > NVTBits) {
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Lo = DAG.getConstant(0, NVT);
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Hi = DAG.getNode(ISD::SHL, dl,
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Hi = DAG.getNode(ISD::SHL, dl,
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NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
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} else if (Amt == NVTBits) {
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Lo = DAG.getConstant(0, NVT);
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@ -1077,7 +1077,7 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
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Lo = DAG.getConstant(0, NVT);
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Hi = DAG.getConstant(0, NVT);
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} else if (Amt > NVTBits) {
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Lo = DAG.getNode(ISD::SRL, dl,
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Lo = DAG.getNode(ISD::SRL, dl,
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NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
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Hi = DAG.getConstant(0, NVT);
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} else if (Amt == NVTBits) {
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@ -1550,7 +1550,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
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DAG.getConstant(ExcessBits,
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TLI.getPointerTy())));
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// Move high bits to the right position in Hi.
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Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
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Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
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NVT, Hi,
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DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
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TLI.getPointerTy()));
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@ -1986,7 +1986,7 @@ void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
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if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
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if (RHSCST->isAllOnesValue()) {
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// Equality comparison to -1.
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NewLHS = DAG.getNode(ISD::AND, dl,
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NewLHS = DAG.getNode(ISD::AND, dl,
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LHSLo.getValueType(), LHSLo, LHSHi);
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NewRHS = RHSLo;
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return;
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@ -2262,7 +2262,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
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// Check whether the sign bit is set.
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SDValue Lo, Hi;
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GetExpandedInteger(Op, Lo, Hi);
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SDValue SignSet = DAG.getSetCC(dl,
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SDValue SignSet = DAG.getSetCC(dl,
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TLI.getSetCCResultType(Hi.getValueType()),
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Hi, DAG.getConstant(0, Hi.getValueType()),
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ISD::SETLT);
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@ -187,7 +187,7 @@ void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDValue &Lo,
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unsigned IncrementSize = NVT.getSizeInBits() / 8;
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Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
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DAG.getIntPtrConstant(IncrementSize));
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Hi = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getSrcValue(),
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Hi = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getSrcValue(),
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SVOffset+IncrementSize,
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isVolatile, MinAlign(Alignment, IncrementSize));
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@ -306,7 +306,7 @@ SDValue DAGTypeLegalizer::ExpandOp_INSERT_VECTOR_ELT(SDNode *N) {
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// Bitconvert to a vector of twice the length with elements of the expanded
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// type, insert the expanded vector elements, and then convert back.
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MVT NewVecVT = MVT::getVectorVT(NewEVT, NumElts*2);
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SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl,
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SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl,
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NewVecVT, N->getOperand(0));
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SDValue Lo, Hi;
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@ -365,7 +365,7 @@ SDValue DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) {
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Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
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DAG.getIntPtrConstant(IncrementSize));
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assert(isTypeLegal(Ptr.getValueType()) && "Pointers must be legal!");
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Hi = DAG.getStore(Chain, dl, Hi, Ptr, St->getSrcValue(),
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Hi = DAG.getStore(Chain, dl, Hi, Ptr, St->getSrcValue(),
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SVOffset + IncrementSize,
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isVolatile, MinAlign(Alignment, IncrementSize));
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