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fix CodeGen/Generic/2008-01-25-dag-combine-mul.ll on sparc, PR2105
llvm-svn: 47706
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@ -7,6 +7,7 @@ To-do
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* We can fold small constant offsets into the %hi/%lo references to constant
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pool addresses as well.
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* When in V9 mode, register allocate %icc[0-3].
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* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
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* Emit the 'Branch on Integer Register with Prediction' instructions. It's
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not clear how to write a pattern for this though:
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@ -218,6 +218,9 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
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// FIXME: Sparc provides these multiplies, but we don't have them yet.
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setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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