mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-03-01 00:35:43 +00:00
[mips][microMIPS][DSP] Implement BALIGN, BITREV, BPOSGE32, CMP*, CMPGDU*, CMPGU* and CMPU* instructions
Differential Revision: http://reviews.llvm.org/D16182 llvm-svn: 269752
This commit is contained in:
Zlatko Buljan
parent
6435e10dbd
commit
0fef23e430
@ -249,5 +249,54 @@ class POOL32I_IMMB0_FMT<string opstr, bits<5> op> : MMDSPInst<opstr> {
|
||||
let Inst{31-26} = 0b010000;
|
||||
let Inst{25-21} = op;
|
||||
let Inst{20-16} = 0;
|
||||
let Inst{15-0} = offset;
|
||||
let Inst{15-0} = offset;
|
||||
}
|
||||
|
||||
class POOL32A_2RBP_FMT<string opstr> : MMDSPInst<opstr> {
|
||||
bits<5> rt;
|
||||
bits<5> rs;
|
||||
bits<2> bp;
|
||||
|
||||
let Inst{31-26} = 0;
|
||||
let Inst{25-21} = rt;
|
||||
let Inst{20-16} = rs;
|
||||
let Inst{15-14} = bp;
|
||||
let Inst{13-6} = 0b00100010;
|
||||
let Inst{5-0} = 0b111100;
|
||||
}
|
||||
|
||||
class POOL32A_2RB0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
|
||||
bits<5> rt;
|
||||
bits<5> rs;
|
||||
|
||||
let Inst{31-26} = 0;
|
||||
let Inst{25-21} = rt;
|
||||
let Inst{20-16} = rs;
|
||||
let Inst{15-10} = 0;
|
||||
let Inst{9-0} = op;
|
||||
}
|
||||
|
||||
class POOL32S_3RB0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
|
||||
bits<5> rt;
|
||||
bits<5> rs;
|
||||
bits<5> rd;
|
||||
|
||||
let Inst{31-26} = 0b010110;
|
||||
let Inst{25-21} = rt;
|
||||
let Inst{20-16} = rs;
|
||||
let Inst{15-11} = rd;
|
||||
let Inst{10} = 0b0;
|
||||
let Inst{9-0} = op;
|
||||
}
|
||||
|
||||
class POOL32A_2R2B0_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
|
||||
bits<5> rt;
|
||||
bits<5> rs;
|
||||
|
||||
let Inst{31-26} = 0;
|
||||
let Inst{25-21} = rt;
|
||||
let Inst{20-16} = rs;
|
||||
let Inst{15-11} = 0;
|
||||
let Inst{10} = 0;
|
||||
let Inst{9-0} = op;
|
||||
}
|
||||
|
||||
@ -160,6 +160,21 @@ class MODSUB_MM_ENC : POOL32A_3RB0_FMT<"modsub", 0b1010010101>;
|
||||
class MULSA_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"mulsa.w.ph", 0b10110010>;
|
||||
class MULSAQ_S_W_PH_MM_ENC : POOL32A_2RAC_FMT<"mulsaq_s.w.ph", 0b11110010>;
|
||||
class BPOSGE32C_MMR3_ENC : POOL32I_IMMB0_FMT<"bposge32c", 0b11001>;
|
||||
class BITREV_MM_ENC : POOL32A_2R_FMT<"bitrev", 0b0011000100>;
|
||||
class BALIGN_MMR2_ENC : POOL32A_2RBP_FMT<"balign">;
|
||||
class BPOSGE32_MM_ENC : POOL32I_IMMB0_FMT<"bposge32", 0b11011>;
|
||||
class CMP_EQ_PH_MM_ENC : POOL32A_2RB0_FMT<"cmp.eq.ph", 0b0000000101>;
|
||||
class CMP_LE_PH_MM_ENC : POOL32A_2RB0_FMT<"cmp.le.ph", 0b0010000101>;
|
||||
class CMP_LT_PH_MM_ENC : POOL32A_2RB0_FMT<"cmp.lt.ph", 0b0001000101>;
|
||||
class CMPGDU_EQ_QB_MMR2_ENC : POOL32A_3RB0_FMT<"cmpgdu.eq.qb", 0b0110000101>;
|
||||
class CMPGDU_LT_QB_MMR2_ENC : POOL32A_3RB0_FMT<"cmpgdu.lt.qb", 0b0111000101>;
|
||||
class CMPGDU_LE_QB_MMR2_ENC : POOL32A_3RB0_FMT<"cmpgdu.le.qb", 0b1000000101>;
|
||||
class CMPGU_EQ_QB_MM_ENC : POOL32S_3RB0_FMT<"cmpgu.eq.qb", 0b0011000101>;
|
||||
class CMPGU_LT_QB_MM_ENC : POOL32S_3RB0_FMT<"cmpgu.lt.qb", 0b0100000101>;
|
||||
class CMPGU_LE_QB_MM_ENC : POOL32S_3RB0_FMT<"cmpgu.le.qb", 0b0101000101>;
|
||||
class CMPU_EQ_QB_MM_ENC : POOL32A_2R2B0_FMT<"cmpu.eq.qb", 0b1001000101>;
|
||||
class CMPU_LT_QB_MM_ENC : POOL32A_2R2B0_FMT<"cmpu.lt.qb", 0b1010000101>;
|
||||
class CMPU_LE_QB_MM_ENC : POOL32A_2R2B0_FMT<"cmpu.le.qb", 0b1011000101>;
|
||||
|
||||
// Instruction desc.
|
||||
class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
|
||||
@ -383,6 +398,23 @@ class BPOSGE32C_MMR3_DESC {
|
||||
bit hasDelaySlot = 0;
|
||||
}
|
||||
|
||||
class BALIGN_MMR2_DESC {
|
||||
dag OutOperandList = (outs GPR32Opnd:$rt);
|
||||
dag InOperandList = (ins GPR32Opnd:$rs, uimm2:$bp, GPR32Opnd:$src);
|
||||
string AsmString = !strconcat("balign", "\t$rt, $rs, $bp");
|
||||
list<dag> Pattern = [(set GPR32Opnd:$rt, (int_mips_balign GPR32Opnd:$src,
|
||||
GPR32Opnd:$rs,
|
||||
immZExt2:$bp))];
|
||||
InstrItinClass Itinerary = NoItinerary;
|
||||
string Constraints = "$src = $rt";
|
||||
}
|
||||
|
||||
class BITREV_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<"bitrev", int_mips_bitrev,
|
||||
NoItinerary, GPR32Opnd>;
|
||||
|
||||
class BPOSGE32_MM_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget_mm,
|
||||
NoItinerary>;
|
||||
|
||||
// Instruction defs.
|
||||
// microMIPS DSP Rev 1
|
||||
def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC;
|
||||
@ -489,6 +521,18 @@ def SHILOV_MM : DspMMRel, SHILOV_MM_ENC, SHILOV_DESC;
|
||||
def WRDSP_MM : DspMMRel, WRDSP_MM_ENC, WRDSP_MM_DESC;
|
||||
def MODSUB_MM : DspMMRel, MODSUB_MM_ENC, MODSUB_DESC;
|
||||
def MULSAQ_S_W_PH_MM : DspMMRel, MULSAQ_S_W_PH_MM_ENC, MULSAQ_S_W_PH_DESC;
|
||||
def BITREV_MM : DspMMRel, BITREV_MM_ENC, BITREV_MM_DESC;
|
||||
def BPOSGE32_MM : DspMMRel, BPOSGE32_MM_ENC, BPOSGE32_MM_DESC,
|
||||
ISA_MIPS1_NOT_32R6_64R6;
|
||||
def CMP_EQ_PH_MM : DspMMRel, CMP_EQ_PH_MM_ENC, CMP_EQ_PH_DESC;
|
||||
def CMP_LT_PH_MM : DspMMRel, CMP_LT_PH_MM_ENC, CMP_LT_PH_DESC;
|
||||
def CMP_LE_PH_MM : DspMMRel, CMP_LE_PH_MM_ENC, CMP_LE_PH_DESC;
|
||||
def CMPGU_EQ_QB_MM : DspMMRel, CMPGU_EQ_QB_MM_ENC, CMPGU_EQ_QB_DESC;
|
||||
def CMPGU_LT_QB_MM : DspMMRel, CMPGU_LT_QB_MM_ENC, CMPGU_LT_QB_DESC;
|
||||
def CMPGU_LE_QB_MM : DspMMRel, CMPGU_LE_QB_MM_ENC, CMPGU_LE_QB_DESC;
|
||||
def CMPU_EQ_QB_MM : DspMMRel, CMPU_EQ_QB_MM_ENC, CMPU_EQ_QB_DESC;
|
||||
def CMPU_LT_QB_MM : DspMMRel, CMPU_LT_QB_MM_ENC, CMPU_LT_QB_DESC;
|
||||
def CMPU_LE_QB_MM : DspMMRel, CMPU_LE_QB_MM_ENC, CMPU_LE_QB_DESC;
|
||||
// microMIPS DSP Rev 2
|
||||
def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
|
||||
ISA_DSPR2;
|
||||
@ -512,6 +556,13 @@ def SHRA_R_QB_MMR2 : DspMMRel, SHRA_R_QB_MMR2_ENC, SHRA_R_QB_MMR2_DESC,
|
||||
def SHRAV_QB_MMR2 : DspMMRel, SHRAV_QB_MMR2_ENC, SHRAV_QB_MMR2_DESC, ISA_DSPR2;
|
||||
def SHRAV_R_QB_MMR2 : DspMMRel, SHRAV_R_QB_MMR2_ENC, SHRAV_R_QB_MMR2_DESC,
|
||||
ISA_DSPR2;
|
||||
def BALIGN_MMR2 : DspMMRel, BALIGN_MMR2_ENC, BALIGN_MMR2_DESC, ISA_DSPR2;
|
||||
def CMPGDU_EQ_QB_MMR2 : DspMMRel, CMPGDU_EQ_QB_MMR2_ENC, CMPGDU_EQ_QB_DESC,
|
||||
ISA_DSPR2;
|
||||
def CMPGDU_LT_QB_MMR2 : DspMMRel, CMPGDU_LT_QB_MMR2_ENC, CMPGDU_LT_QB_DESC,
|
||||
ISA_DSPR2;
|
||||
def CMPGDU_LE_QB_MMR2 : DspMMRel, CMPGDU_LE_QB_MMR2_ENC, CMPGDU_LE_QB_DESC,
|
||||
ISA_DSPR2;
|
||||
def SHRL_PH_MMR2 : DspMMRel, SHRL_PH_MMR2_ENC, SHRL_PH_MMR2_DESC, ISA_DSPR2;
|
||||
def SHRLV_PH_MMR2 : DspMMRel, SHRLV_PH_MMR2_ENC, SHRLV_PH_MMR2_DESC, ISA_DSPR2;
|
||||
def SUBQH_PH_MMR2 : DspMMRel, SUBQH_PH_MMR2_ENC, SUBQH_PH_DESC, ISA_DSPR2;
|
||||
|
||||
@ -286,6 +286,7 @@ class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
|
||||
list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
|
||||
InstrItinClass Itinerary = itin;
|
||||
string BaseOpcode = instr_asm;
|
||||
}
|
||||
|
||||
class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
@ -513,14 +514,16 @@ class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
|
||||
bit usesCustomInserter = 1;
|
||||
}
|
||||
|
||||
class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
|
||||
class BPOSGE32_DESC_BASE<string instr_asm, DAGOperand opnd,
|
||||
InstrItinClass itin> {
|
||||
dag OutOperandList = (outs);
|
||||
dag InOperandList = (ins brtarget:$offset);
|
||||
dag InOperandList = (ins opnd:$offset);
|
||||
string AsmString = !strconcat(instr_asm, "\t$offset");
|
||||
InstrItinClass Itinerary = itin;
|
||||
bit isBranch = 1;
|
||||
bit isTerminator = 1;
|
||||
bit hasDelaySlot = 1;
|
||||
string BaseOpcode = instr_asm;
|
||||
}
|
||||
|
||||
class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
|
||||
@ -871,7 +874,7 @@ class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>;
|
||||
|
||||
class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>;
|
||||
|
||||
class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
|
||||
class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget, NoItinerary>;
|
||||
|
||||
// Extr
|
||||
class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>,
|
||||
@ -1177,16 +1180,16 @@ def MADD_DSP : DspMMRel, MADD_DSP_ENC, MADD_DSP_DESC;
|
||||
def MADDU_DSP : DspMMRel, MADDU_DSP_ENC, MADDU_DSP_DESC;
|
||||
def MSUB_DSP : DspMMRel, MSUB_DSP_ENC, MSUB_DSP_DESC;
|
||||
def MSUBU_DSP : DspMMRel, MSUBU_DSP_ENC, MSUBU_DSP_DESC;
|
||||
def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
|
||||
def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
|
||||
def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
|
||||
def CMPGU_EQ_QB : CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
|
||||
def CMPGU_LT_QB : CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
|
||||
def CMPGU_LE_QB : CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
|
||||
def CMP_EQ_PH : CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
|
||||
def CMP_LT_PH : CMP_LT_PH_ENC, CMP_LT_PH_DESC;
|
||||
def CMP_LE_PH : CMP_LE_PH_ENC, CMP_LE_PH_DESC;
|
||||
def BITREV : BITREV_ENC, BITREV_DESC;
|
||||
def CMPU_EQ_QB : DspMMRel, CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
|
||||
def CMPU_LT_QB : DspMMRel, CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
|
||||
def CMPU_LE_QB : DspMMRel, CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
|
||||
def CMPGU_EQ_QB : DspMMRel, CMPGU_EQ_QB_ENC, CMPGU_EQ_QB_DESC;
|
||||
def CMPGU_LT_QB : DspMMRel, CMPGU_LT_QB_ENC, CMPGU_LT_QB_DESC;
|
||||
def CMPGU_LE_QB : DspMMRel, CMPGU_LE_QB_ENC, CMPGU_LE_QB_DESC;
|
||||
def CMP_EQ_PH : DspMMRel, CMP_EQ_PH_ENC, CMP_EQ_PH_DESC;
|
||||
def CMP_LT_PH : DspMMRel, CMP_LT_PH_ENC, CMP_LT_PH_DESC;
|
||||
def CMP_LE_PH : DspMMRel, CMP_LE_PH_ENC, CMP_LE_PH_DESC;
|
||||
def BITREV : DspMMRel, BITREV_ENC, BITREV_DESC;
|
||||
def PACKRL_PH : DspMMRel, PACKRL_PH_ENC, PACKRL_PH_DESC;
|
||||
def REPL_QB : DspMMRel, REPL_QB_ENC, REPL_QB_DESC;
|
||||
def REPL_PH : DspMMRel, REPL_PH_ENC, REPL_PH_DESC;
|
||||
@ -1197,7 +1200,9 @@ def PICK_PH : DspMMRel, PICK_PH_ENC, PICK_PH_DESC;
|
||||
def LWX : DspMMRel, LWX_ENC, LWX_DESC;
|
||||
def LHX : DspMMRel, LHX_ENC, LHX_DESC;
|
||||
def LBUX : DspMMRel, LBUX_ENC, LBUX_DESC;
|
||||
def BPOSGE32 : DspMMRel, BPOSGE32_ENC, BPOSGE32_DESC;
|
||||
let AdditionalPredicates = [NotInMicroMips] in {
|
||||
def BPOSGE32 : DspMMRel, BPOSGE32_ENC, BPOSGE32_DESC;
|
||||
}
|
||||
def INSV : DspMMRel, INSV_ENC, INSV_DESC;
|
||||
def EXTP : DspMMRel, EXTP_ENC, EXTP_DESC;
|
||||
def EXTPV : DspMMRel, EXTPV_ENC, EXTPV_DESC;
|
||||
@ -1224,9 +1229,9 @@ def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC, ISA_DSPR2;
|
||||
def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC, ISA_DSPR2;
|
||||
def SUBU_PH : DspMMRel, SUBU_PH_ENC, SUBU_PH_DESC, ISA_DSPR2;
|
||||
def SUBU_S_PH : DspMMRel, SUBU_S_PH_ENC, SUBU_S_PH_DESC, ISA_DSPR2;
|
||||
def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC, ISA_DSPR2;
|
||||
def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC, ISA_DSPR2;
|
||||
def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC, ISA_DSPR2;
|
||||
def CMPGDU_EQ_QB : DspMMRel, CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC, ISA_DSPR2;
|
||||
def CMPGDU_LT_QB : DspMMRel, CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC, ISA_DSPR2;
|
||||
def CMPGDU_LE_QB : DspMMRel, CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC, ISA_DSPR2;
|
||||
def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC, ISA_DSPR2;
|
||||
def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC, ISA_DSPR2;
|
||||
def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC, ISA_DSPR2;
|
||||
@ -1264,7 +1269,7 @@ def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC, ISA_DSPR2;
|
||||
def SHRL_PH : DspMMRel, SHRL_PH_ENC, SHRL_PH_DESC, ISA_DSPR2;
|
||||
def SHRLV_PH : DspMMRel, SHRLV_PH_ENC, SHRLV_PH_DESC, ISA_DSPR2;
|
||||
def APPEND : DspMMRel, APPEND_ENC, APPEND_DESC, ISA_DSPR2;
|
||||
def BALIGN : BALIGN_ENC, BALIGN_DESC, ISA_DSPR2;
|
||||
def BALIGN : DspMMRel, BALIGN_ENC, BALIGN_DESC, ISA_DSPR2;
|
||||
def PREPEND : DspMMRel, PREPEND_ENC, PREPEND_DESC, ISA_DSPR2;
|
||||
|
||||
// Pseudos.
|
||||
|
||||
@ -0,0 +1,3 @@
|
||||
# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r3 -mattr=micromips -mattr=+dsp | FileCheck %s
|
||||
|
||||
0x43 0x60 0x00 0xab # CHECK: bposge32 342
|
||||
@ -103,3 +103,13 @@
|
||||
0x00 0xa0 0x96 0x7c # CHECK: wrdsp $5, 2
|
||||
0x00 0xc5 0x22 0x95 # CHECK: modsub $4, $5, $6
|
||||
0x00 0x43 0x3c 0xbc # CHECK: mulsaq_s.w.ph $ac0, $3, $2
|
||||
0x00 0x43 0x31 0x3c # CHECK: bitrev $2, $3
|
||||
0x00 0x62 0x00 0x05 # CHECK: cmp.eq.ph $2, $3
|
||||
0x00 0x62 0x00 0x85 # CHECK: cmp.le.ph $2, $3
|
||||
0x00 0x62 0x00 0x45 # CHECK: cmp.lt.ph $2, $3
|
||||
0x58 0x62 0x08 0xc5 # CHECK: cmpgu.eq.qb $1, $2, $3
|
||||
0x58 0x62 0x09 0x05 # CHECK: cmpgu.lt.qb $1, $2, $3
|
||||
0x58 0x62 0x09 0x45 # CHECK: cmpgu.le.qb $1, $2, $3
|
||||
0x00 0x41 0x02 0x45 # CHECK: cmpu.eq.qb $1, $2
|
||||
0x00 0x41 0x02 0x85 # CHECK: cmpu.lt.qb $1, $2
|
||||
0x00 0x41 0x02 0xc5 # CHECK: cmpu.le.qb $1, $2
|
||||
|
||||
@ -125,3 +125,17 @@
|
||||
0x00 0xa0 0x96 0x7c # CHECK: wrdsp $5, 2
|
||||
0x00 0x64 0x2a 0x15 # CHECK: append $3, $4, 5
|
||||
0x00 0x43 0x2c 0xbc # CHECK: mulsa.w.ph $ac0, $3, $2
|
||||
0x00 0x43 0xc8 0xbc # CHECK: balign $2, $3, 3
|
||||
0x00 0x43 0x31 0x3c # CHECK: bitrev $2, $3
|
||||
0x00 0x62 0x00 0x05 # CHECK: cmp.eq.ph $2, $3
|
||||
0x00 0x62 0x00 0x85 # CHECK: cmp.le.ph $2, $3
|
||||
0x00 0x62 0x00 0x45 # CHECK: cmp.lt.ph $2, $3
|
||||
0x00 0x62 0x09 0x85 # CHECK: cmpgdu.eq.qb $1, $2, $3
|
||||
0x00 0x62 0x09 0xc5 # CHECK: cmpgdu.lt.qb $1, $2, $3
|
||||
0x00 0x62 0x0a 0x05 # CHECK: cmpgdu.le.qb $1, $2, $3
|
||||
0x58 0x62 0x08 0xc5 # CHECK: cmpgu.eq.qb $1, $2, $3
|
||||
0x58 0x62 0x09 0x05 # CHECK: cmpgu.lt.qb $1, $2, $3
|
||||
0x58 0x62 0x09 0x45 # CHECK: cmpgu.le.qb $1, $2, $3
|
||||
0x00 0x41 0x02 0x45 # CHECK: cmpu.eq.qb $1, $2
|
||||
0x00 0x41 0x02 0x85 # CHECK: cmpu.lt.qb $1, $2
|
||||
0x00 0x41 0x02 0xc5 # CHECK: cmpu.le.qb $1, $2
|
||||
|
||||
@ -21,3 +21,5 @@
|
||||
shrl.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
|
||||
shilo $ac1, 64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate
|
||||
shilo $ac1, -64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate
|
||||
# bposge32 is microMIPS DSP instruction but it is removed in Release 6
|
||||
bposge32 342 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
|
||||
4
test/MC/Mips/micromips-dsp/valid-micromips32r3.s
Normal file
4
test/MC/Mips/micromips-dsp/valid-micromips32r3.s
Normal file
@ -0,0 +1,4 @@
|
||||
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r3 -mattr=micromips -mattr=+dsp | FileCheck %s
|
||||
|
||||
.set noat
|
||||
bposge32 342 # CHECK: bposge32 342 # encoding: [0x43,0x60,0x00,0xab]
|
||||
@ -105,3 +105,13 @@
|
||||
wrdsp $5, 31 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c]
|
||||
modsub $4, $5, $6 # CHECK: modsub $4, $5, $6 # encoding: [0x00,0xc5,0x22,0x95]
|
||||
mulsaq_s.w.ph $ac0, $3, $2 # CHECK: mulsaq_s.w.ph $ac0, $3, $2 # encoding: [0x00,0x43,0x3c,0xbc]
|
||||
bitrev $2, $3 # CHECK: bitrev $2, $3 # encoding: [0x00,0x43,0x31,0x3c]
|
||||
cmp.eq.ph $2, $3 # CHECK: cmp.eq.ph $2, $3 # encoding: [0x00,0x62,0x00,0x05]
|
||||
cmp.le.ph $2, $3 # CHECK: cmp.le.ph $2, $3 # encoding: [0x00,0x62,0x00,0x85]
|
||||
cmp.lt.ph $2, $3 # CHECK: cmp.lt.ph $2, $3 # encoding: [0x00,0x62,0x00,0x45]
|
||||
cmpgu.eq.qb $1, $2, $3 # CHECK: cmpgu.eq.qb $1, $2, $3 # encoding: [0x58,0x62,0x08,0xc5]
|
||||
cmpgu.lt.qb $1, $2, $3 # CHECK: cmpgu.lt.qb $1, $2, $3 # encoding: [0x58,0x62,0x09,0x05]
|
||||
cmpgu.le.qb $1, $2, $3 # CHECK: cmpgu.le.qb $1, $2, $3 # encoding: [0x58,0x62,0x09,0x45]
|
||||
cmpu.eq.qb $1, $2 # CHECK: cmpu.eq.qb $1, $2 # encoding: [0x00,0x41,0x02,0x45]
|
||||
cmpu.lt.qb $1, $2 # CHECK: cmpu.lt.qb $1, $2 # encoding: [0x00,0x41,0x02,0x85]
|
||||
cmpu.le.qb $1, $2 # CHECK: cmpu.le.qb $1, $2 # encoding: [0x00,0x41,0x02,0xc5]
|
||||
|
||||
@ -1,6 +1,8 @@
|
||||
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 2>%t1
|
||||
# RUN: FileCheck %s < %t1
|
||||
|
||||
balign $2, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate
|
||||
balign $2, $3, 4 # CHECK: :[[@LINE]]:18: error: expected 2-bit unsigned immediate
|
||||
shra.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
|
||||
shra.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
|
||||
shra_r.qb $3, $4, 8 # CHECK: :[[@LINE]]:21: error: expected 3-bit unsigned immediate
|
||||
@ -13,3 +15,5 @@
|
||||
mulsa.w.ph $31, $3, $2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
|
||||
mulsaq_s.w.ph $8, $3, $2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
|
||||
mulsaq_s.w.ph $31, $3, $2 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
|
||||
# bposge32 is microMIPS DSP instruction but it is removed in Release 6
|
||||
bposge32 342 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
|
||||
@ -127,3 +127,17 @@
|
||||
wrdsp $5, 31 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c]
|
||||
append $3, $4, 5 # CHECK: append $3, $4, 5 # encoding: [0x00,0x64,0x2a,0x15]
|
||||
mulsa.w.ph $ac0, $3, $2 # CHECK: mulsa.w.ph $ac0, $3, $2 # encoding: [0x00,0x43,0x2c,0xbc]
|
||||
balign $2, $3, 3 # CHECK: balign $2, $3, 3 # encoding: [0x00,0x43,0xc8,0xbc]
|
||||
bitrev $2, $3 # CHECK: bitrev $2, $3 # encoding: [0x00,0x43,0x31,0x3c]
|
||||
cmp.eq.ph $2, $3 # CHECK: cmp.eq.ph $2, $3 # encoding: [0x00,0x62,0x00,0x05]
|
||||
cmp.le.ph $2, $3 # CHECK: cmp.le.ph $2, $3 # encoding: [0x00,0x62,0x00,0x85]
|
||||
cmp.lt.ph $2, $3 # CHECK: cmp.lt.ph $2, $3 # encoding: [0x00,0x62,0x00,0x45]
|
||||
cmpgdu.eq.qb $1, $2, $3 # CHECK: cmpgdu.eq.qb $1, $2, $3 # encoding: [0x00,0x62,0x09,0x85]
|
||||
cmpgdu.lt.qb $1, $2, $3 # CHECK: cmpgdu.lt.qb $1, $2, $3 # encoding: [0x00,0x62,0x09,0xc5]
|
||||
cmpgdu.le.qb $1, $2, $3 # CHECK: cmpgdu.le.qb $1, $2, $3 # encoding: [0x00,0x62,0x0a,0x05]
|
||||
cmpgu.eq.qb $1, $2, $3 # CHECK: cmpgu.eq.qb $1, $2, $3 # encoding: [0x58,0x62,0x08,0xc5]
|
||||
cmpgu.lt.qb $1, $2, $3 # CHECK: cmpgu.lt.qb $1, $2, $3 # encoding: [0x58,0x62,0x09,0x05]
|
||||
cmpgu.le.qb $1, $2, $3 # CHECK: cmpgu.le.qb $1, $2, $3 # encoding: [0x58,0x62,0x09,0x45]
|
||||
cmpu.eq.qb $1, $2 # CHECK: cmpu.eq.qb $1, $2 # encoding: [0x00,0x41,0x02,0x45]
|
||||
cmpu.lt.qb $1, $2 # CHECK: cmpu.lt.qb $1, $2 # encoding: [0x00,0x41,0x02,0x85]
|
||||
cmpu.le.qb $1, $2 # CHECK: cmpu.le.qb $1, $2 # encoding: [0x00,0x41,0x02,0xc5]
|
||||
|
||||
@ -196,3 +196,5 @@
|
||||
swp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
swp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
|
||||
swp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
|
||||
# bposge32 is microMIPS DSP instruction
|
||||
bposge32 342 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
|
||||
@ -236,3 +236,5 @@
|
||||
dsra $4, $5, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
|
||||
dsra32 $4, $5, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
|
||||
dsra32 $4, $5, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
|
||||
# bposge32 is microMIPS DSP instruction
|
||||
bposge32 342 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user