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ARM64: fix assertion in ISelDAGToDAG

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Also an unused variable, so double bonus!

This should deal with PR19548.

llvm-svn: 207221
This commit is contained in:
Tim Northover 2014-04-25 10:48:47 +00:00
parent 51d6f272a3
commit 1017923163
2 changed files with 17 additions and 2 deletions
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2
lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
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@ -1403,8 +1403,6 @@ static bool isBitfieldDstMask(uint64_t DstMask, APInt BitsToBeInserted,
assert((VT == MVT::i32 || VT == MVT::i64) &&
"i32 or i64 mask type expected!");
unsigned BitWidth = VT.getSizeInBits() - NumberOfIgnoredHighBits;
APInt SignificantBits =
~APInt::getHighBitsSet(BitWidth, NumberOfIgnoredHighBits);
APInt SignificantDstMask = APInt(BitWidth, DstMask);
APInt SignificantBitsToBeInserted = BitsToBeInserted.zextOrTrunc(BitWidth);

17
test/CodeGen/ARM64/bitfield-extract.ll
View File

@ -500,3 +500,20 @@ end:
%conv3 = phi i80 [%conv, %entry], [%conv2, %then]
ret i80 %conv3
}
define i16 @test_ignored_rightbits(i32 %dst, i32 %in) {
; CHECK-LABEL: test_ignored_rightbits:
%positioned_field = shl i32 %in, 3
%positioned_masked_field = and i32 %positioned_field, 120
%masked_dst = and i32 %dst, 7
%insertion = or i32 %masked_dst, %positioned_masked_field
; CHECK: {{bfm|bfi}}
%shl16 = shl i32 %insertion, 8
%or18 = or i32 %shl16, %insertion
%conv19 = trunc i32 %or18 to i16
; CHECK: {{bfm w[0-9]+, w[0-9]+, #24, #6|bfi w[0-9]+, w[0-9]+, #8, #7}}
ret i16 %conv19
}