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[X86][MC][Target] Initial backend support a tune CPU to support -mtune

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This patch implements initial backend support for a -mtune CPU controlled by a "tune-cpu" function attribute. If the attribute is not present X86 will use the resolved CPU from target-cpu attribute or command line.

This patch adds MC layer support a tune CPU. Each CPU now has two sets of features stored in their GenSubtargetInfo.inc tables . These features lists are passed separately to the Processor and ProcessorModel classes in tablegen. The tune list defaults to an empty list to avoid changes to non-X86. This annoyingly increases the size of static tables on all target as we now store 24 more bytes per CPU. I haven't quantified the overall impact, but I can if we're concerned.

One new test is added to X86 to show a few tuning features with mismatched tune-cpu and target-cpu/target-feature attributes to demonstrate independent control. Another new test is added to demonstrate that the scheduler model follows the tune CPU.

I have not added a -mtune to llc/opt or MC layer command line yet. With no attributes we'll just use the -mcpu for both. MC layer tools will always follow the normal CPU for tuning.

Differential Revision: https://reviews.llvm.org/D85165
This commit is contained in:
Craig Topper 2020-08-14 14:56:54 -07:00
parent e6a595a264
commit 10839866a1
62 changed files with 211 additions and 158 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
include/llvm/CodeGen/TargetSubtargetInfo.h
View File

@ -58,8 +58,8 @@ class Triple;
///
class TargetSubtargetInfo : public MCSubtargetInfo {
protected: // Can only create subclasses...
TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
ArrayRef<SubtargetFeatureKV> PF,
TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU,
StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
ArrayRef<SubtargetSubTypeKV> PD,
const MCWriteProcResEntry *WPR,
const MCWriteLatencyEntry *WL,

15
include/llvm/MC/MCSubtargetInfo.h
View File

@ -54,6 +54,7 @@ struct SubtargetFeatureKV {
struct SubtargetSubTypeKV {
const char *Key; ///< K-V key string
FeatureBitArray Implies; ///< K-V bit mask
FeatureBitArray TuneImplies; ///< K-V bit mask
const MCSchedModel *SchedModel;
/// Compare routine for std::lower_bound
@ -74,6 +75,7 @@ struct SubtargetSubTypeKV {
class MCSubtargetInfo {
Triple TargetTriple;
std::string CPU; // CPU being targeted.
std::string TuneCPU; // CPU being tuned for.
ArrayRef<SubtargetFeatureKV> ProcFeatures; // Processor feature list
ArrayRef<SubtargetSubTypeKV> ProcDesc; // Processor descriptions
@ -90,8 +92,8 @@ class MCSubtargetInfo {
public:
MCSubtargetInfo(const MCSubtargetInfo &) = default;
MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
ArrayRef<SubtargetFeatureKV> PF,
MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU,
StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
ArrayRef<SubtargetSubTypeKV> PD,
const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA, const InstrStage *IS,
@ -103,6 +105,7 @@ public:
const Triple &getTargetTriple() const { return TargetTriple; }
StringRef getCPU() const { return CPU; }
StringRef getTuneCPU() const { return TuneCPU; }
const FeatureBitset& getFeatureBits() const { return FeatureBits; }
void setFeatureBits(const FeatureBitset &FeatureBits_) {
@ -118,12 +121,12 @@ protected:
///
/// FIXME: Find a way to stick this in the constructor, since it should only
/// be called during initialization.
void InitMCProcessorInfo(StringRef CPU, StringRef FS);
void InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU, StringRef FS);
public:
/// Set the features to the default for the given CPU with an appended feature
/// string.
void setDefaultFeatures(StringRef CPU, StringRef FS);
/// Set the features to the default for the given CPU and TuneCPU, with ano
/// appended feature string.
void setDefaultFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
/// Toggle a feature and return the re-computed feature bits.
/// This version does not change the implied bits.

14
include/llvm/Target/Target.td
View File

@ -1558,7 +1558,8 @@ class ComplexDeprecationPredicate<string dep> {
// by the scheduler. Each Processor definition requires corresponding
// instruction itineraries.
//
class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f,
list<SubtargetFeature> tunef = []> {
// Name - Chip set name. Used by command line (-mcpu=) to determine the
// appropriate target chip.
//
@ -1574,6 +1575,12 @@ class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
// Features - list of
list<SubtargetFeature> Features = f;
// TuneFeatures - list of features for tuning for this CPU. If the target
// supports -mtune, this should contain the list of features used to make
// microarchitectural optimization decisions for a given processor. While
// Features should contain the architectural features for the processor.
list<SubtargetFeature> TuneFeatures = tunef;
}
// ProcessorModel allows subtargets to specify the more general
@ -1582,8 +1589,9 @@ class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
//
// Although this class always passes NoItineraries to the Processor
// class, the SchedMachineModel may still define valid Itineraries.
class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f>
: Processor<n, NoItineraries, f> {
class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f,
list<SubtargetFeature> tunef = []>
: Processor<n, NoItineraries, f, tunef> {
let SchedModel = m;
}

11
lib/CodeGen/TargetSubtargetInfo.cpp
View File

@ -15,13 +15,12 @@
using namespace llvm;
TargetSubtargetInfo::TargetSubtargetInfo(
const Triple &TT, StringRef CPU, StringRef FS,
const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetSubTypeKV> PD,
const MCWriteProcResEntry *WPR,
const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
const InstrStage *IS, const unsigned *OC, const unsigned *FP)
: MCSubtargetInfo(TT, CPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {
}
const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC,
const unsigned *FP)
: MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {}
TargetSubtargetInfo::~TargetSubtargetInfo() = default;

42
lib/MC/MCSubtargetInfo.cpp
View File

@ -147,7 +147,7 @@ static void cpuHelp(ArrayRef<SubtargetSubTypeKV> CPUTable) {
PrintOnce = true;
}
static FeatureBitset getFeatures(StringRef CPU, StringRef FS,
static FeatureBitset getFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS,
ArrayRef<SubtargetSubTypeKV> ProcDesc,
ArrayRef<SubtargetFeatureKV> ProcFeatures) {
SubtargetFeatures Features(FS);
@ -178,6 +178,19 @@ static FeatureBitset getFeatures(StringRef CPU, StringRef FS,
}
}
if (!TuneCPU.empty()) {
const SubtargetSubTypeKV *CPUEntry = Find(TuneCPU, ProcDesc);
// If there is a match
if (CPUEntry) {
// Set the features implied by this CPU feature, if any.
SetImpliedBits(Bits, CPUEntry->TuneImplies.getAsBitset(), ProcFeatures);
} else if (TuneCPU != CPU) {
errs() << "'" << TuneCPU << "' is not a recognized processor for this "
<< "target (ignoring processor)\n";
}
}
// Iterate through each feature
for (const std::string &Feature : Features.getFeatures()) {
// Check for help
@ -192,30 +205,33 @@ static FeatureBitset getFeatures(StringRef CPU, StringRef FS,
return Bits;
}
void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
if (!CPU.empty())
CPUSchedModel = &getSchedModelForCPU(CPU);
void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU,
StringRef FS) {
FeatureBits = getFeatures(CPU, TuneCPU, FS, ProcDesc, ProcFeatures);
if (!TuneCPU.empty())
CPUSchedModel = &getSchedModelForCPU(TuneCPU);
else
CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
}
void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef FS) {
FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef TuneCPU,
StringRef FS) {
FeatureBits = getFeatures(CPU, TuneCPU, FS, ProcDesc, ProcFeatures);
}
MCSubtargetInfo::MCSubtargetInfo(const Triple &TT, StringRef C, StringRef FS,
ArrayRef<SubtargetFeatureKV> PF,
MCSubtargetInfo::MCSubtargetInfo(const Triple &TT, StringRef C, StringRef TC,
StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
ArrayRef<SubtargetSubTypeKV> PD,
const MCWriteProcResEntry *WPR,
const MCWriteLatencyEntry *WL,
const MCReadAdvanceEntry *RA,
const InstrStage *IS, const unsigned *OC,
const unsigned *FP)
: TargetTriple(TT), CPU(std::string(C)), ProcFeatures(PF), ProcDesc(PD),
WriteProcResTable(WPR), WriteLatencyTable(WL), ReadAdvanceTable(RA),
Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
InitMCProcessorInfo(CPU, FS);
: TargetTriple(TT), CPU(std::string(C)), TuneCPU(std::string(TC)),
ProcFeatures(PF), ProcDesc(PD), WriteProcResTable(WPR),
WriteLatencyTable(WL), ReadAdvanceTable(RA), Stages(IS),
OperandCycles(OC), ForwardingPaths(FP) {
InitMCProcessorInfo(CPU, TuneCPU, FS);
}
FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {

4
lib/Target/AArch64/AArch64Subtarget.cpp
View File

@ -67,7 +67,7 @@ AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
if (CPUString.empty())
CPUString = "generic";
ParseSubtargetFeatures(CPUString, FS);
ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, FS);
initializeProperties();
return *this;
@ -200,7 +200,7 @@ void AArch64Subtarget::initializeProperties() {
AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
const std::string &FS,
const TargetMachine &TM, bool LittleEndian)
: AArch64GenSubtargetInfo(TT, CPU, FS),
: AArch64GenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
IsLittle(LittleEndian),

2
lib/Target/AArch64/AArch64Subtarget.h
View File

@ -511,7 +511,7 @@ public:
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
/// ClassifyGlobalReference - Find the target operand flags that describe
/// how a global value should be referenced for the current subtarget.

5
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
View File

@ -5160,7 +5160,8 @@ bool AArch64AsmParser::parseDirectiveArch(SMLoc L) {
MCSubtargetInfo &STI = copySTI();
std::vector<std::string> ArchFeatures(AArch64Features.begin(), AArch64Features.end());
STI.setDefaultFeatures("generic", join(ArchFeatures.begin(), ArchFeatures.end(), ","));
STI.setDefaultFeatures("generic", /*TuneCPU*/ "generic",
join(ArchFeatures.begin(), ArchFeatures.end(), ","));
SmallVector<StringRef, 4> RequestedExtensions;
if (!ExtensionString.empty())
@ -5262,7 +5263,7 @@ bool AArch64AsmParser::parseDirectiveCPU(SMLoc L) {
}
MCSubtargetInfo &STI = copySTI();
STI.setDefaultFeatures(CPU, "");
STI.setDefaultFeatures(CPU, /*TuneCPU*/ CPU, "");
CurLoc = incrementLoc(CurLoc, CPU.size());
ExpandCryptoAEK(llvm::AArch64::getCPUArchKind(CPU), RequestedExtensions);

2
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
View File

@ -53,7 +53,7 @@ createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
if (CPU.empty())
CPU = "generic";
return createAArch64MCSubtargetInfoImpl(TT, CPU, FS);
return createAArch64MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
}
void AArch64_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {

8
lib/Target/AMDGPU/AMDGPUSubtarget.cpp
View File

@ -57,7 +57,7 @@ R600Subtarget::initializeSubtargetDependencies(const Triple &TT,
StringRef GPU, StringRef FS) {
SmallString<256> FullFS("+promote-alloca,");
FullFS += FS;
ParseSubtargetFeatures(GPU, FullFS);
ParseSubtargetFeatures(GPU, /*TuneCPU*/ GPU, FullFS);
HasMulU24 = getGeneration() >= EVERGREEN;
HasMulI24 = hasCaymanISA();
@ -97,7 +97,7 @@ GCNSubtarget::initializeSubtargetDependencies(const Triple &TT,
FullFS += FS;
ParseSubtargetFeatures(GPU, FullFS);
ParseSubtargetFeatures(GPU, /*TuneCPU*/ GPU, FullFS);
// We don't support FP64 for EG/NI atm.
assert(!hasFP64() || (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS));
@ -170,7 +170,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT) :
GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
const GCNTargetMachine &TM) :
AMDGPUGenSubtargetInfo(TT, GPU, FS),
AMDGPUGenSubtargetInfo(TT, GPU, /*TuneCPU*/ GPU, FS),
AMDGPUSubtarget(TT),
TargetTriple(TT),
Gen(TT.getOS() == Triple::AMDHSA ? SEA_ISLANDS : SOUTHERN_ISLANDS),
@ -541,7 +541,7 @@ unsigned AMDGPUSubtarget::getKernArgSegmentSize(const Function &F,
R600Subtarget::R600Subtarget(const Triple &TT, StringRef GPU, StringRef FS,
const TargetMachine &TM) :
R600GenSubtargetInfo(TT, GPU, FS),
R600GenSubtargetInfo(TT, GPU, /*TuneCPU*/GPU, FS),
AMDGPUSubtarget(TT),
InstrInfo(*this),
FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0),

4
lib/Target/AMDGPU/AMDGPUSubtarget.h
View File

@ -471,7 +471,7 @@ public:
return &InstrItins;
}
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
Generation getGeneration() const {
return (Generation)Gen;
@ -1295,7 +1295,7 @@ public:
return &TSInfo;
}
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
Generation getGeneration() const {
return Gen;

4
lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
View File

@ -74,8 +74,8 @@ MCRegisterInfo *llvm::createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour) {
static MCSubtargetInfo *
createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
if (TT.getArch() == Triple::r600)
return createR600MCSubtargetInfoImpl(TT, CPU, FS);
return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
return createR600MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
return createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
}
static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,

8
lib/Target/ARM/ARMSubtarget.cpp
View File

@ -97,9 +97,9 @@ ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS,
const ARMBaseTargetMachine &TM, bool IsLittle,
bool MinSize)
: ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps),
CPUString(CPU), OptMinSize(MinSize), IsLittle(IsLittle),
TargetTriple(TT), Options(TM.Options), TM(TM),
: ARMGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
UseMulOps(UseFusedMulOps), CPUString(CPU), OptMinSize(MinSize),
IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options), TM(TM),
FrameLowering(initializeFrameLowering(CPU, FS)),
// At this point initializeSubtargetDependencies has been called so
// we can query directly.
@ -185,7 +185,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
else
ArchFS = std::string(FS);
}
ParseSubtargetFeatures(CPUString, ArchFS);
ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, ArchFS);
// FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
// Assert this for now to make the change obvious.

2
lib/Target/ARM/ARMSubtarget.h
View File

@ -526,7 +526,7 @@ public:
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
/// initializeSubtargetDependencies - Initializes using a CPU and feature string
/// so that we can use initializer lists for subtarget initialization.

5
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -11134,7 +11134,8 @@ bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
bool WasThumb = isThumb();
Triple T;
MCSubtargetInfo &STI = copySTI();
STI.setDefaultFeatures("", ("+" + ARM::getArchName(ID)).str());
STI.setDefaultFeatures("", /*TuneCPU*/ "",
("+" + ARM::getArchName(ID)).str());
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
FixModeAfterArchChange(WasThumb, L);
@ -11247,7 +11248,7 @@ bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
bool WasThumb = isThumb();
MCSubtargetInfo &STI = copySTI();
STI.setDefaultFeatures(CPU, "");
STI.setDefaultFeatures(CPU, /*TuneCPU*/ CPU, "");
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
FixModeAfterArchChange(WasThumb, L);

2
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
View File

@ -190,7 +190,7 @@ MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
ArchFS = std::string(FS);
}
return createARMMCSubtargetInfoImpl(TT, CPU, ArchFS);
return createARMMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS);
}
static MCInstrInfo *createARMMCInstrInfo() {

6
lib/Target/AVR/AVRSubtarget.cpp
View File

@ -29,7 +29,7 @@ namespace llvm {
AVRSubtarget::AVRSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const AVRTargetMachine &TM)
: AVRGenSubtargetInfo(TT, CPU, FS), ELFArch(0),
: AVRGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), ELFArch(0),
// Subtarget features
m_hasSRAM(false), m_hasJMPCALL(false), m_hasIJMPCALL(false),
@ -43,14 +43,14 @@ AVRSubtarget::AVRSubtarget(const Triple &TT, const std::string &CPU,
InstrInfo(), FrameLowering(),
TLInfo(TM, initializeSubtargetDependencies(CPU, FS, TM)), TSInfo() {
// Parse features string.
ParseSubtargetFeatures(CPU, FS);
ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
}
AVRSubtarget &
AVRSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
const TargetMachine &TM) {
// Parse features string.
ParseSubtargetFeatures(CPU, FS);
ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
return *this;
}

2
lib/Target/AVR/AVRSubtarget.h
View File

@ -46,7 +46,7 @@ public:
/// Parses a subtarget feature string, setting appropriate options.
/// \note Definition of function is auto generated by `tblgen`.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
AVRSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
const TargetMachine &TM);

2
lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.cpp
View File

@ -53,7 +53,7 @@ static MCRegisterInfo *createAVRMCRegisterInfo(const Triple &TT) {
static MCSubtargetInfo *createAVRMCSubtargetInfo(const Triple &TT,
StringRef CPU, StringRef FS) {
return createAVRMCSubtargetInfoImpl(TT, CPU, FS);
return createAVRMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
}
static MCInstPrinter *createAVRMCInstPrinter(const Triple &T,

4
lib/Target/BPF/BPFSubtarget.cpp
View File

@ -29,7 +29,7 @@ BPFSubtarget &BPFSubtarget::initializeSubtargetDependencies(StringRef CPU,
StringRef FS) {
initializeEnvironment();
initSubtargetFeatures(CPU, FS);
ParseSubtargetFeatures(CPU, FS);
ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
return *this;
}
@ -59,6 +59,6 @@ void BPFSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM)
: BPFGenSubtargetInfo(TT, CPU, FS), InstrInfo(),
: BPFGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), InstrInfo(),
FrameLowering(initializeSubtargetDependencies(CPU, FS)),
TLInfo(TM, *this) {}

2
lib/Target/BPF/BPFSubtarget.h
View File

@ -67,7 +67,7 @@ public:
// ParseSubtargetFeatures - Parses features string setting specified
// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
bool getHasJmpExt() const { return HasJmpExt; }
bool getHasJmp32() const { return HasJmp32; }
bool getHasAlu32() const { return HasAlu32; }

2
lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp
View File

@ -46,7 +46,7 @@ static MCRegisterInfo *createBPFMCRegisterInfo(const Triple &TT) {
static MCSubtargetInfo *createBPFMCSubtargetInfo(const Triple &TT,
StringRef CPU, StringRef FS) {
return createBPFMCSubtargetInfoImpl(TT, CPU, FS);
return createBPFMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
}
static MCStreamer *createBPFMCStreamer(const Triple &T, MCContext &Ctx,

5
lib/Target/Hexagon/HexagonSubtarget.cpp
View File

@ -77,7 +77,8 @@ static cl::opt<bool> EnableCheckBankConflict("hexagon-check-bank-conflict",
HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
StringRef FS, const TargetMachine &TM)
: HexagonGenSubtargetInfo(TT, CPU, FS), OptLevel(TM.getOptLevel()),
: HexagonGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
OptLevel(TM.getOptLevel()),
CPUString(std::string(Hexagon_MC::selectHexagonCPU(CPU))),
TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
RegInfo(getHwMode()), TLInfo(TM, *this),
@ -104,7 +105,7 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
UseBSBScheduling = hasV60Ops() && EnableBSBSched;
ParseSubtargetFeatures(CPUString, FS);
ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, FS);
if (OverrideLongCalls.getPosition())
UseLongCalls = OverrideLongCalls;

2
lib/Target/Hexagon/HexagonSubtarget.h
View File

@ -135,7 +135,7 @@ public:
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
bool hasV5Ops() const {
return getHexagonArchVersion() >= Hexagon::ArchEnum::V5;

3
lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
View File

@ -468,7 +468,8 @@ MCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT,
StringRef CPUName = Features.first;
StringRef ArchFS = Features.second;
MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS);
MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(
TT, CPUName, /*TuneCPU*/ CPUName, ArchFS);
if (X != nullptr && (CPUName == "hexagonv67t"))
addArchSubtarget(X, ArchFS);

4
lib/Target/Lanai/LanaiSubtarget.cpp
View File

@ -27,7 +27,7 @@ void LanaiSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
if (CPUName.empty())
CPUName = "generic";
ParseSubtargetFeatures(CPUName, FS);
ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
}
LanaiSubtarget &LanaiSubtarget::initializeSubtargetDependencies(StringRef CPU,
@ -41,6 +41,6 @@ LanaiSubtarget::LanaiSubtarget(const Triple &TargetTriple, StringRef Cpu,
const TargetOptions & /*Options*/,
CodeModel::Model /*CodeModel*/,
CodeGenOpt::Level /*OptLevel*/)
: LanaiGenSubtargetInfo(TargetTriple, Cpu, FeatureString),
: LanaiGenSubtargetInfo(TargetTriple, Cpu, /*TuneCPU*/ Cpu, FeatureString),
FrameLowering(initializeSubtargetDependencies(Cpu, FeatureString)),
InstrInfo(), TLInfo(TM, *this), TSInfo() {}

2
lib/Target/Lanai/LanaiSubtarget.h
View File

@ -38,7 +38,7 @@ public:
// ParseSubtargetFeatures - Parses features string setting specified
// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
LanaiSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);

2
lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp
View File

@ -56,7 +56,7 @@ createLanaiMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
if (CPUName.empty())
CPUName = "generic";
return createLanaiMCSubtargetInfoImpl(TT, CPUName, FS);
return createLanaiMCSubtargetInfoImpl(TT, CPUName, /*TuneCPU*/ CPUName, FS);
}
static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,

2
lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp
View File

@ -44,7 +44,7 @@ static MCRegisterInfo *createMSP430MCRegisterInfo(const Triple &TT) {
static MCSubtargetInfo *
createMSP430MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
return createMSP430MCSubtargetInfoImpl(TT, CPU, FS);
return createMSP430MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
}
static MCInstPrinter *createMSP430MCInstPrinter(const Triple &T,

4
lib/Target/MSP430/MSP430Subtarget.cpp
View File

@ -47,7 +47,7 @@ MSP430Subtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
if (CPUName.empty())
CPUName = "msp430";
ParseSubtargetFeatures(CPUName, FS);
ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
if (HWMultModeOption != NoHWMult)
HWMultMode = HWMultModeOption;
@ -57,5 +57,5 @@ MSP430Subtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
MSP430Subtarget::MSP430Subtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM)
: MSP430GenSubtargetInfo(TT, CPU, FS), FrameLowering(),
: MSP430GenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), FrameLowering(),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this) {}

2
lib/Target/MSP430/MSP430Subtarget.h
View File

@ -54,7 +54,7 @@ public:
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
bool hasHWMult16() const { return HWMultMode == HWMult16; }
bool hasHWMult32() const { return HWMultMode == HWMult32; }

2
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
View File

@ -77,7 +77,7 @@ static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
StringRef CPU, StringRef FS) {
CPU = MIPS_MC::selectMipsCPU(TT, CPU);
return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
return createMipsMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
}
static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,

32
lib/Target/Mips/MipsSubtarget.cpp
View File

@ -70,21 +70,21 @@ void MipsSubtarget::anchor() {}
MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
bool little, const MipsTargetMachine &TM,
MaybeAlign StackAlignOverride)
: MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
NoABICalls(false), Abs2008(false), IsFP64bit(false), UseOddSPReg(true),
IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
HasCnMipsP(false), HasMips3_32(false), HasMips3_32r2(false),
HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false),
InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), HasDSPR3(false),
AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
UseTCCInDIV(false), HasSym32(false), HasEVA(false), DisableMadd4(false),
HasMT(false), HasCRC(false), HasVirt(false), HasGINV(false),
UseIndirectJumpsHazard(false), StackAlignOverride(StackAlignOverride),
TM(TM), TargetTriple(TT), TSInfo(),
InstrInfo(
MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
: MipsGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
MipsArchVersion(MipsDefault), IsLittle(little), IsSoftFloat(false),
IsSingleFloat(false), IsFPXX(false), NoABICalls(false), Abs2008(false),
IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false),
IsGP64bit(false), HasVFPU(false), HasCnMips(false), HasCnMipsP(false),
HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
HasEVA(false), DisableMadd4(false), HasMT(false), HasCRC(false),
HasVirt(false), HasGINV(false), UseIndirectJumpsHazard(false),
StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT),
TSInfo(), InstrInfo(MipsInstrInfo::create(
initializeSubtargetDependencies(CPU, FS, TM))),
FrameLowering(MipsFrameLowering::create(*this)),
TLInfo(MipsTargetLowering::create(TM, *this)) {
@ -240,7 +240,7 @@ MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
StringRef CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
// Parse features string.
ParseSubtargetFeatures(CPUName, FS);
ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
// Initialize scheduling itinerary for the specified CPU.
InstrItins = getInstrItineraryForCPU(CPUName);

2
lib/Target/Mips/MipsSubtarget.h
View File

@ -240,7 +240,7 @@ public:
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
bool hasMips1() const { return MipsArchVersion >= Mips1; }
bool hasMips2() const { return MipsArchVersion >= Mips2; }

2
lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
View File

@ -46,7 +46,7 @@ static MCRegisterInfo *createNVPTXMCRegisterInfo(const Triple &TT) {
static MCSubtargetInfo *
createNVPTXMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
return createNVPTXMCSubtargetInfoImpl(TT, CPU, FS);
return createNVPTXMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
}
static MCInstPrinter *createNVPTXMCInstPrinter(const Triple &T,

8
lib/Target/NVPTX/NVPTXSubtarget.cpp
View File

@ -35,7 +35,7 @@ NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU,
// Provide the default CPU if we don't have one.
TargetName = std::string(CPU.empty() ? "sm_20" : CPU);
ParseSubtargetFeatures(TargetName, FS);
ParseSubtargetFeatures(TargetName, /*TuneCPU*/ TargetName, FS);
// Set default to PTX 3.2 (CUDA 5.5)
if (PTXVersion == 0) {
@ -48,9 +48,9 @@ NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU,
NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS,
const NVPTXTargetMachine &TM)
: NVPTXGenSubtargetInfo(TT, CPU, FS), PTXVersion(0), SmVersion(20), TM(TM),
InstrInfo(), TLInfo(TM, initializeSubtargetDependencies(CPU, FS)),
FrameLowering() {}
: NVPTXGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), PTXVersion(0),
SmVersion(20), TM(TM), InstrInfo(),
TLInfo(TM, initializeSubtargetDependencies(CPU, FS)), FrameLowering() {}
bool NVPTXSubtarget::hasImageHandles() const {
// Enable handles for Kepler+, where CUDA supports indirect surfaces and

2
lib/Target/NVPTX/NVPTXSubtarget.h
View File

@ -83,7 +83,7 @@ public:
unsigned getPTXVersion() const { return PTXVersion; }
NVPTXSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
};
} // End llvm namespace

2
lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
View File

@ -78,7 +78,7 @@ static MCRegisterInfo *createPPCMCRegisterInfo(const Triple &TT) {
static MCSubtargetInfo *createPPCMCSubtargetInfo(const Triple &TT,
StringRef CPU, StringRef FS) {
return createPPCMCSubtargetInfoImpl(TT, CPU, FS);
return createPPCMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
}
static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI,

4
lib/Target/PowerPC/PPCSubtarget.cpp
View File

@ -49,7 +49,7 @@ PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const PPCTargetMachine &TM)
: PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
: PPCGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TargetTriple(TT),
IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
TargetTriple.getArch() == Triple::ppc64le),
TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
@ -139,7 +139,7 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
InstrItins = getInstrItineraryForCPU(CPUName);
// Parse features string.
ParseSubtargetFeatures(CPUName, FS);
ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
// If the user requested use of 64-bit regs, but the cpu selected doesn't
// support it, ignore.

2
lib/Target/PowerPC/PPCSubtarget.h
View File

@ -165,7 +165,7 @@ public:
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
/// getStackAlignment - Returns the minimum alignment known to hold of the
/// stack frame on entry to the function and which must be maintained by every

2
lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
View File

@ -68,7 +68,7 @@ static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
std::string CPUName = std::string(CPU);
if (CPUName.empty())
CPUName = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
return createRISCVMCSubtargetInfoImpl(TT, CPUName, FS);
return createRISCVMCSubtargetInfoImpl(TT, CPUName, /*TuneCPU*/ CPUName, FS);
}
static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,

4
lib/Target/RISCV/RISCVSubtarget.cpp
View File

@ -36,7 +36,7 @@ RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
std::string CPUName = std::string(CPU);
if (CPUName.empty())
CPUName = Is64Bit ? "generic-rv64" : "generic-rv32";
ParseSubtargetFeatures(CPUName, FS);
ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
if (Is64Bit) {
XLenVT = MVT::i64;
XLen = 64;
@ -49,7 +49,7 @@ RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(
RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
StringRef ABIName, const TargetMachine &TM)
: RISCVGenSubtargetInfo(TT, CPU, FS),
: RISCVGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
UserReservedRegister(RISCV::NUM_TARGET_REGS),
FrameLowering(initializeSubtargetDependencies(TT, CPU, FS, ABIName)),
InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {

2
lib/Target/RISCV/RISCVSubtarget.h
View File

@ -79,7 +79,7 @@ public:
// Parses features string setting specified subtarget options. The
// definition of this function is auto-generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
const RISCVFrameLowering *getFrameLowering() const override {
return &FrameLowering;

2
lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
View File

@ -68,7 +68,7 @@ static MCSubtargetInfo *
createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
if (CPU.empty())
CPU = (TT.getArch() == Triple::sparcv9) ? "v9" : "v8";
return createSparcMCSubtargetInfoImpl(TT, CPU, FS);
return createSparcMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
}
static MCTargetStreamer *

8
lib/Target/Sparc/SparcSubtarget.cpp
View File

@ -55,7 +55,7 @@ SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
CPUName = (Is64Bit) ? "v9" : "v8";
// Parse features string.
ParseSubtargetFeatures(CPUName, FS);
ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
// Popc is a v9-only instruction.
if (!IsV9)
@ -67,9 +67,9 @@ SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
SparcSubtarget::SparcSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM,
bool is64Bit)
: SparcGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), Is64Bit(is64Bit),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
FrameLowering(*this) {}
: SparcGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TargetTriple(TT),
Is64Bit(is64Bit), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
TLInfo(TM, *this), FrameLowering(*this) {}
int SparcSubtarget::getAdjustedFrameSize(int frameSize) const {

2
lib/Target/Sparc/SparcSubtarget.h
View File

@ -101,7 +101,7 @@ public:
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
SparcSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
bool is64Bit() const { return Is64Bit; }

2
lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
View File

@ -171,7 +171,7 @@ static MCRegisterInfo *createSystemZMCRegisterInfo(const Triple &TT) {
static MCSubtargetInfo *
createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
return createSystemZMCSubtargetInfoImpl(TT, CPU, FS);
return createSystemZMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
}
static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T,

14
lib/Target/SystemZ/SystemZSubtarget.cpp
View File

@ -33,7 +33,7 @@ SystemZSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
if (CPUName.empty())
CPUName = "generic";
// Parse features string.
ParseSubtargetFeatures(CPUName, FS);
ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
// -msoft-float implies -mno-vx.
if (HasSoftFloat)
@ -53,12 +53,12 @@ SystemZSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS,
const TargetMachine &TM)
: SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false),
HasPopulationCount(false), HasMessageSecurityAssist3(false),
HasMessageSecurityAssist4(false), HasResetReferenceBitsMultiple(false),
HasFastSerialization(false), HasInterlockedAccess1(false),
HasMiscellaneousExtensions(false),
: SystemZGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
HasDistinctOps(false), HasLoadStoreOnCond(false), HasHighWord(false),
HasFPExtension(false), HasPopulationCount(false),
HasMessageSecurityAssist3(false), HasMessageSecurityAssist4(false),
HasResetReferenceBitsMultiple(false), HasFastSerialization(false),
HasInterlockedAccess1(false), HasMiscellaneousExtensions(false),
HasExecutionHint(false), HasLoadAndTrap(false),
HasTransactionalExecution(false), HasProcessorAssist(false),
HasDFPZonedConversion(false), HasEnhancedDAT2(false),

2
lib/Target/SystemZ/SystemZSubtarget.h
View File

@ -112,7 +112,7 @@ public:
bool enableSubRegLiveness() const override;
// Automatically generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
// Return true if the target has the distinct-operands facility.
bool hasDistinctOps() const { return HasDistinctOps; }

2
lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
View File

@ -76,7 +76,7 @@ static MCAsmBackend *createAsmBackend(const Target & /*T*/,
static MCSubtargetInfo *createMCSubtargetInfo(const Triple &TT, StringRef CPU,
StringRef FS) {
return createWebAssemblyMCSubtargetInfoImpl(TT, CPU, FS);
return createWebAssemblyMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
}
static MCTargetStreamer *

9
lib/Target/WebAssembly/WebAssemblySubtarget.cpp
View File

@ -33,7 +33,7 @@ WebAssemblySubtarget::initializeSubtargetDependencies(StringRef CPU,
if (CPU.empty())
CPU = "generic";
ParseSubtargetFeatures(CPU, FS);
ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
return *this;
}
@ -41,9 +41,10 @@ WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT,
const std::string &CPU,
const std::string &FS,
const TargetMachine &TM)
: WebAssemblyGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
FrameLowering(), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
TSInfo(), TLInfo(TM, *this) {}
: WebAssemblyGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
TargetTriple(TT), FrameLowering(),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TSInfo(),
TLInfo(TM, *this) {}
bool WebAssemblySubtarget::enableAtomicExpand() const {
// If atomics are disabled, atomic ops are lowered instead of expanded

2
lib/Target/WebAssembly/WebAssemblySubtarget.h
View File

@ -105,7 +105,7 @@ public:
/// Parses features string setting specified subtarget options. Definition of
/// function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
};
} // end namespace llvm

2
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
View File

@ -295,7 +295,7 @@ MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
if (CPU.empty())
CPU = "generic";
return createX86MCSubtargetInfoImpl(TT, CPU, ArchFS);
return createX86MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS);
}
static MCInstrInfo *createX86MCInstrInfo() {

4
lib/Target/X86/X86.td
View File

@ -1018,12 +1018,12 @@ def ProcessorFeatures {
class Proc<string Name, list<SubtargetFeature> Features,
list<SubtargetFeature> TuneFeatures>
: ProcessorModel<Name, GenericModel, !listconcat(Features, TuneFeatures)>;
: ProcessorModel<Name, GenericModel, Features, TuneFeatures>;
class ProcModel<string Name, SchedMachineModel Model,
list<SubtargetFeature> Features,
list<SubtargetFeature> TuneFeatures>
: ProcessorModel<Name, Model, !listconcat(Features, TuneFeatures)>;
: ProcessorModel<Name, Model, Features, TuneFeatures>;
// NOTE: CMPXCHG8B is here for legacy compatibility so that it is only disabled
// if i386/i486 is specifically requested.

24
lib/Target/X86/X86Subtarget.cpp
View File

@ -227,10 +227,14 @@ bool X86Subtarget::isLegalToCallImmediateAddr() const {
return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
}
void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,
StringRef FS) {
if (CPU.empty())
CPU = "generic";
if (TuneCPU.empty())
TuneCPU = "generic";
std::string FullFS = X86_MC::ParseX86Triple(TargetTriple);
assert(!FullFS.empty() && "Failed to parse X86 triple");
@ -238,7 +242,7 @@ void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
FullFS = (Twine(FullFS) + "," + FS).str();
// Parse features string and set the CPU.
ParseSubtargetFeatures(CPU, FullFS);
ParseSubtargetFeatures(CPU, TuneCPU, FullFS);
// All CPUs that implement SSE4.2 or SSE4A support unaligned accesses of
// 16-bytes and under that are reasonably fast. These features were
@ -272,22 +276,24 @@ void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
}
X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,
StringRef TuneCPU,
StringRef FS) {
initSubtargetFeatures(CPU, FS);
initSubtargetFeatures(CPU, TuneCPU, FS);
return *this;
}
X86Subtarget::X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
const X86TargetMachine &TM,
X86Subtarget::X86Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
StringRef FS, const X86TargetMachine &TM,
MaybeAlign StackAlignOverride,
unsigned PreferVectorWidthOverride,
unsigned RequiredVectorWidth)
: X86GenSubtargetInfo(TT, CPU, FS), PICStyle(PICStyles::Style::None),
TM(TM), TargetTriple(TT), StackAlignOverride(StackAlignOverride),
: X86GenSubtargetInfo(TT, CPU, TuneCPU, FS),
PICStyle(PICStyles::Style::None), TM(TM), TargetTriple(TT),
StackAlignOverride(StackAlignOverride),
PreferVectorWidthOverride(PreferVectorWidthOverride),
RequiredVectorWidth(RequiredVectorWidth),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
FrameLowering(*this, getStackAlignment()) {
InstrInfo(initializeSubtargetDependencies(CPU, TuneCPU, FS)),
TLInfo(TM, *this), FrameLowering(*this, getStackAlignment()) {
// Determine the PICStyle based on the target selected.
if (!isPositionIndependent())
setPICStyle(PICStyles::Style::None);

10
lib/Target/X86/X86Subtarget.h
View File

@ -514,7 +514,7 @@ public:
/// This constructor initializes the data members to match that
/// of the specified triple.
///
X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
X86Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
const X86TargetMachine &TM, MaybeAlign StackAlignOverride,
unsigned PreferVectorWidthOverride,
unsigned RequiredVectorWidth);
@ -548,7 +548,7 @@ public:
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
/// Methods used by Global ISel
const CallLowering *getCallLowering() const override;
@ -559,8 +559,10 @@ public:
private:
/// Initialize the full set of dependencies so we can use an initializer
/// list for X86Subtarget.
X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
void initSubtargetFeatures(StringRef CPU, StringRef FS);
X86Subtarget &initializeSubtargetDependencies(StringRef CPU,
StringRef TuneCPU,
StringRef FS);
void initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
public:
/// Is this x86_64? (disregarding specific ABI / programming model)

10
lib/Target/X86/X86TargetMachine.cpp
View File

@ -233,11 +233,15 @@ X86TargetMachine::~X86TargetMachine() = default;
const X86Subtarget *
X86TargetMachine::getSubtargetImpl(const Function &F) const {
Attribute CPUAttr = F.getFnAttribute("target-cpu");
Attribute TuneAttr = F.getFnAttribute("tune-cpu");
Attribute FSAttr = F.getFnAttribute("target-features");
StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
? CPUAttr.getValueAsString()
: (StringRef)TargetCPU;
StringRef TuneCPU = !TuneAttr.hasAttribute(Attribute::None)
? TuneAttr.getValueAsString()
: (StringRef)CPU;
StringRef FS = !FSAttr.hasAttribute(Attribute::None)
? FSAttr.getValueAsString()
: (StringRef)TargetFS;
@ -276,6 +280,10 @@ X86TargetMachine::getSubtargetImpl(const Function &F) const {
// Add CPU to the Key.
Key += CPU;
// Add tune CPU to the Key.
Key += "tune=";
Key += TuneCPU;
// Keep track of the start of the feature portion of the string.
unsigned FSStart = Key.size();
@ -304,7 +312,7 @@ X86TargetMachine::getSubtargetImpl(const Function &F) const {
// function that reside in TargetOptions.
resetTargetOptions(F);
I = std::make_unique<X86Subtarget>(
TargetTriple, CPU, FS, *this,
TargetTriple, CPU, TuneCPU, FS, *this,
MaybeAlign(Options.StackAlignmentOverride), PreferVectorWidthOverride,
RequiredVectorWidth);
}

2
lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
View File

@ -51,7 +51,7 @@ static MCRegisterInfo *createXCoreMCRegisterInfo(const Triple &TT) {
static MCSubtargetInfo *
createXCoreMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
return createXCoreMCSubtargetInfoImpl(TT, CPU, FS);
return createXCoreMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
}
static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI,

4
lib/Target/XCore/XCoreSubtarget.cpp
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@ -26,5 +26,5 @@ void XCoreSubtarget::anchor() { }
XCoreSubtarget::XCoreSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM)
: XCoreGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this),
TLInfo(TM, *this), TSInfo() {}
: XCoreGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), InstrInfo(),
FrameLowering(*this), TLInfo(TM, *this), TSInfo() {}

2
lib/Target/XCore/XCoreSubtarget.h
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@ -44,7 +44,7 @@ public:
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
const XCoreInstrInfo *getInstrInfo() const override { return &InstrInfo; }
const XCoreFrameLowering *getFrameLowering() const override {

2
unittests/CodeGen/MFCommon.inc
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@ -72,7 +72,7 @@ public:
class BogusSubtarget : public TargetSubtargetInfo {
public:
BogusSubtarget(TargetMachine &TM)
: TargetSubtargetInfo(Triple(""), "", "", {}, {}, nullptr, nullptr,
: TargetSubtargetInfo(Triple(""), "", "", "", {}, {}, nullptr, nullptr,
nullptr, nullptr, nullptr, nullptr),
FL(), TL(TM) {}
~BogusSubtarget() override {}

26
utils/TableGen/SubtargetEmitter.cpp
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@ -267,12 +267,15 @@ SubtargetEmitter::CPUKeyValues(raw_ostream &OS,
for (Record *Processor : ProcessorList) {
StringRef Name = Processor->getValueAsString("Name");
RecVec FeatureList = Processor->getValueAsListOfDefs("Features");
RecVec TuneFeatureList = Processor->getValueAsListOfDefs("TuneFeatures");
// Emit as { "cpu", "description", 0, { f1 , f2 , ... fn } },
OS << " { "
<< "\"" << Name << "\", ";
printFeatureMask(OS, FeatureList, FeatureMap);
OS << ", ";
printFeatureMask(OS, TuneFeatureList, FeatureMap);
// Emit the scheduler model pointer.
const std::string &ProcModelName =
@ -1692,7 +1695,8 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
<< "// subtarget options.\n"
<< "void llvm::";
OS << Target;
OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {\n"
OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, "
<< "StringRef FS) {\n"
<< " LLVM_DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n"
<< " LLVM_DEBUG(dbgs() << \"\\nCPU:\" << CPU << \"\\n\\n\");\n";
@ -1701,7 +1705,7 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
return;
}
OS << " InitMCProcessorInfo(CPU, FS);\n"
OS << " InitMCProcessorInfo(CPU, TuneCPU, FS);\n"
<< " const FeatureBitset& Bits = getFeatureBits();\n";
for (Record *R : Features) {
@ -1734,14 +1738,15 @@ void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
OS << "struct " << Target
<< "GenMCSubtargetInfo : public MCSubtargetInfo {\n";
OS << " " << Target << "GenMCSubtargetInfo(const Triple &TT, \n"
<< " StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,\n"
OS << " " << Target << "GenMCSubtargetInfo(const Triple &TT,\n"
<< " StringRef CPU, StringRef TuneCPU, StringRef FS,\n"
<< " ArrayRef<SubtargetFeatureKV> PF,\n"
<< " ArrayRef<SubtargetSubTypeKV> PD,\n"
<< " const MCWriteProcResEntry *WPR,\n"
<< " const MCWriteLatencyEntry *WL,\n"
<< " const MCReadAdvanceEntry *RA, const InstrStage *IS,\n"
<< " const unsigned *OC, const unsigned *FP) :\n"
<< " MCSubtargetInfo(TT, CPU, FS, PF, PD,\n"
<< " MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,\n"
<< " WPR, WL, RA, IS, OC, FP) { }\n\n"
<< " unsigned resolveVariantSchedClass(unsigned SchedClass,\n"
<< " const MCInst *MI, unsigned CPUID) const override {\n"
@ -1817,8 +1822,9 @@ void SubtargetEmitter::run(raw_ostream &OS) {
OS << "\nstatic inline MCSubtargetInfo *create" << Target
<< "MCSubtargetInfoImpl("
<< "const Triple &TT, StringRef CPU, StringRef FS) {\n";
OS << " return new " << Target << "GenMCSubtargetInfo(TT, CPU, FS, ";
<< "const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {\n";
OS << " return new " << Target
<< "GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, ";
if (NumFeatures)
OS << Target << "FeatureKV, ";
else
@ -1866,7 +1872,7 @@ void SubtargetEmitter::run(raw_ostream &OS) {
<< "} // end namespace " << Target << "_MC\n\n";
OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
<< " explicit " << ClassName << "(const Triple &TT, StringRef CPU, "
<< "StringRef FS);\n"
<< "StringRef TuneCPU, StringRef FS);\n"
<< "public:\n"
<< " unsigned resolveSchedClass(unsigned SchedClass, "
<< " const MachineInstr *DefMI,"
@ -1909,8 +1915,8 @@ void SubtargetEmitter::run(raw_ostream &OS) {
}
OS << ClassName << "::" << ClassName << "(const Triple &TT, StringRef CPU, "
<< "StringRef FS)\n"
<< " : TargetSubtargetInfo(TT, CPU, FS, ";
<< "StringRef TuneCPU, StringRef FS)\n"
<< " : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ";
if (NumFeatures)
OS << "makeArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), ";
else