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Rename features to match what gcc and clang use.

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There is no advantage in being different and using the same names simplifies
clang a bit.

llvm-svn: 189141
This commit is contained in:
Rafael Espindola 2013-08-23 20:21:34 +00:00
parent a2ec50d21b
commit 112bdc8929
13 changed files with 17 additions and 17 deletions
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6
lib/Target/X86/X86.td
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@ -50,10 +50,10 @@ def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
"Enable SSSE3 instructions",
[FeatureSSE3]>;
def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
"Enable SSE 4.1 instructions",
[FeatureSSSE3]>;
def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
"Enable SSE 4.2 instructions",
[FeatureSSE41]>;
def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
@ -119,7 +119,7 @@ def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
[FeatureSSE2]>;
def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
"Support MOVBE instruction">;
def FeatureRDRAND : SubtargetFeature<"rdrand", "HasRDRAND", "true",
def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
"Support RDRAND instruction">;
def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
"Support 16-bit floating point conversion instructions">;

2
test/CodeGen/X86/bool-simplify.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 -mattr=+sse41,-avx,+rdrand,+rdseed | FileCheck %s
; RUN: llc < %s -march=x86-64 -mattr=+sse4.1,-avx,+rdrnd,+rdseed | FileCheck %s
define i32 @foo(<2 x i64> %c, i32 %a, i32 %b) {
%t1 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %c, <2 x i64> %c)

2
test/CodeGen/X86/vec_compare-sse4.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=x86 -mattr=-sse3,+sse2 | FileCheck %s -check-prefix=SSE2
; RUN: llc < %s -march=x86 -mattr=-sse42,+sse41 | FileCheck %s -check-prefix=SSE41
; RUN: llc < %s -march=x86 -mattr=-sse4.2,+sse4.1 | FileCheck %s -check-prefix=SSE41
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s -check-prefix=SSE42
define <2 x i64> @test1(<2 x i64> %A, <2 x i64> %B) nounwind {

2
test/CodeGen/X86/vec_extract.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -mcpu=corei7 -march=x86 -mattr=+sse2,-sse41 -o %t
; RUN: llc < %s -mcpu=corei7 -march=x86 -mattr=+sse2,-sse4.1 -o %t
; RUN: grep movss %t | count 4
; RUN: grep movhlps %t | count 1
; RUN: not grep pshufd %t

4
test/CodeGen/X86/vec_insert-2.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | FileCheck --check-prefix=X32 %s
; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse41 | FileCheck --check-prefix=X64 %s
; RUN: llc < %s -march=x86 -mattr=+sse2,-sse4.1 | FileCheck --check-prefix=X32 %s
; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse4.1 | FileCheck --check-prefix=X64 %s
define <4 x float> @t1(float %s, <4 x float> %tmp) nounwind {
; X32-LABEL: t1:

2
test/CodeGen/X86/vec_insert-3.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse41 | grep punpcklqdq | count 1
; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse4.1 | grep punpcklqdq | count 1
define <2 x i64> @t1(i64 %s, <2 x i64> %tmp) nounwind {
%tmp1 = insertelement <2 x i64> %tmp, i64 %s, i32 1

4
test/CodeGen/X86/vec_insert.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep movss | count 1
; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | not grep pinsrw
; RUN: llc < %s -march=x86 -mattr=+sse2,-sse4.1 | grep movss | count 1
; RUN: llc < %s -march=x86 -mattr=+sse2,-sse4.1 | not grep pinsrw
define void @test(<4 x float>* %F, i32 %I) nounwind {
%tmp = load <4 x float>* %F ; <<4 x float>> [#uses=1]

2
test/CodeGen/X86/vec_set.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep punpckl | count 7
; RUN: llc < %s -march=x86 -mattr=+sse2,-sse4.1 | grep punpckl | count 7
define void @test(<8 x i16>* %b, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7) nounwind {
%tmp = insertelement <8 x i16> zeroinitializer, i16 %a0, i32 0 ; <<8 x i16>> [#uses=1]

2
test/CodeGen/X86/vec_setcc.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse2 | FileCheck %s -check-prefix=SSE2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse41 | FileCheck %s -check-prefix=SSE41
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=sse4.1 | FileCheck %s -check-prefix=SSE41
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=avx | FileCheck %s -check-prefix=AVX
define <16 x i8> @v16i8_icmp_uge(<16 x i8> %a, <16 x i8> %b) nounwind readnone ssp uwtable {

2
test/CodeGen/X86/vec_shuffle-26.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mcpu=generic -mattr=sse41 | FileCheck %s
; RUN: llc < %s -march=x86 -mcpu=generic -mattr=sse4.1 | FileCheck %s
; RUN: llc < %s -march=x86 -mcpu=atom | FileCheck -check-prefix=ATOM %s
; Transpose example using the more generic vector shuffle. Return float8

2
test/CodeGen/X86/widen_arith-3.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -mcpu=generic -march=x86 -mattr=+sse42 -post-RA-scheduler=true | FileCheck %s
; RUN: llc < %s -mcpu=generic -march=x86 -mattr=+sse4.2 -post-RA-scheduler=true | FileCheck %s
; CHECK: paddd
; Widen a v3i16 to v8i16 to do a vector add

2
test/CodeGen/X86/widen_cast-1.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=x86 -mcpu=generic -mattr=+sse42 < %s | FileCheck %s
; RUN: llc -march=x86 -mcpu=generic -mattr=+sse4.2 < %s | FileCheck %s
; RUN: llc -march=x86 -mcpu=atom < %s | FileCheck -check-prefix=ATOM %s
; CHECK: paddd

2
test/CodeGen/X86/widen_load-2.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -o - -mcpu=generic -march=x86-64 -mattr=+sse42 | FileCheck %s
; RUN: llc < %s -o - -mcpu=generic -march=x86-64 -mattr=+sse4.2 | FileCheck %s
; Test based on pr5626 to load/store
;