mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-12-27 22:15:18 +00:00
Pull operand asm string into base class, shrinkifying intrinsic definitions.
No functionality change. llvm-svn: 27320
This commit is contained in:
Chris Lattner
parent
fc0a2ac06e
commit
12e9ce7104
@ -70,13 +70,15 @@ class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID>
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[(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
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// VX1_Int - A VXForm_1 intrinsic definition.
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class VX1_Int<bits<11> xo, string asmstr, Intrinsic IntID>
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: VXForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), asmstr, VecFP,
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class VX1_Int<bits<11> xo, string opc, Intrinsic IntID>
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: VXForm_1<xo, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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!strconcat(opc, " $vD, $vA, $vB"), VecFP,
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[(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>;
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// VX2_Int - A VXForm_2 intrinsic definition.
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class VX2_Int<bits<11> xo, string asmstr, Intrinsic IntID>
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: VXForm_2<xo, (ops VRRC:$vD, VRRC:$vB), asmstr, VecFP,
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class VX2_Int<bits<11> xo, string opc, Intrinsic IntID>
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: VXForm_2<xo, (ops VRRC:$vD, VRRC:$vB),
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!strconcat(opc, " $vD, $vB"), VecFP,
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[(set VRRC:$vD, (IntID VRRC:$vB))]>;
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//===----------------------------------------------------------------------===//
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@ -231,10 +233,10 @@ def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vminfp $vD, $vA, $vB", VecFP,
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[]>;
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def VMRGHH : VX1_Int<76 , "vmrghh $vD, $vA, $vB", int_ppc_altivec_vmrghh>;
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def VMRGHW : VX1_Int<140, "vmrghw $vD, $vA, $vB", int_ppc_altivec_vmrghw>;
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def VMRGLH : VX1_Int<332, "vmrglh $vD, $vA, $vB", int_ppc_altivec_vmrglh>;
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def VMRGLW : VX1_Int<396, "vmrglw $vD, $vA, $vB", int_ppc_altivec_vmrglw>;
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def VMRGHH : VX1_Int<76 , "vmrghh", int_ppc_altivec_vmrghh>;
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def VMRGHW : VX1_Int<140, "vmrghw", int_ppc_altivec_vmrghw>;
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def VMRGLH : VX1_Int<332, "vmrglh", int_ppc_altivec_vmrglh>;
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def VMRGLW : VX1_Int<396, "vmrglw", int_ppc_altivec_vmrglw>;
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def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>;
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def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>;
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@ -243,23 +245,23 @@ def VMSUMUBM : VA1a_Int<36, "vmsumubm", int_ppc_altivec_vmsumubm>;
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def VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>;
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def VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>;
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def VMULESB : VX1_Int<776, "vmulesb $vD, $vA, $vB", int_ppc_altivec_vmulesb>;
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def VMULESH : VX1_Int<840, "vmulesh $vD, $vA, $vB", int_ppc_altivec_vmulesh>;
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def VMULEUB : VX1_Int<520, "vmuleub $vD, $vA, $vB", int_ppc_altivec_vmuleub>;
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def VMULEUH : VX1_Int<584, "vmuleuh $vD, $vA, $vB", int_ppc_altivec_vmuleuh>;
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def VMULOSB : VX1_Int<264, "vmulosb $vD, $vA, $vB", int_ppc_altivec_vmulosb>;
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def VMULOSH : VX1_Int<328, "vmulosh $vD, $vA, $vB", int_ppc_altivec_vmulosh>;
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def VMULOUB : VX1_Int< 8, "vmuloub $vD, $vA, $vB", int_ppc_altivec_vmuloub>;
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def VMULOUH : VX1_Int< 72, "vmulouh $vD, $vA, $vB", int_ppc_altivec_vmulouh>;
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def VMULESB : VX1_Int<776, "vmulesb", int_ppc_altivec_vmulesb>;
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def VMULESH : VX1_Int<840, "vmulesh", int_ppc_altivec_vmulesh>;
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def VMULEUB : VX1_Int<520, "vmuleub", int_ppc_altivec_vmuleub>;
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def VMULEUH : VX1_Int<584, "vmuleuh", int_ppc_altivec_vmuleuh>;
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def VMULOSB : VX1_Int<264, "vmulosb", int_ppc_altivec_vmulosb>;
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def VMULOSH : VX1_Int<328, "vmulosh", int_ppc_altivec_vmulosh>;
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def VMULOUB : VX1_Int< 8, "vmuloub", int_ppc_altivec_vmuloub>;
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def VMULOUH : VX1_Int< 72, "vmulouh", int_ppc_altivec_vmulouh>;
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def VREFP : VX2_Int<266, "vrefp $vD, $vB", int_ppc_altivec_vrefp>;
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def VRFIM : VX2_Int<714, "vrfim $vD, $vB", int_ppc_altivec_vrfim>;
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def VRFIN : VX2_Int<522, "vrfin $vD, $vB", int_ppc_altivec_vrfin>;
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def VRFIP : VX2_Int<650, "vrfip $vD, $vB", int_ppc_altivec_vrfip>;
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def VRFIZ : VX2_Int<586, "vrfiz $vD, $vB", int_ppc_altivec_vrfiz>;
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def VRSQRTEFP : VX2_Int<330, "vrsqrtefp $vD, $vB", int_ppc_altivec_vrsqrtefp>;
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def VREFP : VX2_Int<266, "vrefp", int_ppc_altivec_vrefp>;
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def VRFIM : VX2_Int<714, "vrfim", int_ppc_altivec_vrfim>;
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def VRFIN : VX2_Int<522, "vrfin", int_ppc_altivec_vrfin>;
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def VRFIP : VX2_Int<650, "vrfip", int_ppc_altivec_vrfip>;
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def VRFIZ : VX2_Int<586, "vrfiz", int_ppc_altivec_vrfiz>;
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def VRSQRTEFP : VX2_Int<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
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def VSUBCUW : VX1_Int<74, "vsubcuw $vD, $vA, $vB", int_ppc_altivec_vsubcuw>;
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def VSUBCUW : VX1_Int<74, "vsubcuw", int_ppc_altivec_vsubcuw>;
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def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsubfp $vD, $vA, $vB", VecGeneral,
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@ -274,17 +276,17 @@ def VSUBUWM : VXForm_1<1152, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vsubuwm $vD, $vA, $vB", VecGeneral,
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[(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>;
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def VSUBSBS : VX1_Int<1792, "vsubsbs $vD, $vA, $vB", int_ppc_altivec_vsubsbs>;
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def VSUBSHS : VX1_Int<1856, "vsubshs $vD, $vA, $vB", int_ppc_altivec_vsubshs>;
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def VSUBSWS : VX1_Int<1920, "vsubsws $vD, $vA, $vB", int_ppc_altivec_vsubsws>;
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def VSUBUBS : VX1_Int<1536, "vsububs $vD, $vA, $vB", int_ppc_altivec_vsububs>;
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def VSUBUHS : VX1_Int<1600, "vsubuhs $vD, $vA, $vB", int_ppc_altivec_vsubuhs>;
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def VSUBUWS : VX1_Int<1664, "vsubuws $vD, $vA, $vB", int_ppc_altivec_vsubuws>;
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def VSUMSWS : VX1_Int<1928, "vsumsws $vD, $vA, $vB", int_ppc_altivec_vsumsws>;
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def VSUM2SWS: VX1_Int<1672, "vsum2sws $vD, $vA, $vB", int_ppc_altivec_vsum2sws>;
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def VSUM4SBS: VX1_Int<1672, "vsum4sbs $vD, $vA, $vB", int_ppc_altivec_vsum4sbs>;
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def VSUM4SHS: VX1_Int<1608, "vsum4shs $vD, $vA, $vB", int_ppc_altivec_vsum4shs>;
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def VSUM4UBS: VX1_Int<1544, "vsum4ubs $vD, $vA, $vB", int_ppc_altivec_vsum4ubs>;
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def VSUBSBS : VX1_Int<1792, "vsubsbs" , int_ppc_altivec_vsubsbs>;
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def VSUBSHS : VX1_Int<1856, "vsubshs" , int_ppc_altivec_vsubshs>;
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def VSUBSWS : VX1_Int<1920, "vsubsws" , int_ppc_altivec_vsubsws>;
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def VSUBUBS : VX1_Int<1536, "vsububs" , int_ppc_altivec_vsububs>;
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def VSUBUHS : VX1_Int<1600, "vsubuhs" , int_ppc_altivec_vsubuhs>;
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def VSUBUWS : VX1_Int<1664, "vsubuws" , int_ppc_altivec_vsubuws>;
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def VSUMSWS : VX1_Int<1928, "vsumsws" , int_ppc_altivec_vsumsws>;
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def VSUM2SWS: VX1_Int<1672, "vsum2sws", int_ppc_altivec_vsum2sws>;
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def VSUM4SBS: VX1_Int<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs>;
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def VSUM4SHS: VX1_Int<1608, "vsum4shs", int_ppc_altivec_vsum4shs>;
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def VSUM4UBS: VX1_Int<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs>;
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def VNOR : VXForm_1<1284, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vnor $vD, $vA, $vB", VecFP,
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@ -296,13 +298,13 @@ def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vxor $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>;
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def VRLB : VX1_Int< 4, "vrlb $vD, $vA, $vB", int_ppc_altivec_vrlb>;
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def VRLH : VX1_Int< 68, "vrlh $vD, $vA, $vB", int_ppc_altivec_vrlh>;
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def VRLW : VX1_Int< 132, "vrlw $vD, $vA, $vB", int_ppc_altivec_vrlw>;
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def VSLO : VX1_Int<1036, "vslo $vD, $vA, $vB", int_ppc_altivec_vslo>;
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def VSLB : VX1_Int< 260, "vslb $vD, $vA, $vB", int_ppc_altivec_vslb>;
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def VSLH : VX1_Int< 324, "vslh $vD, $vA, $vB", int_ppc_altivec_vslh>;
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def VSLW : VX1_Int< 388, "vslw $vD, $vA, $vB", int_ppc_altivec_vslw>;
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def VRLB : VX1_Int< 4, "vrlb", int_ppc_altivec_vrlb>;
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def VRLH : VX1_Int< 68, "vrlh", int_ppc_altivec_vrlh>;
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def VRLW : VX1_Int< 132, "vrlw", int_ppc_altivec_vrlw>;
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def VSLO : VX1_Int<1036, "vslo", int_ppc_altivec_vslo>;
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def VSLB : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>;
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def VSLH : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>;
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def VSLW : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>;
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def VSPLTB : VXForm_1<524, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vspltb $vD, $vB, $UIMM", VecPerm,
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@ -315,14 +317,14 @@ def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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[(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
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VSPLT_shuffle_mask:$UIMM))]>;
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def VSR : VX1_Int< 708, "vsr $vD, $vA, $vB" , int_ppc_altivec_vsr>;
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def VSRO : VX1_Int<1100, "vsro $vD, $vA, $vB" , int_ppc_altivec_vsro>;
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def VSRAB : VX1_Int< 772, "vsrab $vD, $vA, $vB", int_ppc_altivec_vsrab>;
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def VSRAH : VX1_Int< 836, "vsrah $vD, $vA, $vB", int_ppc_altivec_vsrah>;
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def VSRAW : VX1_Int< 900, "vsraw $vD, $vA, $vB", int_ppc_altivec_vsraw>;
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def VSRB : VX1_Int< 516, "vsrb $vD, $vA, $vB" , int_ppc_altivec_vsrb>;
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def VSRH : VX1_Int< 580, "vsrh $vD, $vA, $vB" , int_ppc_altivec_vsrh>;
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def VSRW : VX1_Int< 644, "vsrw $vD, $vA, $vB" , int_ppc_altivec_vsrw>;
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def VSR : VX1_Int< 708, "vsr" , int_ppc_altivec_vsr>;
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def VSRO : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>;
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def VSRAB : VX1_Int< 772, "vsrab", int_ppc_altivec_vsrab>;
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def VSRAH : VX1_Int< 836, "vsrah", int_ppc_altivec_vsrah>;
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def VSRAW : VX1_Int< 900, "vsraw", int_ppc_altivec_vsraw>;
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def VSRB : VX1_Int< 516, "vsrb" , int_ppc_altivec_vsrb>;
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def VSRH : VX1_Int< 580, "vsrh" , int_ppc_altivec_vsrh>;
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def VSRW : VX1_Int< 644, "vsrw" , int_ppc_altivec_vsrw>;
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def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),
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@ -336,40 +338,19 @@ def VSPLTISW : VXForm_3<908, (ops VRRC:$vD, s5imm:$SIMM),
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[(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
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// Vector Pack.
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def VPKPX : VXForm_1<782, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vpkpx $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vpkpx VRRC:$vA, VRRC:$vB))]>;
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def VPKSHSS : VXForm_1<398, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vpkshss $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vpkshss VRRC:$vA, VRRC:$vB))]>;
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def VPKSHUS : VXForm_1<270, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vpkshus $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vpkshus VRRC:$vA, VRRC:$vB))]>;
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def VPKSWSS : VXForm_1<462, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vpkswss $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vpkswss VRRC:$vA, VRRC:$vB))]>;
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def VPKSWUS : VXForm_1<334, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vpkswus $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vpkswus VRRC:$vA, VRRC:$vB))]>;
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def VPKPX : VX1_Int<782, "vpkpx", int_ppc_altivec_vpkpx>;
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def VPKSHSS : VX1_Int<398, "vpkshss", int_ppc_altivec_vpkshss>;
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def VPKSHUS : VX1_Int<270, "vpkshus", int_ppc_altivec_vpkshus>;
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def VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>;
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def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>;
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def VPKUHUM : VXForm_1<14, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vpkuhum $vD, $vA, $vB", VecFP,
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[/*TODO*/]>;
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def VPKUHUS : VXForm_1<142, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vpkuhus $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vpkuhus VRRC:$vA, VRRC:$vB))]>;
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def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>;
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def VPKUWUM : VXForm_1<78, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vpkuwum $vD, $vA, $vB", VecFP,
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[/*TODO*/]>;
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def VPKUWUS : VXForm_1<206, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
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"vpkuwus $vD, $vA, $vB", VecFP,
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[(set VRRC:$vD,
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(int_ppc_altivec_vpkuwus VRRC:$vA, VRRC:$vB))]>;
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def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>;
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// Vector Unpack.
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def VUPKHPX : VXForm_2<846, (ops VRRC:$vD, VRRC:$vB),
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