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Completely eliminate the per-machine-instruction regsUsed set.

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This substantially shrinks the size of each machine instruction, which should
make allocation faster and the cache footprint of the machine code lighter.

Here are some timings for code generation of the larger benchmarks we have.
This are timings of code generation phases of the X86 JIT, when compiled in
debug mode:

		Before	After	Diff
164.gzip:
  InstSel	0.0878	0.0722	-21.6%
  RegAlloc	0.2031	0.1757	-15.6%
  TOTAL		0.5585	0.4999	-11.7%
Ptrdist-bc:
  InstSel	0.0878	0.0722	-21.6%
  RegAlloc	0.2070	0.1933	- 7.1%
  TOTAL		0.6972	0.6464	- 7.9%
197.parser:
  InstSel	0.2148	0.2148	- 0.0%
  RegAlloc	0.4941	0.4277	-15.5%
  TOTAL		1.3749	1.2851	- 7.0%
175.vpr:
  InstSel	0.2519	0.2109	-19.4%
  RegAlloc	0.5976	0.5663	- 5.5%
  TOTAL		1.6933	1.6347	- 3.5%
254.gap:
  InstSel	1.1328	0.9921	-14.2%
  RegAlloc	2.6933	2.4804	- 8.6%
  TOTAL		7.7871	7.2499	- 7.4%

llvm-svn: 7622
This commit is contained in:
Chris Lattner 2003-08-05 22:39:13 +00:00
parent 5a778ec126
commit 138a3fc9ab
1 changed files with 0 additions and 15 deletions
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15
include/llvm/CodeGen/MachineInstr.h
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@ -346,10 +346,6 @@ class MachineInstr {
std::vector<MachineOperand> operands; // the operands
unsigned numImplicitRefs; // number of implicit operands
// regsUsed - all machine registers used for this instruction, including regs
// used to save values across the instruction. This is a bitset of registers.
std::set<int> regsUsed;
// OperandComplete - Return true if it's illegal to add a new operand
bool OperandsComplete() const;
@ -438,17 +434,6 @@ public:
MachineOperand::MO_VirtualRegister, V);
}
//
// Information about registers used in this instruction.
//
const std::set<int> &getRegsUsed() const {
return regsUsed;
}
void insertUsedReg(unsigned Reg) {
assert(((int) Reg) >= 0 && "Invalid register being marked as used");
regsUsed.insert((int) Reg);
}
//
// Debugging support
//