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The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset.
Remove the offending logic and update the test cases. llvm-svn: 127843
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@ -962,11 +962,7 @@ static bool DisassembleThumb1Br(MCInst &MI, unsigned Opcode, uint32_t insn,
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unsigned Imm11 = getT1Imm11(insn);
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// When executing a Thumb instruction, PC reads as the address of the current
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// instruction plus 4. The assembler subtracts 4 from the difference between
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// the branch instruction and the target address, disassembler has to add 4 to
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// to compensate.
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MI.addOperand(MCOperand::CreateImm(SignExtend32<12>(Imm11 << 1) + 4));
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MI.addOperand(MCOperand::CreateImm(SignExtend32<12>(Imm11 << 1)));
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NumOpsAdded = 1;
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@ -1747,11 +1743,7 @@ static bool DisassembleThumb2BrMiscCtrl(MCInst &MI, unsigned Opcode,
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Offset = decodeImm32_BLX(insn);
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break;
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}
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// When executing a Thumb instruction, PC reads as the address of the current
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// instruction plus 4. The assembler subtracts 4 from the difference between
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// the branch instruction and the target address, disassembler has to add 4 to
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// to compensate.
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MI.addOperand(MCOperand::CreateImm(Offset + 4));
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MI.addOperand(MCOperand::CreateImm(Offset));
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// This is an increment as some predicate operands may have been added first.
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NumOpsAdded += 1;
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@ -6,10 +6,10 @@
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# CHECK: adcs r0, r0, #1
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0x50 0xf1 0x01 0x00
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# CHECK: b #34
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# CHECK: b #30
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0x0f 0xe0
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# CHECK: b.w #-12
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# CHECK: b.w #-16
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0xff 0xf7 0xf8 0xaf
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# CHECK: bfi r2, r10, #0, #1
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@ -128,5 +128,5 @@
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# CHECK: msr cpsr_fc, r0
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0x80 0xf3 0x00 0x89
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# CHECK: blx #0
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# CHECK: blx #-4
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0xff 0xf7 0xfe 0xef
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