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Change -prefer-32bit-thumb to attribute -mattr=+32bit instead to disable more 32-bit to 16-bit optimizations.
llvm-svn: 110584
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6a92e01d05
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@ -65,6 +65,9 @@ def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
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"true",
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"true",
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"Use NEON for single precision FP">;
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"Use NEON for single precision FP">;
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// Disable 32-bit to 16-bit narrowing for experimentation.
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def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
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"Prefer 32-bit Thumb instrs">;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// ARM Processors supported.
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// ARM Processors supported.
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@ -357,7 +357,7 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &MF) {
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}
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}
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// Shrink 32-bit Thumb2 branch, load, and store instructions.
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// Shrink 32-bit Thumb2 branch, load, and store instructions.
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if (isThumb2)
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if (isThumb2 && !STI->prefers32BitThumb())
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MadeChange |= OptimizeThumb2Instructions(MF);
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MadeChange |= OptimizeThumb2Instructions(MF);
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// After a while, this might be made debug-only, but it is not expensive.
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// After a while, this might be made debug-only, but it is not expensive.
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@ -84,6 +84,10 @@ protected:
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/// instructions.
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/// instructions.
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bool HasT2ExtractPack;
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bool HasT2ExtractPack;
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/// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
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/// over 16-bit ones.
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bool Pref32BitThumb;
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/// stackAlignment - The minimum alignment known to hold of the stack frame on
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/// stackAlignment - The minimum alignment known to hold of the stack frame on
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/// entry to the function and which must be maintained by every function.
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/// entry to the function and which must be maintained by every function.
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unsigned stackAlignment;
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unsigned stackAlignment;
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@ -137,6 +141,7 @@ protected:
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bool hasT2ExtractPack() const { return HasT2ExtractPack; }
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bool hasT2ExtractPack() const { return HasT2ExtractPack; }
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bool useVMLx() const {return hasVFP2() && !SlowVMLx; }
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bool useVMLx() const {return hasVFP2() && !SlowVMLx; }
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bool isFPBrccSlow() const { return SlowFPBrcc; }
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bool isFPBrccSlow() const { return SlowFPBrcc; }
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bool prefers32BitThumb() const { return Pref32BitThumb; }
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bool hasFP16() const { return HasFP16; }
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bool hasFP16() const { return HasFP16; }
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@ -16,17 +16,11 @@
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#include "ARM.h"
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#include "ARM.h"
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#include "llvm/PassManager.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/Target/TargetRegistry.h"
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using namespace llvm;
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using namespace llvm;
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static cl::opt<bool>
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Prefer32BitThumbInstrs("prefer-32bit-thumb",
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cl::desc("Prefer 32-bit Thumb instructions"),
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cl::init(false));
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static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
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static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
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Triple TheTriple(TT);
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Triple TheTriple(TT);
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switch (TheTriple.getOS()) {
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switch (TheTriple.getOS()) {
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@ -143,7 +137,7 @@ bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
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bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
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bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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CodeGenOpt::Level OptLevel) {
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if (!Prefer32BitThumbInstrs && Subtarget.isThumb2())
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if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
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PM.add(createThumb2SizeReductionPass());
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PM.add(createThumb2SizeReductionPass());
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PM.add(createARMConstantIslandPass());
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PM.add(createARMConstantIslandPass());
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