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[x86] promote 'add nsw' to a wider type to allow more combines
The motivation for this patch starts with PR20134: https://llvm.org/bugs/show_bug.cgi?id=20134 void foo(int *a, int i) { a[i] = a[i+1] + a[i+2]; } It seems better to produce this (14 bytes): movslq %esi, %rsi movl 0x4(%rdi,%rsi,4), %eax addl 0x8(%rdi,%rsi,4), %eax movl %eax, (%rdi,%rsi,4) Rather than this (22 bytes): leal 0x1(%rsi), %eax cltq leal 0x2(%rsi), %ecx movslq %ecx, %rcx movl (%rdi,%rcx,4), %ecx addl (%rdi,%rax,4), %ecx movslq %esi, %rax movl %ecx, (%rdi,%rax,4) The most basic problem (the first test case in the patch combines constants) should also be fixed in InstCombine, but it gets more complicated after that because we need to consider architecture and micro-architecture. For example, AArch64 may not see any benefit from the more general transform because the ISA solves the sexting in hardware. Some x86 chips may not want to replace 2 ADD insts with 1 LEA, and there's an attribute for that: FeatureSlowLEA. But I suspect that doesn't go far enough or maybe it's not getting used when it should; I'm also not sure if FeatureSlowLEA should also mean "slow complex addressing mode". I see no perf differences on test-suite with this change running on AMD Jaguar, but I see small code size improvements when building clang and the LLVM tools with the patched compiler. A more general solution to the sext(add nsw(x, C)) problem that works for multiple targets is available in CodeGenPrepare, but it may take quite a bit more work to get that to fire on all of the test cases that this patch takes care of. Differential Revision: http://reviews.llvm.org/D13757 llvm-svn: 250560
This commit is contained in:
Sanjay Patel
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ba1f8ebc88
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16d66c3d22
@ -25767,6 +25767,57 @@ static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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/// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
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/// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
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/// to combine math ops, use an LEA, or use a complex addressing mode. This can
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/// eliminate extend, add, and shift instructions.
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static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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// TODO: This should be valid for other integer types.
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EVT VT = Sext->getValueType(0);
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if (VT != MVT::i64)
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return SDValue();
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// We need an 'add nsw' feeding into the 'sext'.
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SDValue Add = Sext->getOperand(0);
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if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
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return SDValue();
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// Having a constant operand to the 'add' ensures that we are not increasing
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// the instruction count because the constant is extended for free below.
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// A constant operand can also become the displacement field of an LEA.
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auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
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if (!AddOp1)
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return SDValue();
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// Don't make the 'add' bigger if there's no hope of combining it with some
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// other 'add' or 'shl' instruction.
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// TODO: It may be profitable to generate simpler LEA instructions in place
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// of single 'add' instructions, but the cost model for selecting an LEA
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// currently has a high threshold.
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bool HasLEAPotential = false;
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for (auto *User : Sext->uses()) {
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if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
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HasLEAPotential = true;
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break;
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}
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}
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if (!HasLEAPotential)
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return SDValue();
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// Everything looks good, so pull the 'sext' ahead of the 'add'.
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int64_t AddConstant = AddOp1->getSExtValue();
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SDValue AddOp0 = Add.getOperand(0);
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SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);
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SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
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// The wider add is guaranteed to not wrap because both operands are
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// sign-extended.
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SDNodeFlags Flags;
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Flags.setNoSignedWrap(true);
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return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
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}
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static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget *Subtarget) {
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@ -25861,6 +25912,9 @@ static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
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if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
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return R;
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if (SDValue NewAdd = promoteSextBeforeAddNSW(N, DAG, Subtarget))
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return NewAdd;
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return SDValue();
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}
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@ -1,15 +1,14 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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; The fundamental problem: an add separated from other arithmetic by a sext can't
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; be combined with the later instructions. However, if the first add is 'nsw',
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; be combined with the later instructions. However, if the first add is 'nsw',
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; then we can promote the sext ahead of that add to allow optimizations.
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define i64 @add_nsw_consts(i32 %i) {
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; CHECK-LABEL: add_nsw_consts:
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; CHECK: # BB#0:
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; CHECK-NEXT: addl $5, %edi
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; CHECK-NEXT: movslq %edi, %rax
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; CHECK-NEXT: addq $7, %rax
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; CHECK-NEXT: addq $12, %rax
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; CHECK-NEXT: retq
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%add = add nsw i32 %i, 5
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@ -24,9 +23,8 @@ define i64 @add_nsw_consts(i32 %i) {
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define i64 @add_nsw_sext_add(i32 %i, i64 %x) {
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; CHECK-LABEL: add_nsw_sext_add:
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; CHECK: # BB#0:
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; CHECK-NEXT: addl $5, %edi
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; CHECK-NEXT: movslq %edi, %rax
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; CHECK-NEXT: addq %rsi, %rax
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; CHECK-NEXT: leaq 5(%rax,%rsi), %rax
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; CHECK-NEXT: retq
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%add = add nsw i32 %i, 5
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@ -41,9 +39,8 @@ define i64 @add_nsw_sext_add(i32 %i, i64 %x) {
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define i64 @add_nsw_sext_lsh_add(i32 %i, i64 %x) {
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; CHECK-LABEL: add_nsw_sext_lsh_add:
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; CHECK: # BB#0:
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; CHECK-NEXT: addl $-5, %edi
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; CHECK-NEXT: movslq %edi, %rax
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; CHECK-NEXT: leaq (%rsi,%rax,8), %rax
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; CHECK-NEXT: leaq -40(%rsi,%rax,8), %rax
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; CHECK-NEXT: retq
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%add = add nsw i32 %i, -5
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@ -73,9 +70,8 @@ define i64 @add_nsw_sext(i32 %i, i64 %x) {
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define i8* @gep8(i32 %i, i8* %x) {
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; CHECK-LABEL: gep8:
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; CHECK: # BB#0:
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; CHECK-NEXT: addl $5, %edi
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; CHECK-NEXT: movslq %edi, %rax
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; CHECK-NEXT: addq %rsi, %rax
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; CHECK-NEXT: leaq 5(%rax,%rsi), %rax
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; CHECK-NEXT: retq
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%add = add nsw i32 %i, 5
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@ -87,9 +83,8 @@ define i8* @gep8(i32 %i, i8* %x) {
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define i16* @gep16(i32 %i, i16* %x) {
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; CHECK-LABEL: gep16:
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; CHECK: # BB#0:
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; CHECK-NEXT: addl $-5, %edi
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; CHECK-NEXT: movslq %edi, %rax
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; CHECK-NEXT: leaq (%rsi,%rax,2), %rax
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; CHECK-NEXT: leaq -10(%rsi,%rax,2), %rax
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; CHECK-NEXT: retq
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%add = add nsw i32 %i, -5
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@ -101,9 +96,8 @@ define i16* @gep16(i32 %i, i16* %x) {
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define i32* @gep32(i32 %i, i32* %x) {
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; CHECK-LABEL: gep32:
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; CHECK: # BB#0:
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; CHECK-NEXT: addl $5, %edi
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; CHECK-NEXT: movslq %edi, %rax
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; CHECK-NEXT: leaq (%rsi,%rax,4), %rax
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; CHECK-NEXT: leaq 20(%rsi,%rax,4), %rax
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; CHECK-NEXT: retq
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%add = add nsw i32 %i, 5
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@ -115,9 +109,8 @@ define i32* @gep32(i32 %i, i32* %x) {
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define i64* @gep64(i32 %i, i64* %x) {
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; CHECK-LABEL: gep64:
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; CHECK: # BB#0:
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; CHECK-NEXT: addl $-5, %edi
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; CHECK-NEXT: movslq %edi, %rax
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; CHECK-NEXT: leaq (%rsi,%rax,8), %rax
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; CHECK-NEXT: leaq -40(%rsi,%rax,8), %rax
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; CHECK-NEXT: retq
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%add = add nsw i32 %i, -5
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@ -131,10 +124,9 @@ define i64* @gep64(i32 %i, i64* %x) {
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define i128* @gep128(i32 %i, i128* %x) {
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; CHECK-LABEL: gep128:
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; CHECK: # BB#0:
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; CHECK-NEXT: addl $5, %edi
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; CHECK-NEXT: movslq %edi, %rax
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; CHECK-NEXT: shlq $4, %rax
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; CHECK-NEXT: addq %rsi, %rax
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; CHECK-NEXT: leaq 80(%rax,%rsi), %rax
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; CHECK-NEXT: retq
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%add = add nsw i32 %i, 5
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@ -150,14 +142,10 @@ define i128* @gep128(i32 %i, i128* %x) {
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define void @PR20134(i32* %a, i32 %i) {
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; CHECK-LABEL: PR20134:
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; CHECK: # BB#0:
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; CHECK-NEXT: leal 1(%rsi), %eax
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; CHECK-NEXT: cltq
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; CHECK-NEXT: movl (%rdi,%rax,4), %eax
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; CHECK-NEXT: leal 2(%rsi), %ecx
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; CHECK-NEXT: movslq %ecx, %rcx
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; CHECK-NEXT: addl (%rdi,%rcx,4), %eax
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; CHECK-NEXT: movslq %esi, %rcx
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; CHECK-NEXT: movl %eax, (%rdi,%rcx,4)
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; CHECK-NEXT: movslq %esi, %rax
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; CHECK-NEXT: movl 4(%rdi,%rax,4), %ecx
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; CHECK-NEXT: addl 8(%rdi,%rax,4), %ecx
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; CHECK-NEXT: movl %ecx, (%rdi,%rax,4)
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; CHECK-NEXT: retq
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%add1 = add nsw i32 %i, 1
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