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When lowering an inreg sext first shift left, then right arithmetically.

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Shifting right two times will only yield zero. Should fix
SingleSource/UnitTests/SignlessTypes/factor.

llvm-svn: 172322
This commit is contained in:
Benjamin Kramer 2013-01-12 19:06:44 +00:00
parent 3769319e91
commit 17f2252b33
2 changed files with 6 additions and 6 deletions
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6
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
View File

@ -508,9 +508,9 @@ SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
EVT VT = Op.getValueType();
// Make sure that the SRA and SRL instructions are available.
// Make sure that the SRA and SHL instructions are available.
if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
return DAG.UnrollVectorOp(Op.getNode());
DebugLoc DL = Op.getDebugLoc();
@ -521,7 +521,7 @@ SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
SDValue ShiftSz = DAG.getConstant(BW - OrigBW, VT);
Op = Op.getOperand(0);
Op = DAG.getNode(ISD::SRL, DL, VT, Op, ShiftSz);
Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
}

6
test/CodeGen/PowerPC/vec_extload.ll
View File

@ -15,7 +15,7 @@ define <16 x i8> @v16si8_sext_in_reg(<16 x i8> %a) {
ret <16 x i8> %c
}
; CHECK: v16si8_sext_in_reg:
; CHECK: vsrb
; CHECK: vslb
; CHECK: vsrab
; CHECK: blr
@ -37,7 +37,7 @@ define <8 x i16> @v8si16_sext_in_reg(<8 x i16> %a) {
ret <8 x i16> %c
}
; CHECK: v8si16_sext_in_reg:
; CHECK: vsrh
; CHECK: vslh
; CHECK: vsrah
; CHECK: blr
@ -61,7 +61,7 @@ define <4 x i32> @v4si32_sext_in_reg(<4 x i32> %a) {
ret <4 x i32> %c
}
; CHECK: v4si32_sext_in_reg:
; CHECK: vsrw
; CHECK: vslw
; CHECK: vsraw
; CHECK: blr