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Fix Incorrect CHECK message [0-31]+ in test case.

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In regular expression, [0-31]+ equals to [0-3]+, not the number from
0 to 31. So change it to [0-9]+.

llvm-svn: 197113
This commit is contained in:
Kevin Qin 2013-12-12 02:19:13 +00:00
parent f648b7ec82
commit 18b9563375
16 changed files with 323 additions and 323 deletions
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40
test/CodeGen/AArch64/neon-add-sub.ll
View File

@ -1,119 +1,119 @@
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
define <8 x i8> @add8xi8(<8 x i8> %A, <8 x i8> %B) {
;CHECK: add {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: add {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp3 = add <8 x i8> %A, %B;
ret <8 x i8> %tmp3
}
define <16 x i8> @add16xi8(<16 x i8> %A, <16 x i8> %B) {
;CHECK: add {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: add {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp3 = add <16 x i8> %A, %B;
ret <16 x i8> %tmp3
}
define <4 x i16> @add4xi16(<4 x i16> %A, <4 x i16> %B) {
;CHECK: add {{v[0-31]+}}.4h, {{v[0-31]+}}.4h, {{v[0-31]+}}.4h
;CHECK: add {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
%tmp3 = add <4 x i16> %A, %B;
ret <4 x i16> %tmp3
}
define <8 x i16> @add8xi16(<8 x i16> %A, <8 x i16> %B) {
;CHECK: add {{v[0-31]+}}.8h, {{v[0-31]+}}.8h, {{v[0-31]+}}.8h
;CHECK: add {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
%tmp3 = add <8 x i16> %A, %B;
ret <8 x i16> %tmp3
}
define <2 x i32> @add2xi32(<2 x i32> %A, <2 x i32> %B) {
;CHECK: add {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
;CHECK: add {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
%tmp3 = add <2 x i32> %A, %B;
ret <2 x i32> %tmp3
}
define <4 x i32> @add4x32(<4 x i32> %A, <4 x i32> %B) {
;CHECK: add {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
;CHECK: add {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
%tmp3 = add <4 x i32> %A, %B;
ret <4 x i32> %tmp3
}
define <2 x i64> @add2xi64(<2 x i64> %A, <2 x i64> %B) {
;CHECK: add {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
;CHECK: add {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
%tmp3 = add <2 x i64> %A, %B;
ret <2 x i64> %tmp3
}
define <2 x float> @add2xfloat(<2 x float> %A, <2 x float> %B) {
;CHECK: fadd {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
;CHECK: fadd {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
%tmp3 = fadd <2 x float> %A, %B;
ret <2 x float> %tmp3
}
define <4 x float> @add4xfloat(<4 x float> %A, <4 x float> %B) {
;CHECK: fadd {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
;CHECK: fadd {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
%tmp3 = fadd <4 x float> %A, %B;
ret <4 x float> %tmp3
}
define <2 x double> @add2xdouble(<2 x double> %A, <2 x double> %B) {
;CHECK: add {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
;CHECK: add {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
%tmp3 = fadd <2 x double> %A, %B;
ret <2 x double> %tmp3
}
define <8 x i8> @sub8xi8(<8 x i8> %A, <8 x i8> %B) {
;CHECK: sub {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: sub {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp3 = sub <8 x i8> %A, %B;
ret <8 x i8> %tmp3
}
define <16 x i8> @sub16xi8(<16 x i8> %A, <16 x i8> %B) {
;CHECK: sub {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: sub {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp3 = sub <16 x i8> %A, %B;
ret <16 x i8> %tmp3
}
define <4 x i16> @sub4xi16(<4 x i16> %A, <4 x i16> %B) {
;CHECK: sub {{v[0-31]+}}.4h, {{v[0-31]+}}.4h, {{v[0-31]+}}.4h
;CHECK: sub {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
%tmp3 = sub <4 x i16> %A, %B;
ret <4 x i16> %tmp3
}
define <8 x i16> @sub8xi16(<8 x i16> %A, <8 x i16> %B) {
;CHECK: sub {{v[0-31]+}}.8h, {{v[0-31]+}}.8h, {{v[0-31]+}}.8h
;CHECK: sub {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
%tmp3 = sub <8 x i16> %A, %B;
ret <8 x i16> %tmp3
}
define <2 x i32> @sub2xi32(<2 x i32> %A, <2 x i32> %B) {
;CHECK: sub {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
;CHECK: sub {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
%tmp3 = sub <2 x i32> %A, %B;
ret <2 x i32> %tmp3
}
define <4 x i32> @sub4x32(<4 x i32> %A, <4 x i32> %B) {
;CHECK: sub {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
;CHECK: sub {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
%tmp3 = sub <4 x i32> %A, %B;
ret <4 x i32> %tmp3
}
define <2 x i64> @sub2xi64(<2 x i64> %A, <2 x i64> %B) {
;CHECK: sub {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
;CHECK: sub {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
%tmp3 = sub <2 x i64> %A, %B;
ret <2 x i64> %tmp3
}
define <2 x float> @sub2xfloat(<2 x float> %A, <2 x float> %B) {
;CHECK: fsub {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
;CHECK: fsub {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
%tmp3 = fsub <2 x float> %A, %B;
ret <2 x float> %tmp3
}
define <4 x float> @sub4xfloat(<4 x float> %A, <4 x float> %B) {
;CHECK: fsub {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
;CHECK: fsub {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
%tmp3 = fsub <4 x float> %A, %B;
ret <4 x float> %tmp3
}
define <2 x double> @sub2xdouble(<2 x double> %A, <2 x double> %B) {
;CHECK: sub {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
;CHECK: sub {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
%tmp3 = fsub <2 x double> %A, %B;
ret <2 x double> %tmp3
}

176
test/CodeGen/AArch64/neon-bitwise-instructions.ll
View File

@ -2,45 +2,45 @@
define <8 x i8> @and8xi8(<8 x i8> %a, <8 x i8> %b) {
;CHECK: and {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = and <8 x i8> %a, %b;
ret <8 x i8> %tmp1
}
define <16 x i8> @and16xi8(<16 x i8> %a, <16 x i8> %b) {
;CHECK: and {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = and <16 x i8> %a, %b;
ret <16 x i8> %tmp1
}
define <8 x i8> @orr8xi8(<8 x i8> %a, <8 x i8> %b) {
;CHECK: orr {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = or <8 x i8> %a, %b;
ret <8 x i8> %tmp1
}
define <16 x i8> @orr16xi8(<16 x i8> %a, <16 x i8> %b) {
;CHECK: orr {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = or <16 x i8> %a, %b;
ret <16 x i8> %tmp1
}
define <8 x i8> @xor8xi8(<8 x i8> %a, <8 x i8> %b) {
;CHECK: eor {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = xor <8 x i8> %a, %b;
ret <8 x i8> %tmp1
}
define <16 x i8> @xor16xi8(<16 x i8> %a, <16 x i8> %b) {
;CHECK: eor {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = xor <16 x i8> %a, %b;
ret <16 x i8> %tmp1
}
define <8 x i8> @bsl8xi8_const(<8 x i8> %a, <8 x i8> %b) {
;CHECK: bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = and <8 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
%tmp2 = and <8 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0 >
%tmp3 = or <8 x i8> %tmp1, %tmp2
@ -48,7 +48,7 @@ define <8 x i8> @bsl8xi8_const(<8 x i8> %a, <8 x i8> %b) {
}
define <16 x i8> @bsl16xi8_const(<16 x i8> %a, <16 x i8> %b) {
;CHECK: bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = and <16 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
%tmp2 = and <16 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0 >
%tmp3 = or <16 x i8> %tmp1, %tmp2
@ -56,397 +56,397 @@ define <16 x i8> @bsl16xi8_const(<16 x i8> %a, <16 x i8> %b) {
}
define <8 x i8> @orn8xi8(<8 x i8> %a, <8 x i8> %b) {
;CHECK: orn {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
%tmp2 = or <8 x i8> %a, %tmp1
ret <8 x i8> %tmp2
}
define <16 x i8> @orn16xi8(<16 x i8> %a, <16 x i8> %b) {
;CHECK: orn {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
%tmp2 = or <16 x i8> %a, %tmp1
ret <16 x i8> %tmp2
}
define <8 x i8> @bic8xi8(<8 x i8> %a, <8 x i8> %b) {
;CHECK: bic {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
%tmp2 = and <8 x i8> %a, %tmp1
ret <8 x i8> %tmp2
}
define <16 x i8> @bic16xi8(<16 x i8> %a, <16 x i8> %b) {
;CHECK: bic {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
%tmp2 = and <16 x i8> %a, %tmp1
ret <16 x i8> %tmp2
}
define <2 x i32> @orrimm2s_lsl0(<2 x i32> %a) {
;CHECK: orr {{v[0-31]+}}.2s, #0xff
;CHECK: orr {{v[0-9]+}}.2s, #0xff
%tmp1 = or <2 x i32> %a, < i32 255, i32 255>
ret <2 x i32> %tmp1
}
define <2 x i32> @orrimm2s_lsl8(<2 x i32> %a) {
;CHECK: orr {{v[0-31]+}}.2s, #0xff, lsl #8
;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #8
%tmp1 = or <2 x i32> %a, < i32 65280, i32 65280>
ret <2 x i32> %tmp1
}
define <2 x i32> @orrimm2s_lsl16(<2 x i32> %a) {
;CHECK: orr {{v[0-31]+}}.2s, #0xff, lsl #16
;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #16
%tmp1 = or <2 x i32> %a, < i32 16711680, i32 16711680>
ret <2 x i32> %tmp1
}
define <2 x i32> @orrimm2s_lsl24(<2 x i32> %a) {
;CHECK: orr {{v[0-31]+}}.2s, #0xff, lsl #24
;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #24
%tmp1 = or <2 x i32> %a, < i32 4278190080, i32 4278190080>
ret <2 x i32> %tmp1
}
define <4 x i32> @orrimm4s_lsl0(<4 x i32> %a) {
;CHECK: orr {{v[0-31]+}}.4s, #0xff
;CHECK: orr {{v[0-9]+}}.4s, #0xff
%tmp1 = or <4 x i32> %a, < i32 255, i32 255, i32 255, i32 255>
ret <4 x i32> %tmp1
}
define <4 x i32> @orrimm4s_lsl8(<4 x i32> %a) {
;CHECK: orr {{v[0-31]+}}.4s, #0xff, lsl #8
;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #8
%tmp1 = or <4 x i32> %a, < i32 65280, i32 65280, i32 65280, i32 65280>
ret <4 x i32> %tmp1
}
define <4 x i32> @orrimm4s_lsl16(<4 x i32> %a) {
;CHECK: orr {{v[0-31]+}}.4s, #0xff, lsl #16
;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #16
%tmp1 = or <4 x i32> %a, < i32 16711680, i32 16711680, i32 16711680, i32 16711680>
ret <4 x i32> %tmp1
}
define <4 x i32> @orrimm4s_lsl24(<4 x i32> %a) {
;CHECK: orr {{v[0-31]+}}.4s, #0xff, lsl #24
;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #24
%tmp1 = or <4 x i32> %a, < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080>
ret <4 x i32> %tmp1
}
define <4 x i16> @orrimm4h_lsl0(<4 x i16> %a) {
;CHECK: orr {{v[0-31]+}}.4h, #0xff
;CHECK: orr {{v[0-9]+}}.4h, #0xff
%tmp1 = or <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255 >
ret <4 x i16> %tmp1
}
define <4 x i16> @orrimm4h_lsl8(<4 x i16> %a) {
;CHECK: orr {{v[0-31]+}}.4h, #0xff, lsl #8
;CHECK: orr {{v[0-9]+}}.4h, #0xff, lsl #8
%tmp1 = or <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
ret <4 x i16> %tmp1
}
define <8 x i16> @orrimm8h_lsl0(<8 x i16> %a) {
;CHECK: orr {{v[0-31]+}}.8h, #0xff
;CHECK: orr {{v[0-9]+}}.8h, #0xff
%tmp1 = or <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
ret <8 x i16> %tmp1
}
define <8 x i16> @orrimm8h_lsl8(<8 x i16> %a) {
;CHECK: orr {{v[0-31]+}}.8h, #0xff, lsl #8
;CHECK: orr {{v[0-9]+}}.8h, #0xff, lsl #8
%tmp1 = or <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
ret <8 x i16> %tmp1
}
define <2 x i32> @bicimm2s_lsl0(<2 x i32> %a) {
;CHECK: bic {{v[0-31]+}}.2s, #0x10
;CHECK: bic {{v[0-9]+}}.2s, #0x10
%tmp1 = and <2 x i32> %a, < i32 4294967279, i32 4294967279 >
ret <2 x i32> %tmp1
}
define <2 x i32> @bicimm2s_lsl8(<2 x i32> %a) {
;CHECK: bic {{v[0-31]+}}.2s, #0x10, lsl #8
;CHECK: bic {{v[0-9]+}}.2s, #0x10, lsl #8
%tmp1 = and <2 x i32> %a, < i32 18446744073709547519, i32 18446744073709547519 >
ret <2 x i32> %tmp1
}
define <2 x i32> @bicimm2s_lsl16(<2 x i32> %a) {
;CHECK: bic {{v[0-31]+}}.2s, #0x10, lsl #16
;CHECK: bic {{v[0-9]+}}.2s, #0x10, lsl #16
%tmp1 = and <2 x i32> %a, < i32 18446744073708503039, i32 18446744073708503039 >
ret <2 x i32> %tmp1
}
define <2 x i32> @bicimm2s_lsl124(<2 x i32> %a) {
;CHECK: bic {{v[0-31]+}}.2s, #0x10, lsl #24
;CHECK: bic {{v[0-9]+}}.2s, #0x10, lsl #24
%tmp1 = and <2 x i32> %a, < i32 18446744073441116159, i32 18446744073441116159>
ret <2 x i32> %tmp1
}
define <4 x i32> @bicimm4s_lsl0(<4 x i32> %a) {
;CHECK: bic {{v[0-31]+}}.4s, #0x10
;CHECK: bic {{v[0-9]+}}.4s, #0x10
%tmp1 = and <4 x i32> %a, < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
ret <4 x i32> %tmp1
}
define <4 x i32> @bicimm4s_lsl8(<4 x i32> %a) {
;CHECK: bic {{v[0-31]+}}.4s, #0x10, lsl #8
;CHECK: bic {{v[0-9]+}}.4s, #0x10, lsl #8
%tmp1 = and <4 x i32> %a, < i32 18446744073709547519, i32 18446744073709547519, i32 18446744073709547519, i32 18446744073709547519 >
ret <4 x i32> %tmp1
}
define <4 x i32> @bicimm4s_lsl16(<4 x i32> %a) {
;CHECK: bic {{v[0-31]+}}.4s, #0x10, lsl #16
;CHECK: bic {{v[0-9]+}}.4s, #0x10, lsl #16
%tmp1 = and <4 x i32> %a, < i32 18446744073708503039, i32 18446744073708503039, i32 18446744073708503039, i32 18446744073708503039 >
ret <4 x i32> %tmp1
}
define <4 x i32> @bicimm4s_lsl124(<4 x i32> %a) {
;CHECK: bic {{v[0-31]+}}.4s, #0x10, lsl #24
;CHECK: bic {{v[0-9]+}}.4s, #0x10, lsl #24
%tmp1 = and <4 x i32> %a, < i32 18446744073441116159, i32 18446744073441116159, i32 18446744073441116159, i32 18446744073441116159>
ret <4 x i32> %tmp1
}
define <4 x i16> @bicimm4h_lsl0_a(<4 x i16> %a) {
;CHECK: bic {{v[0-31]+}}.4h, #0x10
;CHECK: bic {{v[0-9]+}}.4h, #0x10
%tmp1 = and <4 x i16> %a, < i16 18446744073709551599, i16 18446744073709551599, i16 18446744073709551599, i16 18446744073709551599 >
ret <4 x i16> %tmp1
}
define <4 x i16> @bicimm4h_lsl0_b(<4 x i16> %a) {
;CHECK: bic {{v[0-31]+}}.4h, #0x0
;CHECK: bic {{v[0-9]+}}.4h, #0x0
%tmp1 = and <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
ret <4 x i16> %tmp1
}
define <4 x i16> @bicimm4h_lsl8_a(<4 x i16> %a) {
;CHECK: bic {{v[0-31]+}}.4h, #0x10, lsl #8
;CHECK: bic {{v[0-9]+}}.4h, #0x10, lsl #8
%tmp1 = and <4 x i16> %a, < i16 18446744073709547519, i16 18446744073709547519, i16 18446744073709547519, i16 18446744073709547519>
ret <4 x i16> %tmp1
}
define <4 x i16> @bicimm4h_lsl8_b(<4 x i16> %a) {
;CHECK: bic {{v[0-31]+}}.4h, #0x0, lsl #8
;CHECK: bic {{v[0-9]+}}.4h, #0x0, lsl #8
%tmp1 = and <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255>
ret <4 x i16> %tmp1
}
define <8 x i16> @bicimm8h_lsl0_a(<8 x i16> %a) {
;CHECK: bic {{v[0-31]+}}.8h, #0x10
;CHECK: bic {{v[0-9]+}}.8h, #0x10
%tmp1 = and <8 x i16> %a, < i16 18446744073709551599, i16 18446744073709551599, i16 18446744073709551599, i16 18446744073709551599,
i16 18446744073709551599, i16 18446744073709551599, i16 18446744073709551599, i16 18446744073709551599 >
ret <8 x i16> %tmp1
}
define <8 x i16> @bicimm8h_lsl0_b(<8 x i16> %a) {
;CHECK: bic {{v[0-31]+}}.8h, #0x0
;CHECK: bic {{v[0-9]+}}.8h, #0x0
%tmp1 = and <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
ret <8 x i16> %tmp1
}
define <8 x i16> @bicimm8h_lsl8_a(<8 x i16> %a) {
;CHECK: bic {{v[0-31]+}}.8h, #0x10, lsl #8
;CHECK: bic {{v[0-9]+}}.8h, #0x10, lsl #8
%tmp1 = and <8 x i16> %a, < i16 18446744073709547519, i16 18446744073709547519, i16 18446744073709547519, i16 18446744073709547519,
i16 18446744073709547519, i16 18446744073709547519, i16 18446744073709547519, i16 18446744073709547519>
ret <8 x i16> %tmp1
}
define <8 x i16> @bicimm8h_lsl8_b(<8 x i16> %a) {
;CHECK: bic {{v[0-31]+}}.8h, #0x0, lsl #8
;CHECK: bic {{v[0-9]+}}.8h, #0x0, lsl #8
%tmp1 = and <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <8 x i16> %tmp1
}
define <2 x i32> @and2xi32(<2 x i32> %a, <2 x i32> %b) {
;CHECK: and {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = and <2 x i32> %a, %b;
ret <2 x i32> %tmp1
}
define <4 x i16> @and4xi16(<4 x i16> %a, <4 x i16> %b) {
;CHECK: and {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = and <4 x i16> %a, %b;
ret <4 x i16> %tmp1
}
define <1 x i64> @and1xi64(<1 x i64> %a, <1 x i64> %b) {
;CHECK: and {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = and <1 x i64> %a, %b;
ret <1 x i64> %tmp1
}
define <4 x i32> @and4xi32(<4 x i32> %a, <4 x i32> %b) {
;CHECK: and {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = and <4 x i32> %a, %b;
ret <4 x i32> %tmp1
}
define <8 x i16> @and8xi16(<8 x i16> %a, <8 x i16> %b) {
;CHECK: and {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = and <8 x i16> %a, %b;
ret <8 x i16> %tmp1
}
define <2 x i64> @and2xi64(<2 x i64> %a, <2 x i64> %b) {
;CHECK: and {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = and <2 x i64> %a, %b;
ret <2 x i64> %tmp1
}
define <2 x i32> @orr2xi32(<2 x i32> %a, <2 x i32> %b) {
;CHECK: orr {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = or <2 x i32> %a, %b;
ret <2 x i32> %tmp1
}
define <4 x i16> @orr4xi16(<4 x i16> %a, <4 x i16> %b) {
;CHECK: orr {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = or <4 x i16> %a, %b;
ret <4 x i16> %tmp1
}
define <1 x i64> @orr1xi64(<1 x i64> %a, <1 x i64> %b) {
;CHECK: orr {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = or <1 x i64> %a, %b;
ret <1 x i64> %tmp1
}
define <4 x i32> @orr4xi32(<4 x i32> %a, <4 x i32> %b) {
;CHECK: orr {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = or <4 x i32> %a, %b;
ret <4 x i32> %tmp1
}
define <8 x i16> @orr8xi16(<8 x i16> %a, <8 x i16> %b) {
;CHECK: orr {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = or <8 x i16> %a, %b;
ret <8 x i16> %tmp1
}
define <2 x i64> @orr2xi64(<2 x i64> %a, <2 x i64> %b) {
;CHECK: orr {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = or <2 x i64> %a, %b;
ret <2 x i64> %tmp1
}
define <2 x i32> @eor2xi32(<2 x i32> %a, <2 x i32> %b) {
;CHECK: eor {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = xor <2 x i32> %a, %b;
ret <2 x i32> %tmp1
}
define <4 x i16> @eor4xi16(<4 x i16> %a, <4 x i16> %b) {
;CHECK: eor {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = xor <4 x i16> %a, %b;
ret <4 x i16> %tmp1
}
define <1 x i64> @eor1xi64(<1 x i64> %a, <1 x i64> %b) {
;CHECK: eor {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = xor <1 x i64> %a, %b;
ret <1 x i64> %tmp1
}
define <4 x i32> @eor4xi32(<4 x i32> %a, <4 x i32> %b) {
;CHECK: eor {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = xor <4 x i32> %a, %b;
ret <4 x i32> %tmp1
}
define <8 x i16> @eor8xi16(<8 x i16> %a, <8 x i16> %b) {
;CHECK: eor {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = xor <8 x i16> %a, %b;
ret <8 x i16> %tmp1
}
define <2 x i64> @eor2xi64(<2 x i64> %a, <2 x i64> %b) {
;CHECK: eor {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = xor <2 x i64> %a, %b;
ret <2 x i64> %tmp1
}
define <2 x i32> @bic2xi32(<2 x i32> %a, <2 x i32> %b) {
;CHECK: bic {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
%tmp2 = and <2 x i32> %a, %tmp1
ret <2 x i32> %tmp2
}
define <4 x i16> @bic4xi16(<4 x i16> %a, <4 x i16> %b) {
;CHECK: bic {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
%tmp2 = and <4 x i16> %a, %tmp1
ret <4 x i16> %tmp2
}
define <1 x i64> @bic1xi64(<1 x i64> %a, <1 x i64> %b) {
;CHECK: bic {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = xor <1 x i64> %b, < i64 -1>
%tmp2 = and <1 x i64> %a, %tmp1
ret <1 x i64> %tmp2
}
define <4 x i32> @bic4xi32(<4 x i32> %a, <4 x i32> %b) {
;CHECK: bic {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
%tmp2 = and <4 x i32> %a, %tmp1
ret <4 x i32> %tmp2
}
define <8 x i16> @bic8xi16(<8 x i16> %a, <8 x i16> %b) {
;CHECK: bic {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
%tmp2 = and <8 x i16> %a, %tmp1
ret <8 x i16> %tmp2
}
define <2 x i64> @bic2xi64(<2 x i64> %a, <2 x i64> %b) {
;CHECK: bic {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
%tmp2 = and <2 x i64> %a, %tmp1
ret <2 x i64> %tmp2
}
define <2 x i32> @orn2xi32(<2 x i32> %a, <2 x i32> %b) {
;CHECK: orn {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
%tmp2 = or <2 x i32> %a, %tmp1
ret <2 x i32> %tmp2
}
define <4 x i16> @orn4xi16(<4 x i16> %a, <4 x i16> %b) {
;CHECK: orn {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
%tmp2 = or <4 x i16> %a, %tmp1
ret <4 x i16> %tmp2
}
define <1 x i64> @orn1xi64(<1 x i64> %a, <1 x i64> %b) {
;CHECK: orn {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = xor <1 x i64> %b, < i64 -1>
%tmp2 = or <1 x i64> %a, %tmp1
ret <1 x i64> %tmp2
}
define <4 x i32> @orn4xi32(<4 x i32> %a, <4 x i32> %b) {
;CHECK: orn {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
%tmp2 = or <4 x i32> %a, %tmp1
ret <4 x i32> %tmp2
}
define <8 x i16> @orn8xi16(<8 x i16> %a, <8 x i16> %b) {
;CHECK: orn {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
%tmp2 = or <8 x i16> %a, %tmp1
ret <8 x i16> %tmp2
}
define <2 x i64> @orn2xi64(<2 x i64> %a, <2 x i64> %b) {
;CHECK: orn {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
%tmp2 = or <2 x i64> %a, %tmp1
ret <2 x i64> %tmp2
}
define <2 x i32> @bsl2xi32_const(<2 x i32> %a, <2 x i32> %b) {
;CHECK: bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = and <2 x i32> %a, < i32 -1, i32 -1 >
%tmp2 = and <2 x i32> %b, < i32 0, i32 0 >
%tmp3 = or <2 x i32> %tmp1, %tmp2
@ -455,7 +455,7 @@ define <2 x i32> @bsl2xi32_const(<2 x i32> %a, <2 x i32> %b) {
define <4 x i16> @bsl4xi16_const(<4 x i16> %a, <4 x i16> %b) {
;CHECK: bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = and <4 x i16> %a, < i16 -1, i16 -1, i16 -1,i16 -1 >
%tmp2 = and <4 x i16> %b, < i16 0, i16 0,i16 0, i16 0 >
%tmp3 = or <4 x i16> %tmp1, %tmp2
@ -463,7 +463,7 @@ define <4 x i16> @bsl4xi16_const(<4 x i16> %a, <4 x i16> %b) {
}
define <1 x i64> @bsl1xi64_const(<1 x i64> %a, <1 x i64> %b) {
;CHECK: bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = and <1 x i64> %a, < i64 -1 >
%tmp2 = and <1 x i64> %b, < i64 0 >
%tmp3 = or <1 x i64> %tmp1, %tmp2
@ -471,7 +471,7 @@ define <1 x i64> @bsl1xi64_const(<1 x i64> %a, <1 x i64> %b) {
}
define <4 x i32> @bsl4xi32_const(<4 x i32> %a, <4 x i32> %b) {
;CHECK: bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = and <4 x i32> %a, < i32 -1, i32 -1, i32 -1, i32 -1 >
%tmp2 = and <4 x i32> %b, < i32 0, i32 0, i32 0, i32 0 >
%tmp3 = or <4 x i32> %tmp1, %tmp2
@ -479,7 +479,7 @@ define <4 x i32> @bsl4xi32_const(<4 x i32> %a, <4 x i32> %b) {
}
define <8 x i16> @bsl8xi16_const(<8 x i16> %a, <8 x i16> %b) {
;CHECK: bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = and <8 x i16> %a, < i16 -1, i16 -1, i16 -1,i16 -1, i16 -1, i16 -1, i16 -1,i16 -1 >
%tmp2 = and <8 x i16> %b, < i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0 >
%tmp3 = or <8 x i16> %tmp1, %tmp2
@ -487,7 +487,7 @@ define <8 x i16> @bsl8xi16_const(<8 x i16> %a, <8 x i16> %b) {
}
define <2 x i64> @bsl2xi64_const(<2 x i64> %a, <2 x i64> %b) {
;CHECK: bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = and <2 x i64> %a, < i64 -1, i64 -1 >
%tmp2 = and <2 x i64> %b, < i64 0, i64 0 >
%tmp3 = or <2 x i64> %tmp1, %tmp2
@ -496,7 +496,7 @@ define <2 x i64> @bsl2xi64_const(<2 x i64> %a, <2 x i64> %b) {
define <8 x i8> @bsl8xi8(<8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) {
;CHECK: bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%1 = and <8 x i8> %v1, %v2
%2 = xor <8 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
%3 = and <8 x i8> %2, %v3
@ -505,7 +505,7 @@ define <8 x i8> @bsl8xi8(<8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) {
}
define <4 x i16> @bsl4xi16(<4 x i16> %v1, <4 x i16> %v2, <4 x i16> %v3) {
;CHECK: bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%1 = and <4 x i16> %v1, %v2
%2 = xor <4 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1>
%3 = and <4 x i16> %2, %v3
@ -514,7 +514,7 @@ define <4 x i16> @bsl4xi16(<4 x i16> %v1, <4 x i16> %v2, <4 x i16> %v3) {
}
define <2 x i32> @bsl2xi32(<2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) {
;CHECK: bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%1 = and <2 x i32> %v1, %v2
%2 = xor <2 x i32> %v1, <i32 -1, i32 -1>
%3 = and <2 x i32> %2, %v3
@ -523,7 +523,7 @@ define <2 x i32> @bsl2xi32(<2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) {
}
define <1 x i64> @bsl1xi64(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) {
;CHECK: bsl {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%1 = and <1 x i64> %v1, %v2
%2 = xor <1 x i64> %v1, <i64 -1>
%3 = and <1 x i64> %2, %v3
@ -532,7 +532,7 @@ define <1 x i64> @bsl1xi64(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) {
}
define <16 x i8> @bsl16xi8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3) {
;CHECK: bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%1 = and <16 x i8> %v1, %v2
%2 = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
%3 = and <16 x i8> %2, %v3
@ -541,7 +541,7 @@ define <16 x i8> @bsl16xi8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3) {
}
define <8 x i16> @bsl8xi16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) {
;CHECK: bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%1 = and <8 x i16> %v1, %v2
%2 = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
%3 = and <8 x i16> %2, %v3
@ -550,7 +550,7 @@ define <8 x i16> @bsl8xi16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) {
}
define <4 x i32> @bsl4xi32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
;CHECK: bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%1 = and <4 x i32> %v1, %v2
%2 = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1>
%3 = and <4 x i32> %2, %v3
@ -559,7 +559,7 @@ define <4 x i32> @bsl4xi32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
}
define <2 x i64> @bsl2xi64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %v3) {
;CHECK: bsl {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%1 = and <2 x i64> %v1, %v2
%2 = xor <2 x i64> %v1, <i64 -1, i64 -1>
%3 = and <2 x i64> %2, %v3
@ -568,25 +568,25 @@ define <2 x i64> @bsl2xi64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %v3) {
}
define <8 x i8> @orrimm8b_as_orrimm4h_lsl0(<8 x i8> %a) {
;CHECK: orr {{v[0-31]+}}.4h, #0xff
;CHECK: orr {{v[0-9]+}}.4h, #0xff
%val = or <8 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
ret <8 x i8> %val
}
define <8 x i8> @orrimm8b_as_orimm4h_lsl8(<8 x i8> %a) {
;CHECK: orr {{v[0-31]+}}.4h, #0xff, lsl #8
;CHECK: orr {{v[0-9]+}}.4h, #0xff, lsl #8
%val = or <8 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
ret <8 x i8> %val
}
define <16 x i8> @orimm16b_as_orrimm8h_lsl0(<16 x i8> %a) {
;CHECK: orr {{v[0-31]+}}.8h, #0xff
;CHECK: orr {{v[0-9]+}}.8h, #0xff
%val = or <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
ret <16 x i8> %val
}
define <16 x i8> @orimm16b_as_orrimm8h_lsl8(<16 x i8> %a) {
;CHECK: orr {{v[0-31]+}}.8h, #0xff, lsl #8
;CHECK: orr {{v[0-9]+}}.8h, #0xff, lsl #8
%val = or <16 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
ret <16 x i8> %val
}

98
test/CodeGen/AArch64/neon-copy.ll
View File

@ -2,269 +2,269 @@
define <16 x i8> @ins16bw(<16 x i8> %tmp1, i8 %tmp2) {
;CHECK: ins {{v[0-31]+}}.b[15], {{w[0-31]+}}
;CHECK: ins {{v[0-9]+}}.b[15], {{w[0-9]+}}
%tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 15
ret <16 x i8> %tmp3
}
define <8 x i16> @ins8hw(<8 x i16> %tmp1, i16 %tmp2) {
;CHECK: ins {{v[0-31]+}}.h[6], {{w[0-31]+}}
;CHECK: ins {{v[0-9]+}}.h[6], {{w[0-9]+}}
%tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 6
ret <8 x i16> %tmp3
}
define <4 x i32> @ins4sw(<4 x i32> %tmp1, i32 %tmp2) {
;CHECK: ins {{v[0-31]+}}.s[2], {{w[0-31]+}}
;CHECK: ins {{v[0-9]+}}.s[2], {{w[0-9]+}}
%tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 2
ret <4 x i32> %tmp3
}
define <2 x i64> @ins2dw(<2 x i64> %tmp1, i64 %tmp2) {
;CHECK: ins {{v[0-31]+}}.d[1], {{x[0-31]+}}
;CHECK: ins {{v[0-9]+}}.d[1], {{x[0-9]+}}
%tmp3 = insertelement <2 x i64> %tmp1, i64 %tmp2, i32 1
ret <2 x i64> %tmp3
}
define <8 x i8> @ins8bw(<8 x i8> %tmp1, i8 %tmp2) {
;CHECK: ins {{v[0-31]+}}.b[5], {{w[0-31]+}}
;CHECK: ins {{v[0-9]+}}.b[5], {{w[0-9]+}}
%tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 5
ret <8 x i8> %tmp3
}
define <4 x i16> @ins4hw(<4 x i16> %tmp1, i16 %tmp2) {
;CHECK: ins {{v[0-31]+}}.h[3], {{w[0-31]+}}
;CHECK: ins {{v[0-9]+}}.h[3], {{w[0-9]+}}
%tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 3
ret <4 x i16> %tmp3
}
define <2 x i32> @ins2sw(<2 x i32> %tmp1, i32 %tmp2) {
;CHECK: ins {{v[0-31]+}}.s[1], {{w[0-31]+}}
;CHECK: ins {{v[0-9]+}}.s[1], {{w[0-9]+}}
%tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1
ret <2 x i32> %tmp3
}
define <16 x i8> @ins16b16(<16 x i8> %tmp1, <16 x i8> %tmp2) {
;CHECK: ins {{v[0-31]+}}.b[15], {{v[0-31]+}}.b[2]
;CHECK: ins {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]
%tmp3 = extractelement <16 x i8> %tmp1, i32 2
%tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15
ret <16 x i8> %tmp4
}
define <8 x i16> @ins8h8(<8 x i16> %tmp1, <8 x i16> %tmp2) {
;CHECK: ins {{v[0-31]+}}.h[7], {{v[0-31]+}}.h[2]
;CHECK: ins {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]
%tmp3 = extractelement <8 x i16> %tmp1, i32 2
%tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7
ret <8 x i16> %tmp4
}
define <4 x i32> @ins4s4(<4 x i32> %tmp1, <4 x i32> %tmp2) {
;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[2]
;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
%tmp3 = extractelement <4 x i32> %tmp1, i32 2
%tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1
ret <4 x i32> %tmp4
}
define <2 x i64> @ins2d2(<2 x i64> %tmp1, <2 x i64> %tmp2) {
;CHECK: ins {{v[0-31]+}}.d[1], {{v[0-31]+}}.d[0]
;CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
%tmp3 = extractelement <2 x i64> %tmp1, i32 0
%tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1
ret <2 x i64> %tmp4
}
define <4 x float> @ins4f4(<4 x float> %tmp1, <4 x float> %tmp2) {
;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[2]
;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
%tmp3 = extractelement <4 x float> %tmp1, i32 2
%tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1
ret <4 x float> %tmp4
}
define <2 x double> @ins2df2(<2 x double> %tmp1, <2 x double> %tmp2) {
;CHECK: ins {{v[0-31]+}}.d[1], {{v[0-31]+}}.d[0]
;CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
%tmp3 = extractelement <2 x double> %tmp1, i32 0
%tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1
ret <2 x double> %tmp4
}
define <16 x i8> @ins8b16(<8 x i8> %tmp1, <16 x i8> %tmp2) {
;CHECK: ins {{v[0-31]+}}.b[15], {{v[0-31]+}}.b[2]
;CHECK: ins {{v[0-9]+}}.b[15], {{v[0-9]+}}.b[2]
%tmp3 = extractelement <8 x i8> %tmp1, i32 2
%tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15
ret <16 x i8> %tmp4
}
define <8 x i16> @ins4h8(<4 x i16> %tmp1, <8 x i16> %tmp2) {
;CHECK: ins {{v[0-31]+}}.h[7], {{v[0-31]+}}.h[2]
;CHECK: ins {{v[0-9]+}}.h[7], {{v[0-9]+}}.h[2]
%tmp3 = extractelement <4 x i16> %tmp1, i32 2
%tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7
ret <8 x i16> %tmp4
}
define <4 x i32> @ins2s4(<2 x i32> %tmp1, <4 x i32> %tmp2) {
;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[1]
;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]
%tmp3 = extractelement <2 x i32> %tmp1, i32 1
%tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1
ret <4 x i32> %tmp4
}
define <2 x i64> @ins1d2(<1 x i64> %tmp1, <2 x i64> %tmp2) {
;CHECK: ins {{v[0-31]+}}.d[1], {{v[0-31]+}}.d[0]
;CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
%tmp3 = extractelement <1 x i64> %tmp1, i32 0
%tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1
ret <2 x i64> %tmp4
}
define <4 x float> @ins2f4(<2 x float> %tmp1, <4 x float> %tmp2) {
;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[1]
;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[1]
%tmp3 = extractelement <2 x float> %tmp1, i32 1
%tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1
ret <4 x float> %tmp4
}
define <2 x double> @ins1f2(<1 x double> %tmp1, <2 x double> %tmp2) {
;CHECK: ins {{v[0-31]+}}.d[1], {{v[0-31]+}}.d[0]
;CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
%tmp3 = extractelement <1 x double> %tmp1, i32 0
%tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1
ret <2 x double> %tmp4
}
define <8 x i8> @ins16b8(<16 x i8> %tmp1, <8 x i8> %tmp2) {
;CHECK: ins {{v[0-31]+}}.b[7], {{v[0-31]+}}.b[2]
;CHECK: ins {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[2]
%tmp3 = extractelement <16 x i8> %tmp1, i32 2
%tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 7
ret <8 x i8> %tmp4
}
define <4 x i16> @ins8h4(<8 x i16> %tmp1, <4 x i16> %tmp2) {
;CHECK: ins {{v[0-31]+}}.h[3], {{v[0-31]+}}.h[2]
;CHECK: ins {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]
%tmp3 = extractelement <8 x i16> %tmp1, i32 2
%tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3
ret <4 x i16> %tmp4
}
define <2 x i32> @ins4s2(<4 x i32> %tmp1, <2 x i32> %tmp2) {
;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[2]
;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
%tmp3 = extractelement <4 x i32> %tmp1, i32 2
%tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1
ret <2 x i32> %tmp4
}
define <1 x i64> @ins2d1(<2 x i64> %tmp1, <1 x i64> %tmp2) {
;CHECK: ins {{v[0-31]+}}.d[0], {{v[0-31]+}}.d[0]
;CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
%tmp3 = extractelement <2 x i64> %tmp1, i32 0
%tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0
ret <1 x i64> %tmp4
}
define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) {
;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[2]
;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[2]
%tmp3 = extractelement <4 x float> %tmp1, i32 2
%tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
ret <2 x float> %tmp4
}
define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) {
;CHECK: ins {{v[0-31]+}}.d[0], {{v[0-31]+}}.d[0]
;CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
%tmp3 = extractelement <2 x double> %tmp1, i32 0
%tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
ret <1 x double> %tmp4
}
define <8 x i8> @ins8b8(<8 x i8> %tmp1, <8 x i8> %tmp2) {
;CHECK: ins {{v[0-31]+}}.b[4], {{v[0-31]+}}.b[2]
;CHECK: ins {{v[0-9]+}}.b[4], {{v[0-9]+}}.b[2]
%tmp3 = extractelement <8 x i8> %tmp1, i32 2
%tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 4
ret <8 x i8> %tmp4
}
define <4 x i16> @ins4h4(<4 x i16> %tmp1, <4 x i16> %tmp2) {
;CHECK: ins {{v[0-31]+}}.h[3], {{v[0-31]+}}.h[2]
;CHECK: ins {{v[0-9]+}}.h[3], {{v[0-9]+}}.h[2]
%tmp3 = extractelement <4 x i16> %tmp1, i32 2
%tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3
ret <4 x i16> %tmp4
}
define <2 x i32> @ins2s2(<2 x i32> %tmp1, <2 x i32> %tmp2) {
;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[0]
;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]
%tmp3 = extractelement <2 x i32> %tmp1, i32 0
%tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1
ret <2 x i32> %tmp4
}
define <1 x i64> @ins1d1(<1 x i64> %tmp1, <1 x i64> %tmp2) {
;CHECK: ins {{v[0-31]+}}.d[0], {{v[0-31]+}}.d[0]
;CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
%tmp3 = extractelement <1 x i64> %tmp1, i32 0
%tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0
ret <1 x i64> %tmp4
}
define <2 x float> @ins2f2(<2 x float> %tmp1, <2 x float> %tmp2) {
;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[0]
;CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0]
%tmp3 = extractelement <2 x float> %tmp1, i32 0
%tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
ret <2 x float> %tmp4
}
define <1 x double> @ins1df1(<1 x double> %tmp1, <1 x double> %tmp2) {
;CHECK: ins {{v[0-31]+}}.d[0], {{v[0-31]+}}.d[0]
;CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[0]
%tmp3 = extractelement <1 x double> %tmp1, i32 0
%tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
ret <1 x double> %tmp4
}
define i32 @umovw16b(<16 x i8> %tmp1) {
;CHECK: umov {{w[0-31]+}}, {{v[0-31]+}}.b[8]
;CHECK: umov {{w[0-9]+}}, {{v[0-9]+}}.b[8]
%tmp3 = extractelement <16 x i8> %tmp1, i32 8
%tmp4 = zext i8 %tmp3 to i32
ret i32 %tmp4
}
define i32 @umovw8h(<8 x i16> %tmp1) {
;CHECK: umov {{w[0-31]+}}, {{v[0-31]+}}.h[2]
;CHECK: umov {{w[0-9]+}}, {{v[0-9]+}}.h[2]
%tmp3 = extractelement <8 x i16> %tmp1, i32 2
%tmp4 = zext i16 %tmp3 to i32
ret i32 %tmp4
}
define i32 @umovw4s(<4 x i32> %tmp1) {
;CHECK: umov {{w[0-31]+}}, {{v[0-31]+}}.s[2]
;CHECK: umov {{w[0-9]+}}, {{v[0-9]+}}.s[2]
%tmp3 = extractelement <4 x i32> %tmp1, i32 2
ret i32 %tmp3
}
define i64 @umovx2d(<2 x i64> %tmp1) {
;CHECK: umov {{x[0-31]+}}, {{v[0-31]+}}.d[0]
;CHECK: umov {{x[0-9]+}}, {{v[0-9]+}}.d[0]
%tmp3 = extractelement <2 x i64> %tmp1, i32 0
ret i64 %tmp3
}
define i32 @umovw8b(<8 x i8> %tmp1) {
;CHECK: umov {{w[0-31]+}}, {{v[0-31]+}}.b[7]
;CHECK: umov {{w[0-9]+}}, {{v[0-9]+}}.b[7]
%tmp3 = extractelement <8 x i8> %tmp1, i32 7
%tmp4 = zext i8 %tmp3 to i32
ret i32 %tmp4
}
define i32 @umovw4h(<4 x i16> %tmp1) {
;CHECK: umov {{w[0-31]+}}, {{v[0-31]+}}.h[2]
;CHECK: umov {{w[0-9]+}}, {{v[0-9]+}}.h[2]
%tmp3 = extractelement <4 x i16> %tmp1, i32 2
%tmp4 = zext i16 %tmp3 to i32
ret i32 %tmp4
}
define i32 @umovw2s(<2 x i32> %tmp1) {
;CHECK: umov {{w[0-31]+}}, {{v[0-31]+}}.s[1]
;CHECK: umov {{w[0-9]+}}, {{v[0-9]+}}.s[1]
%tmp3 = extractelement <2 x i32> %tmp1, i32 1
ret i32 %tmp3
}
define i64 @umovx1d(<1 x i64> %tmp1) {
;CHECK: fmov {{x[0-31]+}}, {{d[0-31]+}}
;CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
%tmp3 = extractelement <1 x i64> %tmp1, i32 0
ret i64 %tmp3
}
define i32 @smovw16b(<16 x i8> %tmp1) {
;CHECK: smov {{w[0-31]+}}, {{v[0-31]+}}.b[8]
;CHECK: smov {{w[0-9]+}}, {{v[0-9]+}}.b[8]
%tmp3 = extractelement <16 x i8> %tmp1, i32 8
%tmp4 = sext i8 %tmp3 to i32
%tmp5 = add i32 5, %tmp4
@ -272,7 +272,7 @@ define i32 @smovw16b(<16 x i8> %tmp1) {
}
define i32 @smovw8h(<8 x i16> %tmp1) {
;CHECK: smov {{w[0-31]+}}, {{v[0-31]+}}.h[2]
;CHECK: smov {{w[0-9]+}}, {{v[0-9]+}}.h[2]
%tmp3 = extractelement <8 x i16> %tmp1, i32 2
%tmp4 = sext i16 %tmp3 to i32
%tmp5 = add i32 5, %tmp4
@ -280,28 +280,28 @@ define i32 @smovw8h(<8 x i16> %tmp1) {
}
define i32 @smovx16b(<16 x i8> %tmp1) {
;CHECK: smov {{x[0-31]+}}, {{v[0-31]+}}.b[8]
;CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.b[8]
%tmp3 = extractelement <16 x i8> %tmp1, i32 8
%tmp4 = sext i8 %tmp3 to i32
ret i32 %tmp4
}
define i32 @smovx8h(<8 x i16> %tmp1) {
;CHECK: smov {{x[0-31]+}}, {{v[0-31]+}}.h[2]
;CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.h[2]
%tmp3 = extractelement <8 x i16> %tmp1, i32 2
%tmp4 = sext i16 %tmp3 to i32
ret i32 %tmp4
}
define i64 @smovx4s(<4 x i32> %tmp1) {
;CHECK: smov {{x[0-31]+}}, {{v[0-31]+}}.s[2]
;CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.s[2]
%tmp3 = extractelement <4 x i32> %tmp1, i32 2
%tmp4 = sext i32 %tmp3 to i64
ret i64 %tmp4
}
define i32 @smovw8b(<8 x i8> %tmp1) {
;CHECK: smov {{w[0-31]+}}, {{v[0-31]+}}.b[4]
;CHECK: smov {{w[0-9]+}}, {{v[0-9]+}}.b[4]
%tmp3 = extractelement <8 x i8> %tmp1, i32 4
%tmp4 = sext i8 %tmp3 to i32
%tmp5 = add i32 5, %tmp4
@ -309,7 +309,7 @@ define i32 @smovw8b(<8 x i8> %tmp1) {
}
define i32 @smovw4h(<4 x i16> %tmp1) {
;CHECK: smov {{w[0-31]+}}, {{v[0-31]+}}.h[2]
;CHECK: smov {{w[0-9]+}}, {{v[0-9]+}}.h[2]
%tmp3 = extractelement <4 x i16> %tmp1, i32 2
%tmp4 = sext i16 %tmp3 to i32
%tmp5 = add i32 5, %tmp4
@ -317,21 +317,21 @@ define i32 @smovw4h(<4 x i16> %tmp1) {
}
define i32 @smovx8b(<8 x i8> %tmp1) {
;CHECK: smov {{x[0-31]+}}, {{v[0-31]+}}.b[6]
;CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.b[6]
%tmp3 = extractelement <8 x i8> %tmp1, i32 6
%tmp4 = sext i8 %tmp3 to i32
ret i32 %tmp4
}
define i32 @smovx4h(<4 x i16> %tmp1) {
;CHECK: smov {{x[0-31]+}}, {{v[0-31]+}}.h[2]
;CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.h[2]
%tmp3 = extractelement <4 x i16> %tmp1, i32 2
%tmp4 = sext i16 %tmp3 to i32
ret i32 %tmp4
}
define i64 @smovx2s(<2 x i32> %tmp1) {
;CHECK: smov {{x[0-31]+}}, {{v[0-31]+}}.s[1]
;CHECK: smov {{x[0-9]+}}, {{v[0-9]+}}.s[1]
%tmp3 = extractelement <2 x i32> %tmp1, i32 1
%tmp4 = sext i32 %tmp3 to i64
ret i64 %tmp4

30
test/CodeGen/AArch64/neon-fma.ll
View File

@ -1,21 +1,21 @@
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
define <2 x float> @fmla2xfloat(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
;CHECK: fmla {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
;CHECK: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
%tmp1 = fmul <2 x float> %A, %B;
%tmp2 = fadd <2 x float> %C, %tmp1;
ret <2 x float> %tmp2
}
define <4 x float> @fmla4xfloat(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
;CHECK: fmla {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
;CHECK: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
%tmp1 = fmul <4 x float> %A, %B;
%tmp2 = fadd <4 x float> %C, %tmp1;
ret <4 x float> %tmp2
}
define <2 x double> @fmla2xdouble(<2 x double> %A, <2 x double> %B, <2 x double> %C) {
;CHECK: fmla {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
;CHECK: fmla {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
%tmp1 = fmul <2 x double> %A, %B;
%tmp2 = fadd <2 x double> %C, %tmp1;
ret <2 x double> %tmp2
@ -23,21 +23,21 @@ define <2 x double> @fmla2xdouble(<2 x double> %A, <2 x double> %B, <2 x double>
define <2 x float> @fmls2xfloat(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
;CHECK: fmls {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
;CHECK: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
%tmp1 = fmul <2 x float> %A, %B;
%tmp2 = fsub <2 x float> %C, %tmp1;
ret <2 x float> %tmp2
}
define <4 x float> @fmls4xfloat(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
;CHECK: fmls {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
;CHECK: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
%tmp1 = fmul <4 x float> %A, %B;
%tmp2 = fsub <4 x float> %C, %tmp1;
ret <4 x float> %tmp2
}
define <2 x double> @fmls2xdouble(<2 x double> %A, <2 x double> %B, <2 x double> %C) {
;CHECK: fmls {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
;CHECK: fmls {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
%tmp1 = fmul <2 x double> %A, %B;
%tmp2 = fsub <2 x double> %C, %tmp1;
ret <2 x double> %tmp2
@ -51,39 +51,39 @@ declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)
declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>)
define <2 x float> @fmla2xfloat_fused(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
;CHECK: fmla {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
;CHECK: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
%val = call <2 x float> @llvm.fma.v2f32(<2 x float> %A, <2 x float> %B, <2 x float> %C)
ret <2 x float> %val
}
define <4 x float> @fmla4xfloat_fused(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
;CHECK: fmla {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
;CHECK: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
%val = call <4 x float> @llvm.fma.v4f32(<4 x float> %A, <4 x float> %B, <4 x float> %C)
ret <4 x float> %val
}
define <2 x double> @fmla2xdouble_fused(<2 x double> %A, <2 x double> %B, <2 x double> %C) {
;CHECK: fmla {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
;CHECK: fmla {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
%val = call <2 x double> @llvm.fma.v2f64(<2 x double> %A, <2 x double> %B, <2 x double> %C)
ret <2 x double> %val
}
define <2 x float> @fmls2xfloat_fused(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
;CHECK: fmls {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
;CHECK: fmls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
%negA = fsub <2 x float> <float -0.0, float -0.0>, %A
%val = call <2 x float> @llvm.fma.v2f32(<2 x float> %negA, <2 x float> %B, <2 x float> %C)
ret <2 x float> %val
}
define <4 x float> @fmls4xfloat_fused(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
;CHECK: fmls {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
;CHECK: fmls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
%negA = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %A
%val = call <4 x float> @llvm.fma.v4f32(<4 x float> %negA, <4 x float> %B, <4 x float> %C)
ret <4 x float> %val
}
define <2 x double> @fmls2xdouble_fused(<2 x double> %A, <2 x double> %B, <2 x double> %C) {
;CHECK: fmls {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
;CHECK: fmls {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
%negA = fsub <2 x double> <double -0.0, double -0.0>, %A
%val = call <2 x double> @llvm.fma.v2f64(<2 x double> %negA, <2 x double> %B, <2 x double> %C)
ret <2 x double> %val
@ -94,19 +94,19 @@ declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>)
declare <2 x double> @llvm.fmuladd.v2f64(<2 x double>, <2 x double>, <2 x double>)
define <2 x float> @fmuladd2xfloat(<2 x float> %A, <2 x float> %B, <2 x float> %C) {
;CHECK: fmla {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
;CHECK: fmla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
%val = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %A, <2 x float> %B, <2 x float> %C)
ret <2 x float> %val
}
define <4 x float> @fmuladd4xfloat_fused(<4 x float> %A, <4 x float> %B, <4 x float> %C) {
;CHECK: fmla {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
;CHECK: fmla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
%val = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %A, <4 x float> %B, <4 x float> %C)
ret <4 x float> %val
}
define <2 x double> @fmuladd2xdouble_fused(<2 x double> %A, <2 x double> %B, <2 x double> %C) {
;CHECK: fmla {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
;CHECK: fmla {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
%val = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> %A, <2 x double> %B, <2 x double> %C)
ret <2 x double> %val
}

24
test/CodeGen/AArch64/neon-mla-mls.ll
View File

@ -2,84 +2,84 @@
define <8 x i8> @mla8xi8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) {
;CHECK: mla {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: mla {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = mul <8 x i8> %A, %B;
%tmp2 = add <8 x i8> %C, %tmp1;
ret <8 x i8> %tmp2
}
define <16 x i8> @mla16xi8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) {
;CHECK: mla {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: mla {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = mul <16 x i8> %A, %B;
%tmp2 = add <16 x i8> %C, %tmp1;
ret <16 x i8> %tmp2
}
define <4 x i16> @mla4xi16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C) {
;CHECK: mla {{v[0-31]+}}.4h, {{v[0-31]+}}.4h, {{v[0-31]+}}.4h
;CHECK: mla {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
%tmp1 = mul <4 x i16> %A, %B;
%tmp2 = add <4 x i16> %C, %tmp1;
ret <4 x i16> %tmp2
}
define <8 x i16> @mla8xi16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) {
;CHECK: mla {{v[0-31]+}}.8h, {{v[0-31]+}}.8h, {{v[0-31]+}}.8h
;CHECK: mla {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
%tmp1 = mul <8 x i16> %A, %B;
%tmp2 = add <8 x i16> %C, %tmp1;
ret <8 x i16> %tmp2
}
define <2 x i32> @mla2xi32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {
;CHECK: mla {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
;CHECK: mla {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
%tmp1 = mul <2 x i32> %A, %B;
%tmp2 = add <2 x i32> %C, %tmp1;
ret <2 x i32> %tmp2
}
define <4 x i32> @mla4xi32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
;CHECK: mla {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
;CHECK: mla {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
%tmp1 = mul <4 x i32> %A, %B;
%tmp2 = add <4 x i32> %C, %tmp1;
ret <4 x i32> %tmp2
}
define <8 x i8> @mls8xi8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) {
;CHECK: mls {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: mls {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp1 = mul <8 x i8> %A, %B;
%tmp2 = sub <8 x i8> %C, %tmp1;
ret <8 x i8> %tmp2
}
define <16 x i8> @mls16xi8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) {
;CHECK: mls {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: mls {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp1 = mul <16 x i8> %A, %B;
%tmp2 = sub <16 x i8> %C, %tmp1;
ret <16 x i8> %tmp2
}
define <4 x i16> @mls4xi16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C) {
;CHECK: mls {{v[0-31]+}}.4h, {{v[0-31]+}}.4h, {{v[0-31]+}}.4h
;CHECK: mls {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
%tmp1 = mul <4 x i16> %A, %B;
%tmp2 = sub <4 x i16> %C, %tmp1;
ret <4 x i16> %tmp2
}
define <8 x i16> @mls8xi16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) {
;CHECK: mls {{v[0-31]+}}.8h, {{v[0-31]+}}.8h, {{v[0-31]+}}.8h
;CHECK: mls {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
%tmp1 = mul <8 x i16> %A, %B;
%tmp2 = sub <8 x i16> %C, %tmp1;
ret <8 x i16> %tmp2
}
define <2 x i32> @mls2xi32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {
;CHECK: mls {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
;CHECK: mls {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
%tmp1 = mul <2 x i32> %A, %B;
%tmp2 = sub <2 x i32> %C, %tmp1;
ret <2 x i32> %tmp2
}
define <4 x i32> @mls4xi32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
;CHECK: mls {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
;CHECK: mls {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
%tmp1 = mul <4 x i32> %A, %B;
%tmp2 = sub <4 x i32> %C, %tmp1;
ret <4 x i32> %tmp2

78
test/CodeGen/AArch64/neon-mov.ll
View File

@ -1,204 +1,204 @@
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
define <8 x i8> @movi8b() {
;CHECK: movi {{v[0-31]+}}.8b, #0x8
;CHECK: movi {{v[0-9]+}}.8b, #0x8
ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
}
define <16 x i8> @movi16b() {
;CHECK: movi {{v[0-31]+}}.16b, #0x8
;CHECK: movi {{v[0-9]+}}.16b, #0x8
ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
}
define <2 x i32> @movi2s_lsl0() {
;CHECK: movi {{v[0-31]+}}.2s, #0xff
;CHECK: movi {{v[0-9]+}}.2s, #0xff
ret <2 x i32> < i32 255, i32 255 >
}
define <2 x i32> @movi2s_lsl8() {
;CHECK: movi {{v[0-31]+}}.2s, #0xff, lsl #8
;CHECK: movi {{v[0-9]+}}.2s, #0xff, lsl #8
ret <2 x i32> < i32 65280, i32 65280 >
}
define <2 x i32> @movi2s_lsl16() {
;CHECK: movi {{v[0-31]+}}.2s, #0xff, lsl #16
;CHECK: movi {{v[0-9]+}}.2s, #0xff, lsl #16
ret <2 x i32> < i32 16711680, i32 16711680 >
}
define <2 x i32> @movi2s_lsl24() {
;CHECK: movi {{v[0-31]+}}.2s, #0xff, lsl #24
;CHECK: movi {{v[0-9]+}}.2s, #0xff, lsl #24
ret <2 x i32> < i32 4278190080, i32 4278190080 >
}
define <4 x i32> @movi4s_lsl0() {
;CHECK: movi {{v[0-31]+}}.4s, #0xff
;CHECK: movi {{v[0-9]+}}.4s, #0xff
ret <4 x i32> < i32 255, i32 255, i32 255, i32 255 >
}
define <4 x i32> @movi4s_lsl8() {
;CHECK: movi {{v[0-31]+}}.4s, #0xff, lsl #8
;CHECK: movi {{v[0-9]+}}.4s, #0xff, lsl #8
ret <4 x i32> < i32 65280, i32 65280, i32 65280, i32 65280 >
}
define <4 x i32> @movi4s_lsl16() {
;CHECK: movi {{v[0-31]+}}.4s, #0xff, lsl #16
;CHECK: movi {{v[0-9]+}}.4s, #0xff, lsl #16
ret <4 x i32> < i32 16711680, i32 16711680, i32 16711680, i32 16711680 >
}
define <4 x i32> @movi4s_lsl24() {
;CHECK: movi {{v[0-31]+}}.4s, #0xff, lsl #24
;CHECK: movi {{v[0-9]+}}.4s, #0xff, lsl #24
ret <4 x i32> < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080 >
}
define <4 x i16> @movi4h_lsl0() {
;CHECK: movi {{v[0-31]+}}.4h, #0xff
;CHECK: movi {{v[0-9]+}}.4h, #0xff
ret <4 x i16> < i16 255, i16 255, i16 255, i16 255 >
}
define <4 x i16> @movi4h_lsl8() {
;CHECK: movi {{v[0-31]+}}.4h, #0xff, lsl #8
;CHECK: movi {{v[0-9]+}}.4h, #0xff, lsl #8
ret <4 x i16> < i16 65280, i16 65280, i16 65280, i16 65280 >
}
define <8 x i16> @movi8h_lsl0() {
;CHECK: movi {{v[0-31]+}}.8h, #0xff
;CHECK: movi {{v[0-9]+}}.8h, #0xff
ret <8 x i16> < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
}
define <8 x i16> @movi8h_lsl8() {
;CHECK: movi {{v[0-31]+}}.8h, #0xff, lsl #8
;CHECK: movi {{v[0-9]+}}.8h, #0xff, lsl #8
ret <8 x i16> < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
}
define <2 x i32> @mvni2s_lsl0() {
;CHECK: mvni {{v[0-31]+}}.2s, #0x10
;CHECK: mvni {{v[0-9]+}}.2s, #0x10
ret <2 x i32> < i32 4294967279, i32 4294967279 >
}
define <2 x i32> @mvni2s_lsl8() {
;CHECK: mvni {{v[0-31]+}}.2s, #0x10, lsl #8
;CHECK: mvni {{v[0-9]+}}.2s, #0x10, lsl #8
ret <2 x i32> < i32 4294963199, i32 4294963199 >
}
define <2 x i32> @mvni2s_lsl16() {
;CHECK: mvni {{v[0-31]+}}.2s, #0x10, lsl #16
;CHECK: mvni {{v[0-9]+}}.2s, #0x10, lsl #16
ret <2 x i32> < i32 4293918719, i32 4293918719 >
}
define <2 x i32> @mvni2s_lsl24() {
;CHECK: mvni {{v[0-31]+}}.2s, #0x10, lsl #24
;CHECK: mvni {{v[0-9]+}}.2s, #0x10, lsl #24
ret <2 x i32> < i32 4026531839, i32 4026531839 >
}
define <4 x i32> @mvni4s_lsl0() {
;CHECK: mvni {{v[0-31]+}}.4s, #0x10
;CHECK: mvni {{v[0-9]+}}.4s, #0x10
ret <4 x i32> < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
}
define <4 x i32> @mvni4s_lsl8() {
;CHECK: mvni {{v[0-31]+}}.4s, #0x10, lsl #8
;CHECK: mvni {{v[0-9]+}}.4s, #0x10, lsl #8
ret <4 x i32> < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 >
}
define <4 x i32> @mvni4s_lsl16() {
;CHECK: mvni {{v[0-31]+}}.4s, #0x10, lsl #16
;CHECK: mvni {{v[0-9]+}}.4s, #0x10, lsl #16
ret <4 x i32> < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 >
}
define <4 x i32> @mvni4s_lsl24() {
;CHECK: mvni {{v[0-31]+}}.4s, #0x10, lsl #24
;CHECK: mvni {{v[0-9]+}}.4s, #0x10, lsl #24
ret <4 x i32> < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839 >
}
define <4 x i16> @mvni4h_lsl0() {
;CHECK: mvni {{v[0-31]+}}.4h, #0x10
;CHECK: mvni {{v[0-9]+}}.4h, #0x10
ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
}
define <4 x i16> @mvni4h_lsl8() {
;CHECK: mvni {{v[0-31]+}}.4h, #0x10, lsl #8
;CHECK: mvni {{v[0-9]+}}.4h, #0x10, lsl #8
ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
}
define <8 x i16> @mvni8h_lsl0() {
;CHECK: mvni {{v[0-31]+}}.8h, #0x10
;CHECK: mvni {{v[0-9]+}}.8h, #0x10
ret <8 x i16> < i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519 >
}
define <8 x i16> @mvni8h_lsl8() {
;CHECK: mvni {{v[0-31]+}}.8h, #0x10, lsl #8
;CHECK: mvni {{v[0-9]+}}.8h, #0x10, lsl #8
ret <8 x i16> < i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439 >
}
define <2 x i32> @movi2s_msl8(<2 x i32> %a) {
;CHECK: movi {{v[0-31]+}}.2s, #0xff, msl #8
;CHECK: movi {{v[0-9]+}}.2s, #0xff, msl #8
ret <2 x i32> < i32 65535, i32 65535 >
}
define <2 x i32> @movi2s_msl16() {
;CHECK: movi {{v[0-31]+}}.2s, #0xff, msl #16
;CHECK: movi {{v[0-9]+}}.2s, #0xff, msl #16
ret <2 x i32> < i32 16777215, i32 16777215 >
}
define <4 x i32> @movi4s_msl8() {
;CHECK: movi {{v[0-31]+}}.4s, #0xff, msl #8
;CHECK: movi {{v[0-9]+}}.4s, #0xff, msl #8
ret <4 x i32> < i32 65535, i32 65535, i32 65535, i32 65535 >
}
define <4 x i32> @movi4s_msl16() {
;CHECK: movi {{v[0-31]+}}.4s, #0xff, msl #16
;CHECK: movi {{v[0-9]+}}.4s, #0xff, msl #16
ret <4 x i32> < i32 16777215, i32 16777215, i32 16777215, i32 16777215 >
}
define <2 x i32> @mvni2s_msl8() {
;CHECK: mvni {{v[0-31]+}}.2s, #0x10, msl #8
;CHECK: mvni {{v[0-9]+}}.2s, #0x10, msl #8
ret <2 x i32> < i32 18446744073709547264, i32 18446744073709547264>
}
define <2 x i32> @mvni2s_msl16() {
;CHECK: mvni {{v[0-31]+}}.2s, #0x10, msl #16
;CHECK: mvni {{v[0-9]+}}.2s, #0x10, msl #16
ret <2 x i32> < i32 18446744073708437504, i32 18446744073708437504>
}
define <4 x i32> @mvni4s_msl8() {
;CHECK: mvni {{v[0-31]+}}.4s, #0x10, msl #8
;CHECK: mvni {{v[0-9]+}}.4s, #0x10, msl #8
ret <4 x i32> < i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264>
}
define <4 x i32> @mvni4s_msl16() {
;CHECK: mvni {{v[0-31]+}}.4s, #0x10, msl #16
;CHECK: mvni {{v[0-9]+}}.4s, #0x10, msl #16
ret <4 x i32> < i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504>
}
define <2 x i64> @movi2d() {
;CHECK: movi {{v[0-31]+}}.2d, #0xff0000ff0000ffff
;CHECK: movi {{v[0-9]+}}.2d, #0xff0000ff0000ffff
ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
}
define <1 x i64> @movid() {
;CHECK: movi {{d[0-31]+}}, #0xff0000ff0000ffff
;CHECK: movi {{d[0-9]+}}, #0xff0000ff0000ffff
ret <1 x i64> < i64 18374687574888349695 >
}
define <2 x float> @fmov2s() {
;CHECK: fmov {{v[0-31]+}}.2s, #-12.00000000
;CHECK: fmov {{v[0-9]+}}.2s, #-12.00000000
ret <2 x float> < float -1.2e1, float -1.2e1>
}
define <4 x float> @fmov4s() {
;CHECK: fmov {{v[0-31]+}}.4s, #-12.00000000
;CHECK: fmov {{v[0-9]+}}.4s, #-12.00000000
ret <4 x float> < float -1.2e1, float -1.2e1, float -1.2e1, float -1.2e1>
}
define <2 x double> @fmov2d() {
;CHECK: fmov {{v[0-31]+}}.2d, #-12.00000000
;CHECK: fmov {{v[0-9]+}}.2d, #-12.00000000
ret <2 x double> < double -1.2e1, double -1.2e1>
}

24
test/CodeGen/AArch64/neon-mul-div.ll
View File

@ -2,72 +2,72 @@
define <8 x i8> @mul8xi8(<8 x i8> %A, <8 x i8> %B) {
;CHECK: mul {{v[0-31]+}}.8b, {{v[0-31]+}}.8b, {{v[0-31]+}}.8b
;CHECK: mul {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
%tmp3 = mul <8 x i8> %A, %B;
ret <8 x i8> %tmp3
}
define <16 x i8> @mul16xi8(<16 x i8> %A, <16 x i8> %B) {
;CHECK: mul {{v[0-31]+}}.16b, {{v[0-31]+}}.16b, {{v[0-31]+}}.16b
;CHECK: mul {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
%tmp3 = mul <16 x i8> %A, %B;
ret <16 x i8> %tmp3
}
define <4 x i16> @mul4xi16(<4 x i16> %A, <4 x i16> %B) {
;CHECK: mul {{v[0-31]+}}.4h, {{v[0-31]+}}.4h, {{v[0-31]+}}.4h
;CHECK: mul {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
%tmp3 = mul <4 x i16> %A, %B;
ret <4 x i16> %tmp3
}
define <8 x i16> @mul8xi16(<8 x i16> %A, <8 x i16> %B) {
;CHECK: mul {{v[0-31]+}}.8h, {{v[0-31]+}}.8h, {{v[0-31]+}}.8h
;CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
%tmp3 = mul <8 x i16> %A, %B;
ret <8 x i16> %tmp3
}
define <2 x i32> @mul2xi32(<2 x i32> %A, <2 x i32> %B) {
;CHECK: mul {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
;CHECK: mul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
%tmp3 = mul <2 x i32> %A, %B;
ret <2 x i32> %tmp3
}
define <4 x i32> @mul4x32(<4 x i32> %A, <4 x i32> %B) {
;CHECK: mul {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
;CHECK: mul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
%tmp3 = mul <4 x i32> %A, %B;
ret <4 x i32> %tmp3
}
define <2 x float> @mul2xfloat(<2 x float> %A, <2 x float> %B) {
;CHECK: fmul {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
;CHECK: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
%tmp3 = fmul <2 x float> %A, %B;
ret <2 x float> %tmp3
}
define <4 x float> @mul4xfloat(<4 x float> %A, <4 x float> %B) {
;CHECK: fmul {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
;CHECK: fmul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
%tmp3 = fmul <4 x float> %A, %B;
ret <4 x float> %tmp3
}
define <2 x double> @mul2xdouble(<2 x double> %A, <2 x double> %B) {
;CHECK: fmul {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
;CHECK: fmul {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
%tmp3 = fmul <2 x double> %A, %B;
ret <2 x double> %tmp3
}
define <2 x float> @div2xfloat(<2 x float> %A, <2 x float> %B) {
;CHECK: fdiv {{v[0-31]+}}.2s, {{v[0-31]+}}.2s, {{v[0-31]+}}.2s
;CHECK: fdiv {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
%tmp3 = fdiv <2 x float> %A, %B;
ret <2 x float> %tmp3
}
define <4 x float> @div4xfloat(<4 x float> %A, <4 x float> %B) {
;CHECK: fdiv {{v[0-31]+}}.4s, {{v[0-31]+}}.4s, {{v[0-31]+}}.4s
;CHECK: fdiv {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
%tmp3 = fdiv <4 x float> %A, %B;
ret <4 x float> %tmp3
}
define <2 x double> @div2xdouble(<2 x double> %A, <2 x double> %B) {
;CHECK: fdiv {{v[0-31]+}}.2d, {{v[0-31]+}}.2d, {{v[0-31]+}}.2d
;CHECK: fdiv {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
%tmp3 = fdiv <2 x double> %A, %B;
ret <2 x double> %tmp3
}

12
test/CodeGen/AArch64/neon-scalar-add-sub.ll
View File

@ -1,13 +1,13 @@
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
define <1 x i64> @add1xi64(<1 x i64> %A, <1 x i64> %B) {
;CHECK: add {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
;CHECK: add {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
%tmp3 = add <1 x i64> %A, %B;
ret <1 x i64> %tmp3
}
define <1 x i64> @sub1xi64(<1 x i64> %A, <1 x i64> %B) {
;CHECK: sub {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
;CHECK: sub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
%tmp3 = sub <1 x i64> %A, %B;
ret <1 x i64> %tmp3
}
@ -18,14 +18,14 @@ declare <1 x i64> @llvm.aarch64.neon.vadddu(<1 x i64>, <1 x i64>)
define <1 x i64> @test_add_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_add_v1i64:
%tmp1 = call <1 x i64> @llvm.aarch64.neon.vaddds(<1 x i64> %lhs, <1 x i64> %rhs)
; CHECK: add {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
; CHECK: add {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}
define <1 x i64> @test_uadd_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_uadd_v1i64:
%tmp1 = call <1 x i64> @llvm.aarch64.neon.vadddu(<1 x i64> %lhs, <1 x i64> %rhs)
;CHECK: add {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
;CHECK: add {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}
@ -35,14 +35,14 @@ declare <1 x i64> @llvm.aarch64.neon.vsubdu(<1 x i64>, <1 x i64>)
define <1 x i64> @test_sub_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_sub_v1i64:
%tmp1 = call <1 x i64> @llvm.aarch64.neon.vsubds(<1 x i64> %lhs, <1 x i64> %rhs)
; CHECK: sub {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
; CHECK: sub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}
define <1 x i64> @test_usub_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_usub_v1i64:
%tmp1 = call <1 x i64> @llvm.aarch64.neon.vsubdu(<1 x i64> %lhs, <1 x i64> %rhs)
;CHECK: sub {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
;CHECK: sub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}

24
test/CodeGen/AArch64/neon-scalar-by-elem-fma.ll
View File

@ -5,7 +5,7 @@ declare double @llvm.fma.f64(double, double, double)
define float @test_fmla_ss4S(float %a, float %b, <4 x float> %v) {
; CHECK: test_fmla_ss4S
; CHECK: fmla {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-31]+}}.s[3]
; CHECK: fmla {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
%tmp1 = extractelement <4 x float> %v, i32 3
%tmp2 = call float @llvm.fma.f32(float %b, float %tmp1, float %a)
ret float %tmp2
@ -13,7 +13,7 @@ define float @test_fmla_ss4S(float %a, float %b, <4 x float> %v) {
define float @test_fmla_ss4S_swap(float %a, float %b, <4 x float> %v) {
; CHECK: test_fmla_ss4S_swap
; CHECK: fmla {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-31]+}}.s[3]
; CHECK: fmla {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
%tmp1 = extractelement <4 x float> %v, i32 3
%tmp2 = call float @llvm.fma.f32(float %tmp1, float %a, float %a)
ret float %tmp2
@ -21,7 +21,7 @@ define float @test_fmla_ss4S_swap(float %a, float %b, <4 x float> %v) {
define float @test_fmla_ss2S(float %a, float %b, <2 x float> %v) {
; CHECK: test_fmla_ss2S
; CHECK: fmla {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-31]+}}.s[1]
; CHECK: fmla {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
%tmp1 = extractelement <2 x float> %v, i32 1
%tmp2 = call float @llvm.fma.f32(float %b, float %tmp1, float %a)
ret float %tmp2
@ -29,7 +29,7 @@ define float @test_fmla_ss2S(float %a, float %b, <2 x float> %v) {
define double @test_fmla_ddD(double %a, double %b, <1 x double> %v) {
; CHECK: test_fmla_ddD
; CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-31]+}}.d[0]
; CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
%tmp1 = extractelement <1 x double> %v, i32 0
%tmp2 = call double @llvm.fma.f64(double %b, double %tmp1, double %a)
ret double %tmp2
@ -37,7 +37,7 @@ define double @test_fmla_ddD(double %a, double %b, <1 x double> %v) {
define double @test_fmla_dd2D(double %a, double %b, <2 x double> %v) {
; CHECK: test_fmla_dd2D
; CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-31]+}}.d[1]
; CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
%tmp1 = extractelement <2 x double> %v, i32 1
%tmp2 = call double @llvm.fma.f64(double %b, double %tmp1, double %a)
ret double %tmp2
@ -45,7 +45,7 @@ define double @test_fmla_dd2D(double %a, double %b, <2 x double> %v) {
define double @test_fmla_dd2D_swap(double %a, double %b, <2 x double> %v) {
; CHECK: test_fmla_dd2D_swap
; CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-31]+}}.d[1]
; CHECK: fmla {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
%tmp1 = extractelement <2 x double> %v, i32 1
%tmp2 = call double @llvm.fma.f64(double %tmp1, double %b, double %a)
ret double %tmp2
@ -53,7 +53,7 @@ define double @test_fmla_dd2D_swap(double %a, double %b, <2 x double> %v) {
define float @test_fmls_ss4S(float %a, float %b, <4 x float> %v) {
; CHECK: test_fmls_ss4S
; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-31]+}}.s[3]
; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
%tmp1 = extractelement <4 x float> %v, i32 3
%tmp2 = fsub float -0.0, %tmp1
%tmp3 = call float @llvm.fma.f32(float %tmp2, float %tmp1, float %a)
@ -62,7 +62,7 @@ define float @test_fmls_ss4S(float %a, float %b, <4 x float> %v) {
define float @test_fmls_ss4S_swap(float %a, float %b, <4 x float> %v) {
; CHECK: test_fmls_ss4S_swap
; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-31]+}}.s[3]
; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
%tmp1 = extractelement <4 x float> %v, i32 3
%tmp2 = fsub float -0.0, %tmp1
%tmp3 = call float @llvm.fma.f32(float %tmp1, float %tmp2, float %a)
@ -72,7 +72,7 @@ define float @test_fmls_ss4S_swap(float %a, float %b, <4 x float> %v) {
define float @test_fmls_ss2S(float %a, float %b, <2 x float> %v) {
; CHECK: test_fmls_ss2S
; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-31]+}}.s[1]
; CHECK: fmls {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
%tmp1 = extractelement <2 x float> %v, i32 1
%tmp2 = fsub float -0.0, %tmp1
%tmp3 = call float @llvm.fma.f32(float %tmp2, float %tmp1, float %a)
@ -81,7 +81,7 @@ define float @test_fmls_ss2S(float %a, float %b, <2 x float> %v) {
define double @test_fmls_ddD(double %a, double %b, <1 x double> %v) {
; CHECK: test_fmls_ddD
; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-31]+}}.d[0]
; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
%tmp1 = extractelement <1 x double> %v, i32 0
%tmp2 = fsub double -0.0, %tmp1
%tmp3 = call double @llvm.fma.f64(double %tmp2, double %tmp1, double %a)
@ -90,7 +90,7 @@ define double @test_fmls_ddD(double %a, double %b, <1 x double> %v) {
define double @test_fmls_dd2D(double %a, double %b, <2 x double> %v) {
; CHECK: test_fmls_dd2D
; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-31]+}}.d[1]
; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
%tmp1 = extractelement <2 x double> %v, i32 1
%tmp2 = fsub double -0.0, %tmp1
%tmp3 = call double @llvm.fma.f64(double %tmp2, double %tmp1, double %a)
@ -99,7 +99,7 @@ define double @test_fmls_dd2D(double %a, double %b, <2 x double> %v) {
define double @test_fmls_dd2D_swap(double %a, double %b, <2 x double> %v) {
; CHECK: test_fmls_dd2D_swap
; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-31]+}}.d[1]
; CHECK: fmls {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
%tmp1 = extractelement <2 x double> %v, i32 1
%tmp2 = fsub double -0.0, %tmp1
%tmp3 = call double @llvm.fma.f64(double %tmp1, double %tmp2, double %a)

28
test/CodeGen/AArch64/neon-scalar-by-elem-mul.ll
View File

@ -2,7 +2,7 @@
define float @test_fmul_lane_ss2S(float %a, <2 x float> %v) {
; CHECK: test_fmul_lane_ss2S
; CHECK: fmul {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[1]
; CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
%tmp1 = extractelement <2 x float> %v, i32 1
%tmp2 = fmul float %a, %tmp1;
ret float %tmp2;
@ -10,7 +10,7 @@ define float @test_fmul_lane_ss2S(float %a, <2 x float> %v) {
define float @test_fmul_lane_ss2S_swap(float %a, <2 x float> %v) {
; CHECK: test_fmul_lane_ss2S_swap
; CHECK: fmul {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[1]
; CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
%tmp1 = extractelement <2 x float> %v, i32 1
%tmp2 = fmul float %tmp1, %a;
ret float %tmp2;
@ -19,7 +19,7 @@ define float @test_fmul_lane_ss2S_swap(float %a, <2 x float> %v) {
define float @test_fmul_lane_ss4S(float %a, <4 x float> %v) {
; CHECK: test_fmul_lane_ss4S
; CHECK: fmul {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[3]
; CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
%tmp1 = extractelement <4 x float> %v, i32 3
%tmp2 = fmul float %a, %tmp1;
ret float %tmp2;
@ -27,7 +27,7 @@ define float @test_fmul_lane_ss4S(float %a, <4 x float> %v) {
define float @test_fmul_lane_ss4S_swap(float %a, <4 x float> %v) {
; CHECK: test_fmul_lane_ss4S_swap
; CHECK: fmul {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[3]
; CHECK: fmul {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
%tmp1 = extractelement <4 x float> %v, i32 3
%tmp2 = fmul float %tmp1, %a;
ret float %tmp2;
@ -36,7 +36,7 @@ define float @test_fmul_lane_ss4S_swap(float %a, <4 x float> %v) {
define double @test_fmul_lane_ddD(double %a, <1 x double> %v) {
; CHECK: test_fmul_lane_ddD
; CHECK: fmul {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[0]
; CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
%tmp1 = extractelement <1 x double> %v, i32 0
%tmp2 = fmul double %a, %tmp1;
ret double %tmp2;
@ -46,7 +46,7 @@ define double @test_fmul_lane_ddD(double %a, <1 x double> %v) {
define double @test_fmul_lane_dd2D(double %a, <2 x double> %v) {
; CHECK: test_fmul_lane_dd2D
; CHECK: fmul {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[1]
; CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
%tmp1 = extractelement <2 x double> %v, i32 1
%tmp2 = fmul double %a, %tmp1;
ret double %tmp2;
@ -55,7 +55,7 @@ define double @test_fmul_lane_dd2D(double %a, <2 x double> %v) {
define double @test_fmul_lane_dd2D_swap(double %a, <2 x double> %v) {
; CHECK: test_fmul_lane_dd2D_swap
; CHECK: fmul {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[1]
; CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
%tmp1 = extractelement <2 x double> %v, i32 1
%tmp2 = fmul double %tmp1, %a;
ret double %tmp2;
@ -65,7 +65,7 @@ declare float @llvm.aarch64.neon.vmulx.f32(float, float)
define float @test_fmulx_lane_f32(float %a, <2 x float> %v) {
; CHECK: test_fmulx_lane_f32
; CHECK: fmulx {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[1]
; CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[1]
%tmp1 = extractelement <2 x float> %v, i32 1
%tmp2 = call float @llvm.aarch64.neon.vmulx.f32(float %a, float %tmp1)
ret float %tmp2;
@ -73,7 +73,7 @@ define float @test_fmulx_lane_f32(float %a, <2 x float> %v) {
define float @test_fmulx_laneq_f32(float %a, <4 x float> %v) {
; CHECK: test_fmulx_laneq_f32
; CHECK: fmulx {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[3]
; CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
%tmp1 = extractelement <4 x float> %v, i32 3
%tmp2 = call float @llvm.aarch64.neon.vmulx.f32(float %a, float %tmp1)
ret float %tmp2;
@ -81,7 +81,7 @@ define float @test_fmulx_laneq_f32(float %a, <4 x float> %v) {
define float @test_fmulx_laneq_f32_swap(float %a, <4 x float> %v) {
; CHECK: test_fmulx_laneq_f32_swap
; CHECK: fmulx {{s[0-31]+}}, {{s[0-31]+}}, {{v[0-31]+}}.s[3]
; CHECK: fmulx {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}.s[3]
%tmp1 = extractelement <4 x float> %v, i32 3
%tmp2 = call float @llvm.aarch64.neon.vmulx.f32(float %tmp1, float %a)
ret float %tmp2;
@ -91,7 +91,7 @@ declare double @llvm.aarch64.neon.vmulx.f64(double, double)
define double @test_fmulx_lane_f64(double %a, <1 x double> %v) {
; CHECK: test_fmulx_lane_f64
; CHECK: fmulx {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[0]
; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
%tmp1 = extractelement <1 x double> %v, i32 0
%tmp2 = call double @llvm.aarch64.neon.vmulx.f64(double %a, double %tmp1)
ret double %tmp2;
@ -99,7 +99,7 @@ define double @test_fmulx_lane_f64(double %a, <1 x double> %v) {
define double @test_fmulx_laneq_f64_0(double %a, <2 x double> %v) {
; CHECK: test_fmulx_laneq_f64_0
; CHECK: fmulx {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[0]
; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[0]
%tmp1 = extractelement <2 x double> %v, i32 0
%tmp2 = call double @llvm.aarch64.neon.vmulx.f64(double %a, double %tmp1)
ret double %tmp2;
@ -108,7 +108,7 @@ define double @test_fmulx_laneq_f64_0(double %a, <2 x double> %v) {
define double @test_fmulx_laneq_f64_1(double %a, <2 x double> %v) {
; CHECK: test_fmulx_laneq_f64_1
; CHECK: fmulx {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[1]
; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
%tmp1 = extractelement <2 x double> %v, i32 1
%tmp2 = call double @llvm.aarch64.neon.vmulx.f64(double %a, double %tmp1)
ret double %tmp2;
@ -116,7 +116,7 @@ define double @test_fmulx_laneq_f64_1(double %a, <2 x double> %v) {
define double @test_fmulx_laneq_f64_1_swap(double %a, <2 x double> %v) {
; CHECK: test_fmulx_laneq_f64_1_swap
; CHECK: fmulx {{d[0-31]+}}, {{d[0-31]+}}, {{v[0-31]+}}.d[1]
; CHECK: fmulx {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}.d[1]
%tmp1 = extractelement <2 x double> %v, i32 1
%tmp2 = call double @llvm.aarch64.neon.vmulx.f64(double %tmp1, double %a)
ret double %tmp2;

24
test/CodeGen/AArch64/neon-scalar-copy.ll
View File

@ -2,21 +2,21 @@
define float @test_dup_sv2S(<2 x float> %v) {
;CHECK: test_dup_sv2S
;CHECK: dup {{s[0-31]+}}, {{v[0-31]+}}.s[1]
;CHECK: dup {{s[0-9]+}}, {{v[0-9]+}}.s[1]
%tmp1 = extractelement <2 x float> %v, i32 1
ret float %tmp1
}
define float @test_dup_sv4S(<4 x float> %v) {
;CHECK: test_dup_sv4S
;CHECK: dup {{s[0-31]+}}, {{v[0-31]+}}.s[0]
;CHECK: dup {{s[0-9]+}}, {{v[0-9]+}}.s[0]
%tmp1 = extractelement <4 x float> %v, i32 0
ret float %tmp1
}
define double @test_dup_dvD(<1 x double> %v) {
;CHECK: test_dup_dvD
;CHECK-NOT: dup {{d[0-31]+}}, {{v[0-31]+}}.d[0]
;CHECK-NOT: dup {{d[0-9]+}}, {{v[0-9]+}}.d[0]
;CHECK: ret
%tmp1 = extractelement <1 x double> %v, i32 0
ret double %tmp1
@ -24,63 +24,63 @@ define double @test_dup_dvD(<1 x double> %v) {
define double @test_dup_dv2D(<2 x double> %v) {
;CHECK: test_dup_dv2D
;CHECK: dup {{d[0-31]+}}, {{v[0-31]+}}.d[1]
;CHECK: dup {{d[0-9]+}}, {{v[0-9]+}}.d[1]
%tmp1 = extractelement <2 x double> %v, i32 1
ret double %tmp1
}
define <1 x i8> @test_vector_dup_bv16B(<16 x i8> %v1) {
;CHECK: test_vector_dup_bv16B
;CHECK: dup {{b[0-31]+}}, {{v[0-31]+}}.b[14]
;CHECK: dup {{b[0-9]+}}, {{v[0-9]+}}.b[14]
%shuffle.i = shufflevector <16 x i8> %v1, <16 x i8> undef, <1 x i32> <i32 14>
ret <1 x i8> %shuffle.i
}
define <1 x i8> @test_vector_dup_bv8B(<8 x i8> %v1) {
;CHECK: test_vector_dup_bv8B
;CHECK: dup {{b[0-31]+}}, {{v[0-31]+}}.b[7]
;CHECK: dup {{b[0-9]+}}, {{v[0-9]+}}.b[7]
%shuffle.i = shufflevector <8 x i8> %v1, <8 x i8> undef, <1 x i32> <i32 7>
ret <1 x i8> %shuffle.i
}
define <1 x i16> @test_vector_dup_hv8H(<8 x i16> %v1) {
;CHECK: test_vector_dup_hv8H
;CHECK: dup {{h[0-31]+}}, {{v[0-31]+}}.h[7]
;CHECK: dup {{h[0-9]+}}, {{v[0-9]+}}.h[7]
%shuffle.i = shufflevector <8 x i16> %v1, <8 x i16> undef, <1 x i32> <i32 7>
ret <1 x i16> %shuffle.i
}
define <1 x i16> @test_vector_dup_hv4H(<4 x i16> %v1) {
;CHECK: test_vector_dup_hv4H
;CHECK: dup {{h[0-31]+}}, {{v[0-31]+}}.h[3]
;CHECK: dup {{h[0-9]+}}, {{v[0-9]+}}.h[3]
%shuffle.i = shufflevector <4 x i16> %v1, <4 x i16> undef, <1 x i32> <i32 3>
ret <1 x i16> %shuffle.i
}
define <1 x i32> @test_vector_dup_sv4S(<4 x i32> %v1) {
;CHECK: test_vector_dup_sv4S
;CHECK: dup {{s[0-31]+}}, {{v[0-31]+}}.s[3]
;CHECK: dup {{s[0-9]+}}, {{v[0-9]+}}.s[3]
%shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <1 x i32> <i32 3>
ret <1 x i32> %shuffle
}
define <1 x i32> @test_vector_dup_sv2S(<2 x i32> %v1) {
;CHECK: test_vector_dup_sv2S
;CHECK: dup {{s[0-31]+}}, {{v[0-31]+}}.s[1]
;CHECK: dup {{s[0-9]+}}, {{v[0-9]+}}.s[1]
%shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <1 x i32> <i32 1>
ret <1 x i32> %shuffle
}
define <1 x i64> @test_vector_dup_dv2D(<2 x i64> %v1) {
;CHECK: test_vector_dup_dv2D
;CHECK: dup {{d[0-31]+}}, {{v[0-31]+}}.d[1]
;CHECK: dup {{d[0-9]+}}, {{v[0-9]+}}.d[1]
%shuffle.i = shufflevector <2 x i64> %v1, <2 x i64> undef, <1 x i32> <i32 1>
ret <1 x i64> %shuffle.i
}
define <1 x i64> @test_vector_copy_dup_dv2D(<1 x i64> %a, <2 x i64> %c) {
;CHECK: test_vector_copy_dup_dv2D
;CHECK: dup {{d[0-31]+}}, {{v[0-31]+}}.d[1]
;CHECK: dup {{d[0-9]+}}, {{v[0-9]+}}.d[1]
%vget_lane = extractelement <2 x i64> %c, i32 1
%vset_lane = insertelement <1 x i64> undef, i64 %vget_lane, i32 0
ret <1 x i64> %vset_lane

8
test/CodeGen/AArch64/neon-scalar-rounding-shift.ll
View File

@ -7,14 +7,14 @@ declare <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64>, <1 x i64>)
define <1 x i64> @test_urshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_urshl_v1i64:
%tmp1 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
;CHECK: urshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
;CHECK: urshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}
define <1 x i64> @test_srshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_srshl_v1i64:
%tmp1 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
;CHECK: srshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
;CHECK: srshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}
@ -24,14 +24,14 @@ declare <1 x i64> @llvm.aarch64.neon.vrshlds(<1 x i64>, <1 x i64>)
define <1 x i64> @test_urshl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_urshl_v1i64_aarch64:
%tmp1 = call <1 x i64> @llvm.aarch64.neon.vrshldu(<1 x i64> %lhs, <1 x i64> %rhs)
;CHECK: urshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
;CHECK: urshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}
define <1 x i64> @test_srshl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_srshl_v1i64_aarch64:
%tmp1 = call <1 x i64> @llvm.aarch64.neon.vrshlds(<1 x i64> %lhs, <1 x i64> %rhs)
;CHECK: srshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
;CHECK: srshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}

32
test/CodeGen/AArch64/neon-scalar-saturating-add-sub.ll
View File

@ -6,14 +6,14 @@ declare <1 x i8> @llvm.arm.neon.vqadds.v1i8(<1 x i8>, <1 x i8>)
define <1 x i8> @test_uqadd_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
; CHECK: test_uqadd_v1i8_aarch64:
%tmp1 = call <1 x i8> @llvm.arm.neon.vqaddu.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
;CHECK: uqadd {{b[0-31]+}}, {{b[0-31]+}}, {{b[0-31]+}}
;CHECK: uqadd {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
ret <1 x i8> %tmp1
}
define <1 x i8> @test_sqadd_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
; CHECK: test_sqadd_v1i8_aarch64:
%tmp1 = call <1 x i8> @llvm.arm.neon.vqadds.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
;CHECK: sqadd {{b[0-31]+}}, {{b[0-31]+}}, {{b[0-31]+}}
;CHECK: sqadd {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
ret <1 x i8> %tmp1
}
@ -23,14 +23,14 @@ declare <1 x i8> @llvm.arm.neon.vqsubs.v1i8(<1 x i8>, <1 x i8>)
define <1 x i8> @test_uqsub_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
; CHECK: test_uqsub_v1i8_aarch64:
%tmp1 = call <1 x i8> @llvm.arm.neon.vqsubu.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
;CHECK: uqsub {{b[0-31]+}}, {{b[0-31]+}}, {{b[0-31]+}}
;CHECK: uqsub {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
ret <1 x i8> %tmp1
}
define <1 x i8> @test_sqsub_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
; CHECK: test_sqsub_v1i8_aarch64:
%tmp1 = call <1 x i8> @llvm.arm.neon.vqsubs.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
;CHECK: sqsub {{b[0-31]+}}, {{b[0-31]+}}, {{b[0-31]+}}
;CHECK: sqsub {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
ret <1 x i8> %tmp1
}
@ -40,14 +40,14 @@ declare <1 x i16> @llvm.arm.neon.vqadds.v1i16(<1 x i16>, <1 x i16>)
define <1 x i16> @test_uqadd_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
; CHECK: test_uqadd_v1i16_aarch64:
%tmp1 = call <1 x i16> @llvm.arm.neon.vqaddu.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
;CHECK: uqadd {{h[0-31]+}}, {{h[0-31]+}}, {{h[0-31]+}}
;CHECK: uqadd {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
ret <1 x i16> %tmp1
}
define <1 x i16> @test_sqadd_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
; CHECK: test_sqadd_v1i16_aarch64:
%tmp1 = call <1 x i16> @llvm.arm.neon.vqadds.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
;CHECK: sqadd {{h[0-31]+}}, {{h[0-31]+}}, {{h[0-31]+}}
;CHECK: sqadd {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
ret <1 x i16> %tmp1
}
@ -57,14 +57,14 @@ declare <1 x i16> @llvm.arm.neon.vqsubs.v1i16(<1 x i16>, <1 x i16>)
define <1 x i16> @test_uqsub_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
; CHECK: test_uqsub_v1i16_aarch64:
%tmp1 = call <1 x i16> @llvm.arm.neon.vqsubu.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
;CHECK: uqsub {{h[0-31]+}}, {{h[0-31]+}}, {{h[0-31]+}}
;CHECK: uqsub {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
ret <1 x i16> %tmp1
}
define <1 x i16> @test_sqsub_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
; CHECK: test_sqsub_v1i16_aarch64:
%tmp1 = call <1 x i16> @llvm.arm.neon.vqsubs.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
;CHECK: sqsub {{h[0-31]+}}, {{h[0-31]+}}, {{h[0-31]+}}
;CHECK: sqsub {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
ret <1 x i16> %tmp1
}
@ -74,14 +74,14 @@ declare <1 x i32> @llvm.arm.neon.vqadds.v1i32(<1 x i32>, <1 x i32>)
define <1 x i32> @test_uqadd_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
; CHECK: test_uqadd_v1i32_aarch64:
%tmp1 = call <1 x i32> @llvm.arm.neon.vqaddu.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
;CHECK: uqadd {{s[0-31]+}}, {{s[0-31]+}}, {{s[0-31]+}}
;CHECK: uqadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
ret <1 x i32> %tmp1
}
define <1 x i32> @test_sqadd_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
; CHECK: test_sqadd_v1i32_aarch64:
%tmp1 = call <1 x i32> @llvm.arm.neon.vqadds.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
;CHECK: sqadd {{s[0-31]+}}, {{s[0-31]+}}, {{s[0-31]+}}
;CHECK: sqadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
ret <1 x i32> %tmp1
}
@ -91,7 +91,7 @@ declare <1 x i32> @llvm.arm.neon.vqsubs.v1i32(<1 x i32>, <1 x i32>)
define <1 x i32> @test_uqsub_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
; CHECK: test_uqsub_v1i32_aarch64:
%tmp1 = call <1 x i32> @llvm.arm.neon.vqsubu.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
;CHECK: uqsub {{s[0-31]+}}, {{s[0-31]+}}, {{s[0-31]+}}
;CHECK: uqsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
ret <1 x i32> %tmp1
}
@ -99,7 +99,7 @@ define <1 x i32> @test_uqsub_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
define <1 x i32> @test_sqsub_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
; CHECK: test_sqsub_v1i32_aarch64:
%tmp1 = call <1 x i32> @llvm.arm.neon.vqsubs.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
;CHECK: sqsub {{s[0-31]+}}, {{s[0-31]+}}, {{s[0-31]+}}
;CHECK: sqsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
ret <1 x i32> %tmp1
}
@ -109,14 +109,14 @@ declare <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64>, <1 x i64>)
define <1 x i64> @test_uqadd_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_uqadd_v1i64_aarch64:
%tmp1 = call <1 x i64> @llvm.arm.neon.vqaddu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
;CHECK: uqadd {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
;CHECK: uqadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}
define <1 x i64> @test_sqadd_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_sqadd_v1i64_aarch64:
%tmp1 = call <1 x i64> @llvm.arm.neon.vqadds.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
;CHECK: sqadd {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
;CHECK: sqadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}
@ -126,14 +126,14 @@ declare <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64>, <1 x i64>)
define <1 x i64> @test_uqsub_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_uqsub_v1i64_aarch64:
%tmp1 = call <1 x i64> @llvm.arm.neon.vqsubu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
;CHECK: uqsub {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
;CHECK: uqsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}
define <1 x i64> @test_sqsub_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_sqsub_v1i64_aarch64:
%tmp1 = call <1 x i64> @llvm.arm.neon.vqsubs.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
;CHECK: sqsub {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
;CHECK: sqsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}

20
test/CodeGen/AArch64/neon-scalar-saturating-rounding-shift.ll
View File

@ -6,7 +6,7 @@ declare <1 x i64> @llvm.arm.neon.vqrshifts.v1i64(<1 x i64>, <1 x i64>)
define <1 x i64> @test_uqrshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_uqrshl_v1i64:
%tmp1 = call <1 x i64> @llvm.arm.neon.vqrshiftu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
;CHECK: uqrshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
;CHECK: uqrshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}
@ -14,7 +14,7 @@ define <1 x i64> @test_uqrshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
define <1 x i64> @test_sqrshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_sqrshl_v1i64:
%tmp1 = call <1 x i64> @llvm.arm.neon.vqrshifts.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
;CHECK: sqrshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
;CHECK: sqrshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}
@ -24,7 +24,7 @@ declare <1 x i8> @llvm.aarch64.neon.vqrshls.v1i8(<1 x i8>, <1 x i8>)
define <1 x i8> @test_uqrshl_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
; CHECK: test_uqrshl_v1i8_aarch64:
%tmp1 = call <1 x i8> @llvm.aarch64.neon.vqrshlu.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
;CHECK: uqrshl {{b[0-31]+}}, {{b[0-31]+}}, {{b[0-31]+}}
;CHECK: uqrshl {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
ret <1 x i8> %tmp1
}
@ -32,7 +32,7 @@ define <1 x i8> @test_uqrshl_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
define <1 x i8> @test_sqrshl_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
; CHECK: test_sqrshl_v1i8_aarch64:
%tmp1 = call <1 x i8> @llvm.aarch64.neon.vqrshls.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
;CHECK: sqrshl {{b[0-31]+}}, {{b[0-31]+}}, {{b[0-31]+}}
;CHECK: sqrshl {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
ret <1 x i8> %tmp1
}
@ -42,7 +42,7 @@ declare <1 x i16> @llvm.aarch64.neon.vqrshls.v1i16(<1 x i16>, <1 x i16>)
define <1 x i16> @test_uqrshl_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
; CHECK: test_uqrshl_v1i16_aarch64:
%tmp1 = call <1 x i16> @llvm.aarch64.neon.vqrshlu.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
;CHECK: uqrshl {{h[0-31]+}}, {{h[0-31]+}}, {{h[0-31]+}}
;CHECK: uqrshl {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
ret <1 x i16> %tmp1
}
@ -50,7 +50,7 @@ define <1 x i16> @test_uqrshl_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
define <1 x i16> @test_sqrshl_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
; CHECK: test_sqrshl_v1i16_aarch64:
%tmp1 = call <1 x i16> @llvm.aarch64.neon.vqrshls.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
;CHECK: sqrshl {{h[0-31]+}}, {{h[0-31]+}}, {{h[0-31]+}}
;CHECK: sqrshl {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
ret <1 x i16> %tmp1
}
@ -60,7 +60,7 @@ declare <1 x i32> @llvm.aarch64.neon.vqrshls.v1i32(<1 x i32>, <1 x i32>)
define <1 x i32> @test_uqrshl_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
; CHECK: test_uqrshl_v1i32_aarch64:
%tmp1 = call <1 x i32> @llvm.aarch64.neon.vqrshlu.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
;CHECK: uqrshl {{s[0-31]+}}, {{s[0-31]+}}, {{s[0-31]+}}
;CHECK: uqrshl {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
ret <1 x i32> %tmp1
}
@ -68,7 +68,7 @@ define <1 x i32> @test_uqrshl_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
define <1 x i32> @test_sqrshl_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
; CHECK: test_sqrshl_v1i32_aarch64:
%tmp1 = call <1 x i32> @llvm.aarch64.neon.vqrshls.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
;CHECK: sqrshl {{s[0-31]+}}, {{s[0-31]+}}, {{s[0-31]+}}
;CHECK: sqrshl {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
ret <1 x i32> %tmp1
}
@ -78,7 +78,7 @@ declare <1 x i64> @llvm.aarch64.neon.vqrshls.v1i64(<1 x i64>, <1 x i64>)
define <1 x i64> @test_uqrshl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_uqrshl_v1i64_aarch64:
%tmp1 = call <1 x i64> @llvm.aarch64.neon.vqrshlu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
;CHECK: uqrshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
;CHECK: uqrshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}
@ -86,7 +86,7 @@ define <1 x i64> @test_uqrshl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
define <1 x i64> @test_sqrshl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_sqrshl_v1i64_aarch64:
%tmp1 = call <1 x i64> @llvm.aarch64.neon.vqrshls.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
;CHECK: sqrshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
;CHECK: sqrshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}

20
test/CodeGen/AArch64/neon-scalar-saturating-shift.ll
View File

@ -6,14 +6,14 @@ declare <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64>, <1 x i64>)
define <1 x i64> @test_uqshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_uqshl_v1i64:
%tmp1 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
;CHECK: uqshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
;CHECK: uqshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}
define <1 x i64> @test_sqshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_sqshl_v1i64:
%tmp1 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
;CHECK: sqshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
;CHECK: sqshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}
@ -23,14 +23,14 @@ declare <1 x i8> @llvm.aarch64.neon.vqshls.v1i8(<1 x i8>, <1 x i8>)
define <1 x i8> @test_uqshl_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
; CHECK: test_uqshl_v1i8_aarch64:
%tmp1 = call <1 x i8> @llvm.aarch64.neon.vqshlu.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
;CHECK: uqshl {{b[0-31]+}}, {{b[0-31]+}}, {{b[0-31]+}}
;CHECK: uqshl {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
ret <1 x i8> %tmp1
}
define <1 x i8> @test_sqshl_v1i8_aarch64(<1 x i8> %lhs, <1 x i8> %rhs) {
; CHECK: test_sqshl_v1i8_aarch64:
%tmp1 = call <1 x i8> @llvm.aarch64.neon.vqshls.v1i8(<1 x i8> %lhs, <1 x i8> %rhs)
;CHECK: sqshl {{b[0-31]+}}, {{b[0-31]+}}, {{b[0-31]+}}
;CHECK: sqshl {{b[0-9]+}}, {{b[0-9]+}}, {{b[0-9]+}}
ret <1 x i8> %tmp1
}
@ -40,14 +40,14 @@ declare <1 x i16> @llvm.aarch64.neon.vqshls.v1i16(<1 x i16>, <1 x i16>)
define <1 x i16> @test_uqshl_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
; CHECK: test_uqshl_v1i16_aarch64:
%tmp1 = call <1 x i16> @llvm.aarch64.neon.vqshlu.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
;CHECK: uqshl {{h[0-31]+}}, {{h[0-31]+}}, {{h[0-31]+}}
;CHECK: uqshl {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
ret <1 x i16> %tmp1
}
define <1 x i16> @test_sqshl_v1i16_aarch64(<1 x i16> %lhs, <1 x i16> %rhs) {
; CHECK: test_sqshl_v1i16_aarch64:
%tmp1 = call <1 x i16> @llvm.aarch64.neon.vqshls.v1i16(<1 x i16> %lhs, <1 x i16> %rhs)
;CHECK: sqshl {{h[0-31]+}}, {{h[0-31]+}}, {{h[0-31]+}}
;CHECK: sqshl {{h[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
ret <1 x i16> %tmp1
}
@ -57,14 +57,14 @@ declare <1 x i32> @llvm.aarch64.neon.vqshls.v1i32(<1 x i32>, <1 x i32>)
define <1 x i32> @test_uqshl_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
; CHECK: test_uqshl_v1i32_aarch64:
%tmp1 = call <1 x i32> @llvm.aarch64.neon.vqshlu.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
;CHECK: uqshl {{s[0-31]+}}, {{s[0-31]+}}, {{s[0-31]+}}
;CHECK: uqshl {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
ret <1 x i32> %tmp1
}
define <1 x i32> @test_sqshl_v1i32_aarch64(<1 x i32> %lhs, <1 x i32> %rhs) {
; CHECK: test_sqshl_v1i32_aarch64:
%tmp1 = call <1 x i32> @llvm.aarch64.neon.vqshls.v1i32(<1 x i32> %lhs, <1 x i32> %rhs)
;CHECK: sqshl {{s[0-31]+}}, {{s[0-31]+}}, {{s[0-31]+}}
;CHECK: sqshl {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
ret <1 x i32> %tmp1
}
@ -74,14 +74,14 @@ declare <1 x i64> @llvm.aarch64.neon.vqshls.v1i64(<1 x i64>, <1 x i64>)
define <1 x i64> @test_uqshl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_uqshl_v1i64_aarch64:
%tmp1 = call <1 x i64> @llvm.aarch64.neon.vqshlu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
;CHECK: uqshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
;CHECK: uqshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}
define <1 x i64> @test_sqshl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_sqshl_v1i64_aarch64:
%tmp1 = call <1 x i64> @llvm.aarch64.neon.vqshls.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
;CHECK: sqshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
;CHECK: sqshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}

8
test/CodeGen/AArch64/neon-scalar-shift.ll
View File

@ -6,7 +6,7 @@ declare <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64>, <1 x i64>)
define <1 x i64> @test_ushl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_ushl_v1i64:
%tmp1 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
; CHECK: ushl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
; CHECK: ushl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}
@ -14,7 +14,7 @@ define <1 x i64> @test_ushl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
define <1 x i64> @test_sshl_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_sshl_v1i64:
%tmp1 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %lhs, <1 x i64> %rhs)
; CHECK: sshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
; CHECK: sshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}
@ -24,14 +24,14 @@ declare <1 x i64> @llvm.aarch64.neon.vshlds(<1 x i64>, <1 x i64>)
define <1 x i64> @test_ushl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_ushl_v1i64_aarch64:
%tmp1 = call <1 x i64> @llvm.aarch64.neon.vshldu(<1 x i64> %lhs, <1 x i64> %rhs)
; CHECK: ushl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
; CHECK: ushl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}
define <1 x i64> @test_sshl_v1i64_aarch64(<1 x i64> %lhs, <1 x i64> %rhs) {
; CHECK: test_sshl_v1i64_aarch64:
%tmp1 = call <1 x i64> @llvm.aarch64.neon.vshlds(<1 x i64> %lhs, <1 x i64> %rhs)
; CHECK: sshl {{d[0-31]+}}, {{d[0-31]+}}, {{d[0-31]+}}
; CHECK: sshl {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
ret <1 x i64> %tmp1
}