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[PowerPC] Support bd(n)zl and bd(n)zlrl

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This adds support for the bd(n)zl and bd(n)zlrl instructions.
The patterns are currently used for the asm parser only.

llvm-svn: 184720
This commit is contained in:
Ulrich Weigand 2013-06-24 11:02:38 +00:00
parent 5c11c4d795
commit 19b0f3dd0c
2 changed files with 22 additions and 4 deletions
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12
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -938,6 +938,18 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in {
def BCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond),
"b${cond:cc}lrl ${cond:reg}", BrB, []>;
}
let Defs = [CTR], Uses = [CTR, RM] in {
def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst),
"bdzl $dst">;
def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst),
"bdnzl $dst">;
}
let Defs = [CTR], Uses = [CTR, LR, RM] in {
def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins),
"bdzlrl", BrB, []>;
def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins),
"bdnzlrl", BrB, []>;
}
}
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in

14
test/MC/PowerPC/ppc64-encoding-ext.s
View File

@ -54,9 +54,12 @@
# FIXME: bdnza target
# CHECK: bdnzlr # encoding: [0x4e,0x00,0x00,0x20]
bdnzlr
# FIXME: bdnzl target
# CHECK: bdnzl target # encoding: [0x42,0x00,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdnzl target
# FIXME: bdnzla target
# FIXME: bdnzlrl
# CHECK: bdnzlrl # encoding: [0x4e,0x00,0x00,0x21]
bdnzlrl
# FIXME: bdnzt 2, target
# FIXME: bdnzt target
@ -89,9 +92,12 @@
# FIXME: bdza target
# CHECK: bdzlr # encoding: [0x4e,0x40,0x00,0x20]
bdzlr
# FIXME: bdzl target
# CHECK: bdzl target # encoding: [0x42,0x40,A,0bAAAAAA01]
# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14
bdzl target
# FIXME: bdzla target
# FIXME: bdzlrl
# CHECK: bdzlrl # encoding: [0x4e,0x40,0x00,0x21]
bdzlrl
# FIXME: bdzt 2, target
# FIXME: bdzt target