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ARM assembly parsing and encoding for RFE instruction.
Fill in the missing fixed bits and the register operand bits of the instruction encoding. Refactor the definition to make the mode explicit, which is consistent with how loads and stores are normally represented and makes parsing much easier. Add parsing aliases for pseudo-instruction variants. Update the disassembler for the new representations. Add tests for parsing and encoding. llvm-svn: 136479
This commit is contained in:
Jim Grosbach
parent
b651954088
commit
1b69dbc796
@ -1739,19 +1739,44 @@ def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
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let Inst{7-5} = 0b000;
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}
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// Return From Exception
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def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
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NoItinerary, "rfe${amode}\t$base!", []> {
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class RFEI<bit wb, string asm>
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: XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
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NoItinerary, asm, "", []> {
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bits<4> Rn;
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let Inst{31-28} = 0b1111;
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let Inst{22-20} = 0b011; // W = 1
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let Inst{15-0} = 0x0a00;
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let Inst{27-25} = 0b100;
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let Inst{22} = 0;
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let Inst{21} = wb;
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let Inst{20} = 1;
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let Inst{19-16} = Rn;
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let Inst{15-0} = 0xa00;
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}
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def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
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NoItinerary, "rfe${amode}\t$base", []> {
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let Inst{31-28} = 0b1111;
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let Inst{22-20} = 0b001; // W = 0
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let Inst{15-0} = 0x0a00;
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def RFEDA : RFEI<0, "rfeda\t$Rn"> {
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let Inst{24-23} = 0;
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}
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def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
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let Inst{24-23} = 0;
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}
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def RFEDB : RFEI<0, "rfedb\t$Rn"> {
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let Inst{24-23} = 0b10;
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}
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def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
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let Inst{24-23} = 0b10;
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}
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def RFEIA : RFEI<0, "rfeia\t$Rn"> {
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let Inst{24-23} = 0b01;
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}
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def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
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let Inst{24-23} = 0b01;
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}
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def RFEIB : RFEI<0, "rfeib\t$Rn"> {
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let Inst{24-23} = 0b11;
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}
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def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
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let Inst{24-23} = 0b11;
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}
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//===----------------------------------------------------------------------===//
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@ -4421,3 +4446,11 @@ def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
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def : InstAlias<"uxtb${p} $Rd, $Rm", (UXTB GPR:$Rd, GPR:$Rm, 0, pred:$p)>;
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def : InstAlias<"uxtb16${p} $Rd, $Rm", (UXTB16 GPR:$Rd, GPR:$Rm, 0, pred:$p)>;
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def : InstAlias<"uxth${p} $Rd, $Rm", (UXTH GPR:$Rd, GPR:$Rm, 0, pred:$p)>;
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// RFE aliases
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def : MnemonicAlias<"rfefa", "rfeda">;
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def : MnemonicAlias<"rfeea", "rfedb">;
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def : MnemonicAlias<"rfefd", "rfeia">;
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def : MnemonicAlias<"rfeed", "rfeib">;
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def : MnemonicAlias<"rfe", "rfeia">;
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@ -2540,6 +2540,7 @@ getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
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Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
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Mnemonic == "setend" ||
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((Mnemonic == "pld" || Mnemonic == "pli") && !isThumb()) ||
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(Mnemonic.startswith("rfe") && !isThumb()) ||
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Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
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CanAcceptPredicationCode = false;
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} else {
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@ -799,7 +799,7 @@ static bool DisassembleCoprocessor(MCInst &MI, unsigned Opcode, uint32_t insn,
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// BXJ: Rm
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// MSRi/MSRsysi: so_imm
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// SRSW/SRS: ldstm_mode:$amode mode_imm
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// RFEW/RFE: ldstm_mode:$amode Rn
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// RFE: Rn
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static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
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unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
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@ -858,19 +858,26 @@ static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
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NumOpsAdded = 2;
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return true;
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}
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if (Opcode == ARM::SRSW || Opcode == ARM::SRS ||
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Opcode == ARM::RFEW || Opcode == ARM::RFE) {
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if (Opcode == ARM::SRSW || Opcode == ARM::SRS) {
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ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
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MI.addOperand(MCOperand::CreateImm(ARM_AM::getAM4ModeImm(SubMode)));
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if (Opcode == ARM::SRSW || Opcode == ARM::SRS)
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MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0)));
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else
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
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decodeRn(insn))));
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NumOpsAdded = 3;
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return true;
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}
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if (Opcode == ARM::RFEDA || Opcode == ARM::RFEDB ||
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Opcode == ARM::RFEIA || Opcode == ARM::RFEIB ||
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Opcode == ARM::RFEDA_UPD || Opcode == ARM::RFEDB_UPD ||
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Opcode == ARM::RFEIA_UPD || Opcode == ARM::RFEIB_UPD) {
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
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decodeRn(insn))));
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NumOpsAdded = 1;
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return true;
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}
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assert((Opcode == ARM::Bcc || Opcode == ARM::BL || Opcode == ARM::BL_pred
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|| Opcode == ARM::SMC || Opcode == ARM::SVC) &&
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@ -1168,6 +1168,56 @@ Lforward:
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@ CHECK: revshne r9, r1 @ encoding: [0xb1,0x9f,0xff,0x16]
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@------------------------------------------------------------------------------
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@ RFE
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@------------------------------------------------------------------------------
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rfeda r2
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rfedb r3
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rfeia r5
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rfeib r6
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rfeda r4!
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rfedb r7!
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rfeia r9!
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rfeib r8!
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rfefa r2
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rfeea r3
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rfefd r5
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rfeed r6
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rfefa r4!
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rfeea r7!
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rfefd r9!
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rfeed r8!
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rfe r1
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rfe r1!
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@ CHECK: rfeda r2 @ encoding: [0x00,0x0a,0x12,0xf8]
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@ CHECK: rfedb r3 @ encoding: [0x00,0x0a,0x13,0xf9]
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@ CHECK: rfeia r5 @ encoding: [0x00,0x0a,0x95,0xf8]
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@ CHECK: rfeib r6 @ encoding: [0x00,0x0a,0x96,0xf9]
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@ CHECK: rfeda r4! @ encoding: [0x00,0x0a,0x34,0xf8]
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@ CHECK: rfedb r7! @ encoding: [0x00,0x0a,0x37,0xf9]
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@ CHECK: rfeia r9! @ encoding: [0x00,0x0a,0xb9,0xf8]
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@ CHECK: rfeib r8! @ encoding: [0x00,0x0a,0xb8,0xf9]
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@ CHECK: rfeda r2 @ encoding: [0x00,0x0a,0x12,0xf8]
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@ CHECK: rfedb r3 @ encoding: [0x00,0x0a,0x13,0xf9]
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@ CHECK: rfeia r5 @ encoding: [0x00,0x0a,0x95,0xf8]
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@ CHECK: rfeib r6 @ encoding: [0x00,0x0a,0x96,0xf9]
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@ CHECK: rfeda r4! @ encoding: [0x00,0x0a,0x34,0xf8]
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@ CHECK: rfedb r7! @ encoding: [0x00,0x0a,0x37,0xf9]
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@ CHECK: rfeia r9! @ encoding: [0x00,0x0a,0xb9,0xf8]
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@ CHECK: rfeib r8! @ encoding: [0x00,0x0a,0xb8,0xf9]
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@ CHECK: rfeia r1 @ encoding: [0x00,0x0a,0x91,0xf8]
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@ CHECK: rfeia r1! @ encoding: [0x00,0x0a,0xb1,0xf8]
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@------------------------------------------------------------------------------
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@ RSB
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@------------------------------------------------------------------------------
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