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correct suffix matching to search for s/l/t suffixes on
floating point stack instructions instead of looking for b/w/l/q. This fixes issues where we'd accidentally match fistp to fistpl, when it is in fact an ambiguous instruction. This changes the behavior of llvm-mc to reject fstp, which was the correct fix for rdar://8456389: t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt') fstp (%rax) it also causes us to correctly reject fistp and fist, which addresses PR8528: t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl') fistp (%rax) ^ t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl') fist (%rax) ^ Thanks to Ismail Donmez for tracking down the issue here! llvm-svn: 118346
This commit is contained in:
Chris Lattner
parent
96ac873014
commit
1beb2b3fc5
@ -919,14 +919,6 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
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NameLoc, NameLoc));
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}
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// fstp <mem> -> fstps <mem>. Without this, we'll default to fstpl due to
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// suffix searching.
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if (Name == "fstp" && Operands.size() == 2 &&
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static_cast<X86Operand*>(Operands[1])->isMem()) {
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delete Operands[0];
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Operands[0] = X86Operand::CreateToken("fstps", NameLoc);
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}
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// FIXME: Hack to handle recognize "aa[dm]" -> "aa[dm] $0xA".
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if ((Name.startswith("aad") || Name.startswith("aam")) &&
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Operands.size() == 1) {
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@ -1002,16 +994,26 @@ MatchAndEmitInstruction(SMLoc IDLoc,
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Tmp += ' ';
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Op->setTokenValue(Tmp.str());
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// If this instruction starts with an 'f', then it is a floating point stack
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// instruction. These come in up to three forms for 32-bit, 64-bit, and
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// 80-bit floating point, which use the suffixes s,l,t respectively.
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//
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// Otherwise, we assume that this may be an integer instruction, which comes
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// in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
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const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
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// Check for the various suffix matches.
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Tmp[Base.size()] = 'b';
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unsigned BErrorInfo, WErrorInfo, LErrorInfo, QErrorInfo;
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MatchResultTy MatchB = MatchInstructionImpl(Operands, Inst, BErrorInfo);
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Tmp[Base.size()] = 'w';
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MatchResultTy MatchW = MatchInstructionImpl(Operands, Inst, WErrorInfo);
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Tmp[Base.size()] = 'l';
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MatchResultTy MatchL = MatchInstructionImpl(Operands, Inst, LErrorInfo);
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Tmp[Base.size()] = 'q';
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MatchResultTy MatchQ = MatchInstructionImpl(Operands, Inst, QErrorInfo);
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Tmp[Base.size()] = Suffixes[0];
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unsigned ErrorInfoIgnore;
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MatchResultTy Match1, Match2, Match3, Match4;
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Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
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Tmp[Base.size()] = Suffixes[1];
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Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
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Tmp[Base.size()] = Suffixes[2];
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Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
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Tmp[Base.size()] = Suffixes[3];
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Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
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// Restore the old token.
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Op->setTokenValue(Base);
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@ -1020,8 +1022,8 @@ MatchAndEmitInstruction(SMLoc IDLoc,
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// instruction will already have been filled in correctly, since the failing
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// matches won't have modified it).
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unsigned NumSuccessfulMatches =
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(MatchB == Match_Success) + (MatchW == Match_Success) +
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(MatchL == Match_Success) + (MatchQ == Match_Success);
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(Match1 == Match_Success) + (Match2 == Match_Success) +
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(Match3 == Match_Success) + (Match4 == Match_Success);
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if (NumSuccessfulMatches == 1) {
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Out.EmitInstruction(Inst);
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return false;
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@ -1034,14 +1036,10 @@ MatchAndEmitInstruction(SMLoc IDLoc,
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if (NumSuccessfulMatches > 1) {
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char MatchChars[4];
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unsigned NumMatches = 0;
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if (MatchB == Match_Success)
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MatchChars[NumMatches++] = 'b';
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if (MatchW == Match_Success)
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MatchChars[NumMatches++] = 'w';
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if (MatchL == Match_Success)
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MatchChars[NumMatches++] = 'l';
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if (MatchQ == Match_Success)
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MatchChars[NumMatches++] = 'q';
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if (Match1 == Match_Success) MatchChars[NumMatches++] = Suffixes[0];
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if (Match2 == Match_Success) MatchChars[NumMatches++] = Suffixes[1];
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if (Match3 == Match_Success) MatchChars[NumMatches++] = Suffixes[2];
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if (Match4 == Match_Success) MatchChars[NumMatches++] = Suffixes[3];
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SmallString<126> Msg;
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raw_svector_ostream OS(Msg);
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@ -1062,8 +1060,8 @@ MatchAndEmitInstruction(SMLoc IDLoc,
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// If all of the instructions reported an invalid mnemonic, then the original
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// mnemonic was invalid.
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if ((MatchB == Match_MnemonicFail) && (MatchW == Match_MnemonicFail) &&
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(MatchL == Match_MnemonicFail) && (MatchQ == Match_MnemonicFail)) {
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if ((Match1 == Match_MnemonicFail) && (Match2 == Match_MnemonicFail) &&
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(Match3 == Match_MnemonicFail) && (Match4 == Match_MnemonicFail)) {
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if (!WasOriginallyInvalidOperand) {
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Error(IDLoc, "invalid instruction mnemonic '" + Base + "'");
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return true;
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@ -1084,16 +1082,16 @@ MatchAndEmitInstruction(SMLoc IDLoc,
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// If one instruction matched with a missing feature, report this as a
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// missing feature.
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if ((MatchB == Match_MissingFeature) + (MatchW == Match_MissingFeature) +
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(MatchL == Match_MissingFeature) + (MatchQ == Match_MissingFeature) == 1){
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if ((Match1 == Match_MissingFeature) + (Match2 == Match_MissingFeature) +
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(Match3 == Match_MissingFeature) + (Match4 == Match_MissingFeature) == 1){
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Error(IDLoc, "instruction requires a CPU feature not currently enabled");
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return true;
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}
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// If one instruction matched with an invalid operand, report this as an
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// operand failure.
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if ((MatchB == Match_InvalidOperand) + (MatchW == Match_InvalidOperand) +
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(MatchL == Match_InvalidOperand) + (MatchQ == Match_InvalidOperand) == 1){
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if ((Match1 == Match_InvalidOperand) + (Match2 == Match_InvalidOperand) +
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(Match3 == Match_InvalidOperand) + (Match4 == Match_InvalidOperand) == 1){
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Error(IDLoc, "invalid operand for instruction");
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return true;
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}
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@ -331,11 +331,6 @@ enter $0x7ace,$1
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enter $0x7ace,$0x7f
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// rdar://8456389
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// CHECK: fstps (%eax)
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// CHECK: encoding: [0x67,0xd9,0x18]
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fstp (%eax)
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// rdar://8456364
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// CHECK: movw %cs, %ax
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mov %CS, %ax
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