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Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode.

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This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.

llvm-svn: 199193
This commit is contained in:
Craig Topper 2014-01-14 07:41:20 +00:00
parent 95dadb39e4
commit 1c1ecbff81
12 changed files with 361 additions and 330 deletions
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10
lib/Target/X86/MCTargetDesc/X86BaseInfo.h
View File

@ -355,6 +355,16 @@ namespace X86II {
// XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
XOPA = 22 << Op0Shift,
// PD - Prefix code for packed double precision vector floating point
// operations performed in the SSE registers.
PD = 23 << Op0Shift,
// T8PD - Prefix before and after 0x0F. Combination of T8 and PD.
T8PD = 24 << Op0Shift,
// TAPD - Prefix before and after 0x0F. Combination of TA and PD.
TAPD = 25 << Op0Shift,
//===------------------------------------------------------------------===//
// REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
// They are used to specify GPRs and SSE registers, 64-bit operand size,

19
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
View File

@ -717,6 +717,10 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
case X86II::TA: // 0F 3A
VEX_5M = 0x3;
break;
case X86II::T8PD: // 66 0F 38
VEX_PP = 0x1;
VEX_5M = 0x2;
break;
case X86II::T8XS: // F3 0F 38
VEX_PP = 0x2;
VEX_5M = 0x2;
@ -725,10 +729,17 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
VEX_PP = 0x3;
VEX_5M = 0x2;
break;
case X86II::TAPD: // 66 0F 3A
VEX_PP = 0x1;
VEX_5M = 0x3;
break;
case X86II::TAXD: // F2 0F 3A
VEX_PP = 0x3;
VEX_5M = 0x3;
break;
case X86II::PD: // 66 0F
VEX_PP = 0x1;
break;
case X86II::XS: // F3 0F
VEX_PP = 0x2;
break;
@ -1215,6 +1226,12 @@ void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
case X86II::A7: // 0F A7
Need0FPrefix = true;
break;
case X86II::PD: // 66 0F
case X86II::T8PD: // 66 0F 38
case X86II::TAPD: // 66 0F 3A
EmitByte(0x66, CurByte, OS);
Need0FPrefix = true;
break;
case X86II::XS: // F3 0F
case X86II::T8XS: // F3 0F 38
EmitByte(0xF3, CurByte, OS);
@ -1252,11 +1269,13 @@ void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
// FIXME: Pull this up into previous switch if REX can be moved earlier.
switch (TSFlags & X86II::Op0Mask) {
case X86II::T8PD: // 66 0F 38
case X86II::T8XS: // F3 0F 38
case X86II::T8XD: // F2 0F 38
case X86II::T8: // 0F 38
EmitByte(0x38, CurByte, OS);
break;
case X86II::TAPD: // 66 0F 3A
case X86II::TAXD: // F2 0F 3A
case X86II::TA: // 0F 3A
EmitByte(0x3A, CurByte, OS);

19
lib/Target/X86/X86CodeEmitter.cpp
View File

@ -696,6 +696,12 @@ void Emitter<CodeEmitter>::emitOpcodePrefix(uint64_t TSFlags,
Need0FPrefix = true;
break;
case X86II::REP: break; // already handled.
case X86II::PD: // 66 0F
case X86II::T8PD: // 66 0F 38
case X86II::TAPD: // 66 0F 3A
MCE.emitByte(0x66);
Need0FPrefix = true;
break;
case X86II::T8XS: // F3 0F 38
case X86II::XS: // F3 0F
MCE.emitByte(0xF3);
@ -728,11 +734,13 @@ void Emitter<CodeEmitter>::emitOpcodePrefix(uint64_t TSFlags,
MCE.emitByte(0x0F);
switch (Desc->TSFlags & X86II::Op0Mask) {
case X86II::T8PD: // 66 0F 38
case X86II::T8XD: // F2 0F 38
case X86II::T8XS: // F3 0F 38
case X86II::T8: // 0F 38
MCE.emitByte(0x38);
break;
case X86II::TAPD: // 66 0F 38
case X86II::TAXD: // F2 0F 38
case X86II::TA: // 0F 3A
MCE.emitByte(0x3A);
@ -882,6 +890,10 @@ void Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags,
case X86II::TA: // 0F 3A
VEX_5M = 0x3;
break;
case X86II::T8PD: // 66 0F 38
VEX_PP = 0x1;
VEX_5M = 0x2;
break;
case X86II::T8XS: // F3 0F 38
VEX_PP = 0x2;
VEX_5M = 0x2;
@ -890,10 +902,17 @@ void Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags,
VEX_PP = 0x3;
VEX_5M = 0x2;
break;
case X86II::TAPD: // 66 0F 3A
VEX_PP = 0x1;
VEX_5M = 0x3;
break;
case X86II::TAXD: // F2 0F 3A
VEX_PP = 0x3;
VEX_5M = 0x3;
break;
case X86II::PD: // 66 0F
VEX_PP = 0x1;
break;
case X86II::XS: // F3 0F
VEX_PP = 0x2;
break;

80
lib/Target/X86/X86InstrAVX512.td
View File

@ -744,12 +744,12 @@ multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
memopv8i64, X86pcmpeqm, v8i64>, T8PD, EVEX_V512, VEX_W;
defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
memopv8i64, X86pcmpgtm, v8i64>, T8PD, EVEX_V512, VEX_W;
def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
(COPY_TO_REGCLASS (VPCMPGTDZrr
@ -843,7 +843,7 @@ multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
"ps", SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
"pd", SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
"pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
EVEX_CD8<64, CD8VF>;
def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
@ -1103,7 +1103,7 @@ multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
VEX_4V, VEX_L, OpSize, TB;
VEX_4V, VEX_L, PD;
}
defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
@ -1155,7 +1155,7 @@ multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
SDNode OpNode> {
defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
VEX, OpSize, TA, VEX_W;
VEX, TAPD, VEX_W;
}
defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
@ -1228,14 +1228,14 @@ defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f3
EVEX_V512, EVEX_CD8<32, CD8VF>;
defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
"vmovapd", SSEPackedDouble>,
OpSize, EVEX_V512, VEX_W,
PD, EVEX_V512, VEX_W,
EVEX_CD8<64, CD8VF>;
defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
"vmovups", SSEPackedSingle>,
EVEX_V512, EVEX_CD8<32, CD8VF>;
defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
"vmovupd", SSEPackedDouble>,
OpSize, EVEX_V512, VEX_W,
PD, EVEX_V512, VEX_W,
EVEX_CD8<64, CD8VF>;
def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
"vmovaps\t{$src, $dst|$dst, $src}",
@ -1245,7 +1245,7 @@ def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$sr
"vmovapd\t{$src, $dst|$dst, $src}",
[(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
SSEPackedDouble>, EVEX, EVEX_V512,
OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
PD, VEX_W, EVEX_CD8<64, CD8VF>;
def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
"vmovups\t{$src, $dst|$dst, $src}",
[(store (v16f32 VR512:$src), addr:$dst)],
@ -1254,7 +1254,7 @@ def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$sr
"vmovupd\t{$src, $dst|$dst, $src}",
[(store (v8f64 VR512:$src), addr:$dst)],
SSEPackedDouble>, EVEX, EVEX_V512,
OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
PD, VEX_W, EVEX_CD8<64, CD8VF>;
let hasSideEffects = 0 in {
def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
@ -1421,7 +1421,7 @@ def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
"vmovq\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
(iPTR 0)))],
IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
Requires<[HasAVX512, In64BitMode]>;
def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
@ -1429,7 +1429,7 @@ def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
"vmovq\t{$src, $dst|$dst, $src}",
[(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
addr:$dst)], IIC_SSE_MOVDQ>,
EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
// Move Scalar Single to Double Int
@ -1770,7 +1770,7 @@ defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
@ -1781,7 +1781,7 @@ defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8PD,
EVEX_V512, EVEX_CD8<64, CD8VF>;
defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
@ -1800,31 +1800,31 @@ def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VR512, memopv16i32,
i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VR512, memopv8i64,
i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VR512, memopv16i32,
i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VR512, memopv8i64,
i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VR512, memopv16i32,
i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VR512, memopv8i64,
i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VR512, memopv16i32,
i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VR512, memopv8i64,
i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
T8, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
(v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
@ -1876,13 +1876,13 @@ defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
@ -1935,15 +1935,15 @@ multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
}
defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
let ExeDomain = SSEPackedSingle in
defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
EVEX_CD8<32, CD8VF>;
let ExeDomain = SSEPackedDouble in
defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
VEX_W, EVEX_CD8<32, CD8VF>;
def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
@ -2038,7 +2038,7 @@ defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
SSE_ALU_ITINS_P.d, 1>,
EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
@ -2046,7 +2046,7 @@ defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
SSE_ALU_ITINS_P.d, 1>,
EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
@ -2060,11 +2060,11 @@ defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
SSE_ALU_ITINS_P.d, 1>,
EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
SSE_ALU_ITINS_P.d, 1>,
EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
@ -2076,11 +2076,11 @@ defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
SSE_ALU_ITINS_P.d, 0>,
EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
SSE_ALU_ITINS_P.d, 0>,
EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
(v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
@ -2840,7 +2840,7 @@ let hasSideEffects = 0 in {
defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
memopv8f64, f512mem, v8f32, v8f64,
SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
SSEPackedSingle>, EVEX_V512, VEX_W, PD,
EVEX_CD8<64, CD8VF>;
defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
@ -2877,7 +2877,7 @@ defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
memopv8f64, f512mem, v8i32, v8f64,
SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
SSEPackedDouble>, EVEX_V512, PD, VEX_W,
EVEX_CD8<64, CD8VF>;
defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
@ -2946,7 +2946,7 @@ let hasSideEffects = 0 in {
}
defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
memopv16f32, f512mem, SSEPackedSingle>, OpSize,
memopv16f32, f512mem, SSEPackedSingle>, PD,
EVEX_V512, EVEX_CD8<32, CD8VF>;
defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
@ -3019,14 +3019,14 @@ let Defs = [EFLAGS], Predicates = [HasAVX512] in {
"ucomiss">, TB, EVEX, VEX_LIG,
EVEX_CD8<32, CD8VT1>;
defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
"ucomisd">, TB, OpSize, EVEX,
"ucomisd">, PD, EVEX,
VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
let Pattern = []<dag> in {
defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
"comiss">, TB, EVEX, VEX_LIG,
EVEX_CD8<32, CD8VT1>;
defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
"comisd">, TB, OpSize, EVEX,
"comisd">, PD, EVEX,
VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
}
let isCodeGenOnly = 1 in {
@ -3034,14 +3034,14 @@ let Defs = [EFLAGS], Predicates = [HasAVX512] in {
load, "ucomiss">, TB, EVEX, VEX_LIG,
EVEX_CD8<32, CD8VT1>;
defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
load, "ucomisd">, TB, OpSize, EVEX,
load, "ucomisd">, PD, EVEX,
VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
load, "comiss">, TB, EVEX, VEX_LIG,
EVEX_CD8<32, CD8VT1>;
defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
load, "comisd">, TB, OpSize, EVEX,
load, "comisd">, PD, EVEX,
VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
}
}
@ -3796,7 +3796,7 @@ multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
(VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;

8
lib/Target/X86/X86InstrArithmetic.td
View File

@ -1363,21 +1363,21 @@ let hasSideEffects = 0, Predicates = [HasADX], Defs = [EFLAGS] in {
let SchedRW = [WriteALU] in {
def ADCX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
"adcx{l}\t{$src, $dst|$dst, $src}",
[], IIC_BIN_NONMEM>, T8, OpSize;
[], IIC_BIN_NONMEM>, T8PD;
def ADCX64rr : I<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
"adcx{q}\t{$src, $dst|$dst, $src}",
[], IIC_BIN_NONMEM>, T8, OpSize, REX_W, Requires<[In64BitMode]>;
[], IIC_BIN_NONMEM>, T8PD, REX_W, Requires<[In64BitMode]>;
} // SchedRW
let mayLoad = 1, SchedRW = [WriteALULd] in {
def ADCX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
"adcx{l}\t{$src, $dst|$dst, $src}",
[], IIC_BIN_MEM>, T8, OpSize;
[], IIC_BIN_MEM>, T8PD;
def ADCX64rm : I<0xF6, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"adcx{q}\t{$src, $dst|$dst, $src}",
[], IIC_BIN_MEM>, T8, OpSize, REX_W, Requires<[In64BitMode]>;
[], IIC_BIN_MEM>, T8PD, REX_W, Requires<[In64BitMode]>;
}
}

127
lib/Target/X86/X86InstrFormats.td
View File

@ -138,6 +138,9 @@ class TAXD { bits<5> Prefix = 19; }
class XOP8 { bits<5> Prefix = 20; }
class XOP9 { bits<5> Prefix = 21; }
class XOPA { bits<5> Prefix = 22; }
class PD { bits<5> Prefix = 23; }
class T8PD { bits<5> Prefix = 24; }
class TAPD { bits<5> Prefix = 25; }
class VEX { bit hasVEXPrefix = 1; }
class VEX_W { bit hasVEX_WPrefix = 1; }
class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
@ -340,6 +343,7 @@ class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
def __xs : XS;
def __xd : XD;
def __pd : PD;
// SI - SSE 1 & 2 scalar instructions
class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
@ -349,7 +353,7 @@ class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
!if(hasVEXPrefix /* VEX */, [UseAVX],
!if(!eq(Prefix, __xs.Prefix), [UseSSE1],
!if(!eq(Prefix, __xd.Prefix), [UseSSE2],
!if(hasOpSizePrefix, [UseSSE2], [UseSSE1])))));
!if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1])))));
// AVX instructions have a 'v' prefix in the mnemonic
let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
@ -373,7 +377,7 @@ class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
: I<o, F, outs, ins, asm, pattern, itin, d> {
let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
!if(hasVEXPrefix /* VEX */, [HasAVX],
!if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1])));
!if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1])));
// AVX instructions have a 'v' prefix in the mnemonic
let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
@ -383,7 +387,7 @@ class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
InstrItinClass itin, Domain d>
: I<o, F, outs, ins, asm, pattern, itin, d> {
let Predicates = !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]);
let Predicates = !if(!eq(Prefix, __pd.Prefix), [HasSSE2], [HasSSE1]);
}
// PIi8 - SSE 1 & 2 packed instructions with immediate
@ -392,7 +396,7 @@ class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
: Ii8<o, F, outs, ins, asm, pattern, itin, d> {
let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
!if(hasVEXPrefix /* VEX */, [HasAVX],
!if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1])));
!if(!eq(Prefix, __pd.Prefix), [UseSSE2], [UseSSE1])));
// AVX instructions have a 'v' prefix in the mnemonic
let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
@ -435,13 +439,13 @@ class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
// SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
// S2SI - SSE2 instructions with XS prefix.
// SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
// PDI - SSE2 instructions with TB and OpSize prefixes, packed double domain.
// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
// PDI - SSE2 instructions with PD prefix, packed double domain.
// PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix.
// VSDI - SSE2 scalar instructions with XD prefix in AVX form.
// VPDI - SSE2 vector instructions with TB and OpSize prefixes in AVX form,
// VPDI - SSE2 vector instructions with PD prefix in AVX form,
// packed double domain.
// VS2I - SSE2 scalar instructions with TB and OpSize prefixes in AVX form.
// S2I - SSE2 scalar instructions with TB and OpSize prefixes.
// VS2I - SSE2 scalar instructions with PD prefix in AVX form.
// S2I - SSE2 scalar instructions with PD prefix.
// MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as
// MMX operands.
// MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as
@ -461,11 +465,11 @@ class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
: Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
Requires<[UseSSE2]>;
class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
Requires<[UseSSE2]>;
class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
@ -477,16 +481,15 @@ class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
Requires<[HasAVX]>;
class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>, TB,
OpSize, Requires<[HasAVX]>;
: I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>,
PD, Requires<[HasAVX]>;
class VS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, TB,
OpSize, Requires<[UseAVX]>;
: I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, PD,
Requires<[UseAVX]>;
class S2I<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: I<o, F, outs, ins, asm, pattern, itin>, TB,
OpSize, Requires<[UseSSE2]>;
: I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[UseSSE2]>;
class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
@ -496,7 +499,7 @@ class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
// SSE3 Instruction Templates:
//
// S3I - SSE3 instructions with TB and OpSize prefixes.
// S3I - SSE3 instructions with PD prefixes.
// S3SI - SSE3 instructions with XS prefix.
// S3DI - SSE3 instructions with XD prefix.
@ -510,7 +513,7 @@ class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
Requires<[UseSSE3]>;
class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
Requires<[UseSSE3]>;
@ -527,11 +530,11 @@ class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
Requires<[UseSSSE3]>;
class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
Requires<[UseSSSE3]>;
class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
@ -549,11 +552,11 @@ class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
//
class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
Requires<[UseSSE41]>;
class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
Requires<[UseSSE41]>;
// SSE4.2 Instruction Templates:
@ -561,7 +564,7 @@ class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
// SS428I - SSE 4.2 instructions with T8 prefix.
class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
Requires<[UseSSE42]>;
// SS42FI - SSE 4.2 instructions with T8XD prefix.
@ -573,53 +576,53 @@ class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
// SS42AI = SSE 4.2 instructions with TA prefix
class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
Requires<[UseSSE42]>;
// AVX Instruction Templates:
// Instructions introduced in AVX (no SSE equivalent forms)
//
// AVX8I - AVX instructions with T8 and OpSize prefix.
// AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
// AVX8I - AVX instructions with T8PD prefix.
// AVXAIi8 - AVX instructions with TAPD prefix and ImmT = Imm8.
class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
Requires<[HasAVX]>;
class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
Requires<[HasAVX]>;
// AVX2 Instruction Templates:
// Instructions introduced in AVX2 (no SSE equivalent forms)
//
// AVX28I - AVX2 instructions with T8 and OpSize prefix.
// AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8.
// AVX28I - AVX2 instructions with T8PD prefix.
// AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8.
class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
Requires<[HasAVX2]>;
class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
Requires<[HasAVX2]>;
// AVX-512 Instruction Templates:
// Instructions introduced in AVX-512 (no SSE equivalent forms)
//
// AVX5128I - AVX-512 instructions with T8 and OpSize prefix.
// AVX512AIi8 - AVX-512 instructions with TA, OpSize prefix and ImmT = Imm8.
// AVX512PDI - AVX-512 instructions with TB, OpSize, double packed.
// AVX5128I - AVX-512 instructions with T8PD prefix.
// AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8.
// AVX512PDI - AVX-512 instructions with PD, double packed.
// AVX512PSI - AVX-512 instructions with TB, single packed.
// AVX512XS8I - AVX-512 instructions with T8 and XS prefixes.
// AVX512XSI - AVX-512 instructions with XS prefix, generic domain.
// AVX512BI - AVX-512 instructions with TB, OpSize, int packed domain.
// AVX512SI - AVX-512 scalar instructions with TB and OpSize prefixes.
// AVX512BI - AVX-512 instructions with PD, int packed domain.
// AVX512SI - AVX-512 scalar instructions with PD prefix.
class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
Requires<[HasAVX512]>;
class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
@ -635,28 +638,28 @@ class AVX512XDI<bits<8> o, Format F, dag outs, dag ins, string asm,
Requires<[HasAVX512]>;
class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB, OpSize,
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
Requires<[HasAVX512]>;
class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB, OpSize,
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
Requires<[HasAVX512]>;
class AVX512SI<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB, OpSize,
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, PD,
Requires<[HasAVX512]>;
class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
Requires<[HasAVX512]>;
class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB,
Requires<[HasAVX512]>;
Requires<[HasAVX512]>;
class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB,
OpSize, Requires<[HasAVX512]>;
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, PD,
Requires<[HasAVX512]>;
class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
@ -669,8 +672,8 @@ class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm,
: I<o, F, outs, ins, asm, pattern, itin, d>, TB, Requires<[HasAVX512]>;
class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag>pattern, InstrItinClass itin = NoItinerary>
: I<o, F, outs, ins, asm, pattern, itin>, T8,
OpSize, EVEX_4V, Requires<[HasAVX512]>;
: I<o, F, outs, ins, asm, pattern, itin>, T8PD,
EVEX_4V, Requires<[HasAVX512]>;
// AES Instruction Templates:
//
@ -678,36 +681,36 @@ class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
// These use the same encoding as the SSE4.2 T8 and TA encodings.
class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag>pattern, InstrItinClass itin = IIC_AES>
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
Requires<[HasAES]>;
class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
Requires<[HasAES]>;
// PCLMUL Instruction Templates
class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag>pattern, InstrItinClass itin = NoItinerary>
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
OpSize, Requires<[HasPCLMUL]>;
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
Requires<[HasPCLMUL]>;
class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag>pattern, InstrItinClass itin = NoItinerary>
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
OpSize, VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
// FMA3 Instruction Templates
class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag>pattern, InstrItinClass itin = NoItinerary>
: I<o, F, outs, ins, asm, pattern, itin>, T8,
OpSize, VEX_4V, FMASC, Requires<[HasFMA]>;
: I<o, F, outs, ins, asm, pattern, itin>, T8PD,
VEX_4V, FMASC, Requires<[HasFMA]>;
// FMA4 Instruction Templates
class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag>pattern, InstrItinClass itin = NoItinerary>
: Ii8<o, F, outs, ins, asm, pattern, itin>, TA,
OpSize, VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>;
: Ii8<o, F, outs, ins, asm, pattern, itin>, TAPD,
VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>;
// XOP 2, 3 and 4 Operand Instruction Template
class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
@ -724,8 +727,8 @@ class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
// XOP 5 operand instruction (VEX encoding!)
class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag>pattern, InstrItinClass itin = NoItinerary>
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
OpSize, VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
// X86-64 Instruction templates...
//
@ -782,7 +785,7 @@ class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
// MMXI - MMX instructions with TB prefix.
// MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
// MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
// MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
// MMX2I - MMX / SSE2 instructions with PD prefix.
// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
// MMXID - MMX instructions with XD prefix.
@ -801,7 +804,7 @@ class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
: I<o, F, outs, ins, asm, pattern, itin>, TB, REX_W, Requires<[HasMMX]>;
class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: I<o, F, outs, ins, asm, pattern, itin>, TB, OpSize, Requires<[HasMMX]>;
: I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[HasMMX]>;
class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: Ii8<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;

6
lib/Target/X86/X86InstrMMX.td
View File

@ -527,16 +527,16 @@ defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
MMX_CVT_PS_ITINS, SSEPackedSingle>, TB;
defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
MMX_CVT_PD_ITINS, SSEPackedDouble>, PD;
defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
MMX_CVT_PS_ITINS, SSEPackedSingle>, TB;
defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
MMX_CVT_PD_ITINS, SSEPackedDouble>, PD;
defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
MMX_CVT_PD_ITINS, SSEPackedDouble>, TB, OpSize;
MMX_CVT_PD_ITINS, SSEPackedDouble>, PD;
let Constraints = "$src1 = $dst" in {
defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
int_x86_sse_cvtpi2ps,

351
lib/Target/X86/X86InstrSSE.td
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File diff suppressed because it is too large Load Diff

4
lib/Target/X86/X86InstrShiftRotate.td
View File

@ -908,8 +908,8 @@ let Predicates = [HasBMI2] in {
defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, VEX_W;
defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem>, T8XD;
defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, VEX_W;
defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8, OpSize;
defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8, OpSize, VEX_W;
defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8PD;
defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8PD, VEX_W;
// Prefer RORX which is non-destructive and doesn't update EFLAGS.
let AddedComplexity = 10 in {

4
lib/Target/X86/X86InstrSystem.td
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@ -542,10 +542,10 @@ let Predicates = [HasFSGSBase, In64BitMode] in {
//===----------------------------------------------------------------------===//
// INVPCID Instruction
def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
"invpcid\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
"invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
Requires<[Not64BitMode]>;
def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
"invpcid\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
"invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
Requires<[In64BitMode]>;
//===----------------------------------------------------------------------===//

10
lib/Target/X86/X86InstrVMX.td
View File

@ -17,22 +17,22 @@
// 66 0F 38 80
def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
"invept\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
"invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
Requires<[Not64BitMode]>;
def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
"invept\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
"invept\t{$src2, $src1|$src1, $src2}", []>, T8PD,
Requires<[In64BitMode]>;
// 66 0F 38 81
def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
"invvpid\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
"invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
Requires<[Not64BitMode]>;
def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
"invvpid\t{$src2, $src1|$src1, $src2}", []>, OpSize, T8,
"invvpid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
Requires<[In64BitMode]>;
// 0F 01 C1
def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
"vmclear\t$vmcs", []>, OpSize, TB;
"vmclear\t$vmcs", []>, PD;
// OF 01 D4
def VMFUNC : I<0x01, MRM_D4, (outs), (ins), "vmfunc", []>, TB;
// 0F 01 C2

53
utils/TableGen/X86RecognizableInstr.cpp
View File

@ -80,7 +80,7 @@ namespace X86Local {
XD = 11, XS = 12,
T8 = 13, P_TA = 14,
A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
XOP8 = 20, XOP9 = 21, XOPA = 22
XOP8 = 20, XOP9 = 21, XOPA = 22, PD = 23, T8PD = 24, TAPD = 25,
};
}
@ -254,7 +254,9 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
Operands = &insn.Operands.OperandList;
IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
IsSSE = ((HasOpSizePrefix || Prefix == X86Local::PD ||
Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
(Name.find("16") == Name.npos)) ||
(Name.find("CRC32") != Name.npos);
HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
@ -309,7 +311,7 @@ InstructionContext RecognizableInstr::insnContext() const {
}
// VEX_L & VEX_W
if (HasVEX_LPrefix && HasVEX_WPrefix) {
if (HasOpSizePrefix)
if (HasOpSizePrefix || Prefix == X86Local::PD)
insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
insnContext = EVEX_KB(IC_EVEX_L_W_XS);
@ -320,7 +322,8 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = EVEX_KB(IC_EVEX_L_W);
} else if (HasVEX_LPrefix) {
// VEX_L
if (HasOpSizePrefix)
if (HasOpSizePrefix || Prefix == X86Local::PD ||
Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
insnContext = EVEX_KB(IC_EVEX_L_XS);
@ -332,7 +335,8 @@ InstructionContext RecognizableInstr::insnContext() const {
}
else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
// EVEX_L2 & VEX_W
if (HasOpSizePrefix)
if (HasOpSizePrefix || Prefix == X86Local::PD ||
Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
@ -343,10 +347,11 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = EVEX_KB(IC_EVEX_L2_W);
} else if (HasEVEX_L2Prefix) {
// EVEX_L2
if (HasOpSizePrefix)
if (HasOpSizePrefix || Prefix == X86Local::PD ||
Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
Prefix == X86Local::TAXD)
Prefix == X86Local::TAXD)
insnContext = EVEX_KB(IC_EVEX_L2_XD);
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
insnContext = EVEX_KB(IC_EVEX_L2_XS);
@ -355,7 +360,8 @@ InstructionContext RecognizableInstr::insnContext() const {
}
else if (HasVEX_WPrefix) {
// VEX_W
if (HasOpSizePrefix)
if (HasOpSizePrefix || Prefix == X86Local::PD ||
Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
insnContext = EVEX_KB(IC_EVEX_W_XS);
@ -366,7 +372,8 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = EVEX_KB(IC_EVEX_W);
}
// No L, no W
else if (HasOpSizePrefix)
else if (HasOpSizePrefix || Prefix == X86Local::PD ||
Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
insnContext = EVEX_KB(IC_EVEX_OPSIZE);
else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
Prefix == X86Local::TAXD)
@ -378,7 +385,8 @@ InstructionContext RecognizableInstr::insnContext() const {
/// eof EVEX
} else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
if (HasVEX_LPrefix && HasVEX_WPrefix) {
if (HasOpSizePrefix)
if (HasOpSizePrefix || Prefix == X86Local::PD ||
Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
insnContext = IC_VEX_L_W_OPSIZE;
else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
insnContext = IC_VEX_L_W_XS;
@ -387,11 +395,16 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = IC_VEX_L_W_XD;
else
insnContext = IC_VEX_L_W;
} else if (HasOpSizePrefix && HasVEX_LPrefix)
} else if ((HasOpSizePrefix || Prefix == X86Local::PD ||
Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
HasVEX_LPrefix)
insnContext = IC_VEX_L_OPSIZE;
else if (HasOpSizePrefix && HasVEX_WPrefix)
else if ((HasOpSizePrefix || Prefix == X86Local::PD ||
Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
HasVEX_WPrefix)
insnContext = IC_VEX_W_OPSIZE;
else if (HasOpSizePrefix)
else if (HasOpSizePrefix || Prefix == X86Local::PD ||
Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
insnContext = IC_VEX_OPSIZE;
else if (HasVEX_LPrefix &&
(Prefix == X86Local::XS || Prefix == X86Local::T8XS))
@ -419,7 +432,8 @@ InstructionContext RecognizableInstr::insnContext() const {
else
insnContext = IC_VEX;
} else if (Is64Bit || HasREX_WPrefix) {
if (HasREX_WPrefix && HasOpSizePrefix)
if (HasREX_WPrefix && (HasOpSizePrefix || Prefix == X86Local::PD ||
Prefix == X86Local::T8PD || Prefix == X86Local::TAPD))
insnContext = IC_64BIT_REXW_OPSIZE;
else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
Prefix == X86Local::T8XD ||
@ -428,7 +442,8 @@ InstructionContext RecognizableInstr::insnContext() const {
else if (HasOpSizePrefix &&
(Prefix == X86Local::XS || Prefix == X86Local::T8XS))
insnContext = IC_64BIT_XS_OPSIZE;
else if (HasOpSizePrefix)
else if (HasOpSizePrefix || Prefix == X86Local::PD ||
Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
insnContext = IC_64BIT_OPSIZE;
else if (HasAdSizePrefix)
insnContext = IC_64BIT_ADSIZE;
@ -458,7 +473,8 @@ InstructionContext RecognizableInstr::insnContext() const {
insnContext = IC_XS_OPSIZE;
else if (HasOpSizePrefix && HasAdSizePrefix)
insnContext = IC_OPSIZE_ADSIZE;
else if (HasOpSizePrefix)
else if (HasOpSizePrefix || Prefix == X86Local::PD ||
Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
insnContext = IC_OPSIZE;
else if (HasAdSizePrefix)
insnContext = IC_ADSIZE;
@ -851,7 +867,8 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
switch (Prefix) {
default: llvm_unreachable("Invalid prefix!");
// Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
// Extended two-byte opcodes can start with 66 0f, f2 0f, f3 0f, or 0f
case X86Local::PD:
case X86Local::XD:
case X86Local::XS:
case X86Local::TB:
@ -897,6 +914,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
opcodeToSet = Opcode;
break;
case X86Local::T8:
case X86Local::T8PD:
case X86Local::T8XD:
case X86Local::T8XS:
opcodeType = THREEBYTE_38;
@ -940,6 +958,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
opcodeToSet = Opcode;
break;
case X86Local::P_TA:
case X86Local::TAPD:
case X86Local::TAXD:
opcodeType = THREEBYTE_3A;
if (needsModRMForDecode(Form))