Revert "Replace a big gob of old coalescer logic with the new CoalescerPair class."

Whiny buildbots.

llvm-svn: 106710

include/llvm/CodeGen/LiveIntervalAnalysis.h

@@ -133,9 +133,10 @@ namespace llvm {
     bool conflictsWithPhysReg(const LiveInterval &li, VirtRegMap &vrm,
                               unsigned reg);
 
-    /// conflictsWithAliasRef - Similar to conflictsWithPhysRegRef except
+    /// conflictsWithSubPhysRegRef - Similar to conflictsWithPhysRegRef except
-    /// it checks for alias uses and defs.
+    /// it checks for sub-register reference and it can check use as well.
-    bool conflictsWithAliasRef(LiveInterval &li, unsigned Reg,
+    bool conflictsWithSubPhysRegRef(LiveInterval &li, unsigned Reg,
+                                    bool CheckUse,
                                    SmallPtrSet<MachineInstr*,32> &JoinedCopies);
 
     // Interval creation

include/llvm/CodeGen/RegisterCoalescer.h

@@ -165,15 +165,9 @@ namespace llvm {
     /// virtual register.
     unsigned subIdx_;
 
-    /// origDstReg_ - dstReg_ without subreg adjustments.
-    unsigned origDstReg_;
-
     /// partial_ - True when the original copy was a partial subregister copy.
     bool partial_;
 
-    /// crossClass_ - True when both regs are virtual, and newRC is constrained.
-    bool crossClass_;
-
     /// flipped_ - True when DstReg and SrcReg are reversed from the oriignal copy
     /// instruction.
     bool flipped_;
@@ -192,8 +186,7 @@ namespace llvm {
   public:
     CoalescerPair(const TargetInstrInfo &tii, const TargetRegisterInfo &tri)
       : tii_(tii), tri_(tri), dstReg_(0), srcReg_(0), subIdx_(0),
-        origDstReg_(0), partial_(false), crossClass_(false), flipped_(false),
+        partial_(false), flipped_(false), newRC_(0) {}
-        newRC_(0) {}
 
     /// setRegisters - set registers to match the copy instruction MI. Return
     /// false if MI is not a coalescable copy instruction.
@@ -214,9 +207,6 @@ namespace llvm {
     /// full register, but was a subreg operation.
     bool isPartial() const { return partial_; }
 
-    /// isCrossClass - Return true if DstReg is virtual and NewRC is a smaller register class than DstReg's.
-    bool isCrossClass() const { return crossClass_; }
-
     /// isFlipped - Return true when getSrcReg is the register being defined by
     /// the original copy instruction.
     bool isFlipped() const { return flipped_; }
@@ -232,10 +222,6 @@ namespace llvm {
     /// coalesced into, or 0.
     unsigned getSubIdx() const { return subIdx_; }
 
-    /// getOrigDstReg - Return DstReg as it appeared in the original copy
-    /// instruction before any subreg adjustments.
-    unsigned getOrigDstReg() const { return isPhys() ? origDstReg_ : dstReg_; }
-
     /// getNewRC - Return the register class of the coalesced register.
     const TargetRegisterClass *getNewRC() const { return newRC_; }
   };

lib/CodeGen/LiveIntervalAnalysis.cpp

@@ -218,7 +218,10 @@ bool LiveIntervals::conflictsWithPhysReg(const LiveInterval &li,
   return false;
 }
 
-bool LiveIntervals::conflictsWithAliasRef(LiveInterval &li, unsigned Reg,
+/// conflictsWithSubPhysRegRef - Similar to conflictsWithPhysRegRef except
+/// it checks for sub-register reference and it can check use as well.
+bool LiveIntervals::conflictsWithSubPhysRegRef(LiveInterval &li,
+                                            unsigned Reg, bool CheckUse,
                                   SmallPtrSet<MachineInstr*,32> &JoinedCopies) {
   for (LiveInterval::Ranges::const_iterator
          I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
@@ -236,11 +239,12 @@ bool LiveIntervals::conflictsWithAliasRef(LiveInterval &li, unsigned Reg,
         MachineOperand& MO = MI->getOperand(i);
         if (!MO.isReg())
           continue;
-        unsigned PhysReg = MO.getReg();
+        if (MO.isUse() && !CheckUse)
-        if (PhysReg == 0 || PhysReg == Reg ||
-            TargetRegisterInfo::isVirtualRegister(PhysReg))
           continue;
-        if (tri_->regsOverlap(Reg, PhysReg))
+        unsigned PhysReg = MO.getReg();
+        if (PhysReg == 0 || TargetRegisterInfo::isVirtualRegister(PhysReg))
+          continue;
+        if (tri_->isSubRegister(Reg, PhysReg))
           return true;
       }
     }
@@ -1280,7 +1284,6 @@ bool LiveIntervals::anyKillInMBBAfterIdx(const LiveInterval &li,
       continue;
 
     SlotIndex KillIdx = VNI->kills[j];
-    assert(getInstructionFromIndex(KillIdx) && "Dangling kill");
     if (KillIdx > Idx && KillIdx <= End)
       return true;
   }

lib/CodeGen/RegisterCoalescer.cpp

@@ -63,7 +63,7 @@ bool CoalescerPair::isMoveInstr(const MachineInstr *MI,
 bool CoalescerPair::setRegisters(const MachineInstr *MI) {
   srcReg_ = dstReg_ = subIdx_ = 0;
   newRC_ = 0;
-  flipped_ = crossClass_ = false;
+  flipped_ = false;
 
   unsigned Src, Dst, SrcSub, DstSub;
   if (!isMoveInstr(MI, Src, Dst, SrcSub, DstSub))
@@ -78,7 +78,6 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) {
     std::swap(SrcSub, DstSub);
     flipped_ = true;
   }
-  origDstReg_ = Dst;
 
   const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
 
@@ -101,19 +100,11 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) {
   } else {
     // Both registers are virtual.
 
-    // Both registers have subreg indices.
+    // Identical sub to sub.
-    if (SrcSub && DstSub) {
+    if (SrcSub == DstSub)
-      // For now we only handle the case of identical indices in commensurate
-      // registers: Dreg:ssub_1 + Dreg:ssub_1 -> Dreg
-      // FIXME: Handle Qreg:ssub_3 + Dreg:ssub_1 as QReg:dsub_1 + Dreg.
-      if (SrcSub != DstSub)
-        return false;
-      const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
-      const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
-      if (!getCommonSubClass(DstRC, SrcRC))
-        return false;
       SrcSub = DstSub = 0;
-    }
+    else if (SrcSub && DstSub)
+      return false; // FIXME: Qreg:ssub_3 + Dreg:ssub_1 => QReg:dsub_1 + Dreg.
 
     // There can be no SrcSub.
     if (SrcSub) {
@@ -133,7 +124,6 @@ bool CoalescerPair::setRegisters(const MachineInstr *MI) {
       newRC_ = getCommonSubClass(DstRC, SrcRC);
     if (!newRC_)
       return false;
-    crossClass_ = newRC_ != DstRC || newRC_ != SrcRC;
   }
   // Check our invariants
   assert(TargetRegisterInfo::isVirtualRegister(Src) && "Src must be virtual");

lib/CodeGen/SimpleRegisterCoalescing.cpp

@@ -783,11 +783,14 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
 /// being updated is not zero, make sure to set it to the correct physical
 /// subregister.
 void
-SimpleRegisterCoalescing::UpdateRegDefsUses(const CoalescerPair &CP) {
+SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
-  bool DstIsPhys = CP.isPhys();
+                                            unsigned SubIdx) {
-  unsigned SrcReg = CP.getSrcReg();
+  bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
-  unsigned DstReg = CP.getDstReg();
+  if (DstIsPhys && SubIdx) {
-  unsigned SubIdx = CP.getSubIdx();
+    // Figure out the real physical register we are updating with.
+    DstReg = tri_->getSubReg(DstReg, SubIdx);
+    SubIdx = 0;
+  }
 
   // Collect all the instructions using SrcReg.
   SmallPtrSet<MachineInstr*, 32> Instrs;
@@ -1011,6 +1014,25 @@ SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
   return removeIntervalIfEmpty(li, li_, tri_);
 }
 
+/// CanCoalesceWithImpDef - Returns true if the specified copy instruction
+/// from an implicit def to another register can be coalesced away.
+bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
+                                                     LiveInterval &li,
+                                                     LiveInterval &ImpLi) const{
+  if (!CopyMI->killsRegister(ImpLi.reg))
+    return false;
+  // Make sure this is the only use.
+  for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(ImpLi.reg),
+         UE = mri_->use_end(); UI != UE;) {
+    MachineInstr *UseMI = &*UI;
+    ++UI;
+    if (CopyMI == UseMI || JoinedCopies.count(UseMI))
+      continue;
+    return false;
+  }
+  return true;
+}
+
 
 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
 /// two virtual registers from different register classes.
@@ -1197,6 +1219,17 @@ SimpleRegisterCoalescing::CanJoinInsertSubRegToPhysReg(unsigned DstReg,
   return true;
 }
 
+/// getRegAllocPreference - Return register allocation preference register.
+///
+static unsigned getRegAllocPreference(unsigned Reg, MachineFunction &MF,
+                                      MachineRegisterInfo *MRI,
+                                      const TargetRegisterInfo *TRI) {
+  if (TargetRegisterInfo::isPhysicalRegister(Reg))
+    return 0;
+  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
+  return TRI->ResolveRegAllocHint(Hint.first, Hint.second, MF);
+}
+
 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
 /// which are the src/dst of the copy instruction CopyMI.  This returns true
 /// if the copy was successfully coalesced away. If it is not currently
@@ -1211,131 +1244,393 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
 
   DEBUG(dbgs() << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
 
+  unsigned SrcReg, DstReg, SrcSubIdx = 0, DstSubIdx = 0;
+  bool isExtSubReg = CopyMI->isExtractSubreg();
+  bool isInsSubReg = CopyMI->isInsertSubreg();
+  bool isSubRegToReg = CopyMI->isSubregToReg();
+  unsigned SubIdx = 0;
+  if (isExtSubReg) {
+    DstReg    = CopyMI->getOperand(0).getReg();
+    DstSubIdx = CopyMI->getOperand(0).getSubReg();
+    SrcReg    = CopyMI->getOperand(1).getReg();
+    SrcSubIdx = CopyMI->getOperand(2).getImm();
+  } else if (isInsSubReg || isSubRegToReg) {
+    DstReg    = CopyMI->getOperand(0).getReg();
+    DstSubIdx = CopyMI->getOperand(3).getImm();
+    SrcReg    = CopyMI->getOperand(2).getReg();
+    SrcSubIdx = CopyMI->getOperand(2).getSubReg();
+    if (SrcSubIdx && SrcSubIdx != DstSubIdx) {
+      // r1025 = INSERT_SUBREG r1025, r1024<2>, 2 Then r1024 has already been
+      // coalesced to a larger register so the subreg indices cancel out.
+      DEBUG(dbgs() << "\tSource of insert_subreg or subreg_to_reg is already "
+                      "coalesced to another register.\n");
+      return false;  // Not coalescable.
+    }
+  } else if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
+    if (SrcSubIdx && DstSubIdx && SrcSubIdx != DstSubIdx) {
+      // e.g. %reg16404:1<def> = MOV8rr %reg16412:2<kill>
+      Again = true;
+      return false;  // Not coalescable.
+    }
+  } else {
+    llvm_unreachable("Unrecognized copy instruction!");
+  }
+
+  // If they are already joined we continue.
+  if (SrcReg == DstReg) {
+    DEBUG(dbgs() << "\tCopy already coalesced.\n");
+    return false;  // Not coalescable.
+  }
+
   CoalescerPair CP(*tii_, *tri_);
   if (!CP.setRegisters(CopyMI)) {
     DEBUG(dbgs() << "\tNot coalescable.\n");
     return false;
   }
 
-  // If they are already joined we continue.
+  bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
-  if (CP.getSrcReg() == CP.getDstReg()) {
+  bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
-    DEBUG(dbgs() << "\tCopy already coalesced.\n");
+
+  // If they are both physical registers, we cannot join them.
+  if (SrcIsPhys && DstIsPhys) {
+    DEBUG(dbgs() << "\tCan not coalesce physregs.\n");
     return false;  // Not coalescable.
   }
 
-  DEBUG(dbgs() << "\tConsidering merging %reg" << CP.getSrcReg());
+  // We only join virtual registers with allocatable physical registers.
+  if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
+    DEBUG(dbgs() << "\tSrc reg is unallocatable physreg.\n");
+    return false;  // Not coalescable.
+  }
+  if (DstIsPhys && !allocatableRegs_[DstReg]) {
+    DEBUG(dbgs() << "\tDst reg is unallocatable physreg.\n");
+    return false;  // Not coalescable.
+  }
 
-  // Enforce policies.
+  // We cannot handle dual subreg indices and mismatched classes at the same
-  if (CP.isPhys()) {
+  // time.
-    DEBUG(dbgs() <<" with physreg %" << tri_->getName(CP.getDstReg()) << "\n");
+  if (SrcSubIdx && DstSubIdx && differingRegisterClasses(SrcReg, DstReg)) {
-    // Only coalesce to allocatable physreg.
+    DEBUG(dbgs() << "\tCannot handle subreg indices and mismatched classes.\n");
-    if (!allocatableRegs_[CP.getDstReg()]) {
+    return false;
-      DEBUG(dbgs() << "\tRegister is an unallocatable physreg.\n");
+  }
-      return false;  // Not coalescable.
+
+  // Check that a physical source register is compatible with dst regclass
+  if (SrcIsPhys) {
+    unsigned SrcSubReg = SrcSubIdx ?
+      tri_->getSubReg(SrcReg, SrcSubIdx) : SrcReg;
+    const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
+    const TargetRegisterClass *DstSubRC = DstRC;
+    if (DstSubIdx)
+      DstSubRC = DstRC->getSubRegisterRegClass(DstSubIdx);
+    assert(DstSubRC && "Illegal subregister index");
+    if (!DstSubRC->contains(SrcSubReg)) {
+      DEBUG(dbgs() << "\tIncompatible destination regclass: "
+                   << "none of the super-registers of "
+                   << tri_->getName(SrcSubReg) << " are in "
+                   << DstSubRC->getName() << ".\n");
+      return false;             // Not coalescable.
     }
-  } else {
+  }
-    DEBUG({
-      dbgs() << " with reg%" << CP.getDstReg();
-      if (CP.getSubIdx())
-        dbgs() << ":" << tri_->getSubRegIndexName(CP.getSubIdx());
-      dbgs() << " to " << CP.getNewRC()->getName() << "\n";
-    });
 
-    // Avoid constraining virtual register regclass too much.
+  // Check that a physical dst register is compatible with source regclass
-    if (CP.isCrossClass()) {
+  if (DstIsPhys) {
-      if (DisableCrossClassJoin) {
+    unsigned DstSubReg = DstSubIdx ?
-        DEBUG(dbgs() << "\tCross-class joins disabled.\n");
+      tri_->getSubReg(DstReg, DstSubIdx) : DstReg;
-        return false;
+    const TargetRegisterClass *SrcRC = mri_->getRegClass(SrcReg);
+    const TargetRegisterClass *SrcSubRC = SrcRC;
+    if (SrcSubIdx)
+      SrcSubRC = SrcRC->getSubRegisterRegClass(SrcSubIdx);
+    assert(SrcSubRC && "Illegal subregister index");
+    if (!SrcSubRC->contains(DstSubReg)) {
+      DEBUG(dbgs() << "\tIncompatible source regclass: "
+                   << "none of the super-registers of "
+                   << tri_->getName(DstSubReg) << " are in "
+                   << SrcSubRC->getName() << ".\n");
+      (void)DstSubReg;
+      return false;             // Not coalescable.
+    }
+  }
+
+  // Should be non-null only when coalescing to a sub-register class.
+  bool CrossRC = false;
+  const TargetRegisterClass *SrcRC= SrcIsPhys ? 0 : mri_->getRegClass(SrcReg);
+  const TargetRegisterClass *DstRC= DstIsPhys ? 0 : mri_->getRegClass(DstReg);
+  const TargetRegisterClass *NewRC = NULL;
+  unsigned RealDstReg = 0;
+  unsigned RealSrcReg = 0;
+  if (isExtSubReg || isInsSubReg || isSubRegToReg) {
+    SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
+    if (SrcIsPhys && isExtSubReg) {
+      // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
+      // coalesced with AX.
+      unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
+      if (DstSubIdx) {
+        // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
+        // coalesced to a larger register so the subreg indices cancel out.
+        if (DstSubIdx != SubIdx) {
+          DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
+          return false; // Not coalescable.
+        }
+      } else
+        SrcReg = tri_->getSubReg(SrcReg, SubIdx);
+      SubIdx = 0;
+    } else if (DstIsPhys && (isInsSubReg || isSubRegToReg)) {
+      // EAX = INSERT_SUBREG EAX, r1024, 0
+      unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
+      if (SrcSubIdx) {
+        // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
+        // coalesced to a larger register so the subreg indices cancel out.
+        if (SrcSubIdx != SubIdx) {
+          DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
+          return false; // Not coalescable.
+        }
+      } else
+        DstReg = tri_->getSubReg(DstReg, SubIdx);
+      SubIdx = 0;
+    } else if ((DstIsPhys && isExtSubReg) ||
+               (SrcIsPhys && (isInsSubReg || isSubRegToReg))) {
+      if (!isSubRegToReg && CopyMI->getOperand(1).getSubReg()) {
+        DEBUG(dbgs() << "\tSrc of extract_subreg already coalesced with reg"
+                     << " of a super-class.\n");
+        return false; // Not coalescable.
       }
-      if (!isWinToJoinCrossClass(CP.getSrcReg(), CP.getDstReg(),
+
-                                 mri_->getRegClass(CP.getSrcReg()),
+      // FIXME: The following checks are somewhat conservative. Perhaps a better
-                                 mri_->getRegClass(CP.getDstReg()),
+      // way to implement this is to treat this as coalescing a vr with the
-                                 CP.getNewRC())) {
+      // super physical register.
+      if (isExtSubReg) {
+        if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealDstReg))
+          return false; // Not coalescable
+      } else {
+        if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
+          return false; // Not coalescable
+      }
+      SubIdx = 0;
+    } else {
+      unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg()
+        : CopyMI->getOperand(2).getSubReg();
+      if (OldSubIdx) {
+        if (OldSubIdx == SubIdx && !differingRegisterClasses(SrcReg, DstReg))
+          // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been
+          // coalesced to a larger register so the subreg indices cancel out.
+          // Also check if the other larger register is of the same register
+          // class as the would be resulting register.
+          SubIdx = 0;
+        else {
+          DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
+          return false; // Not coalescable.
+        }
+      }
+      if (SubIdx) {
+        if (!DstIsPhys && !SrcIsPhys) {
+          if (isInsSubReg || isSubRegToReg) {
+            NewRC = tri_->getMatchingSuperRegClass(DstRC, SrcRC, SubIdx);
+          } else // extract_subreg {
+            NewRC = tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx);
+          }
+        if (!NewRC) {
+          DEBUG(dbgs() << "\t Conflicting sub-register indices.\n");
+          return false;  // Not coalescable
+        }
+
+        if (!isWinToJoinCrossClass(SrcReg, DstReg, SrcRC, DstRC, NewRC)) {
+          DEBUG(dbgs() << "\tAvoid coalescing to constrained register class: "
+                       << SrcRC->getName() << "/"
+                       << DstRC->getName() << " -> "
+                       << NewRC->getName() << ".\n");
+          Again = true;  // May be possible to coalesce later.
+          return false;
+        }
+      }
+    }
+  } else if (differingRegisterClasses(SrcReg, DstReg)) {
+    if (DisableCrossClassJoin)
+      return false;
+    CrossRC = true;
+
+    // FIXME: What if the result of a EXTRACT_SUBREG is then coalesced
+    // with another? If it's the resulting destination register, then
+    // the subidx must be propagated to uses (but only those defined
+    // by the EXTRACT_SUBREG). If it's being coalesced into another
+    // register, it should be safe because register is assumed to have
+    // the register class of the super-register.
+
+    // Process moves where one of the registers have a sub-register index.
+    MachineOperand *DstMO = CopyMI->findRegisterDefOperand(DstReg);
+    MachineOperand *SrcMO = CopyMI->findRegisterUseOperand(SrcReg);
+    SubIdx = DstMO->getSubReg();
+    if (SubIdx) {
+      if (SrcMO->getSubReg())
+        // FIXME: can we handle this?
+        return false;
+      // This is not an insert_subreg but it looks like one.
+      // e.g. %reg1024:4 = MOV32rr %EAX
+      isInsSubReg = true;
+      if (SrcIsPhys) {
+        if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
+          return false; // Not coalescable
+        SubIdx = 0;
+      }
+    } else {
+      SubIdx = SrcMO->getSubReg();
+      if (SubIdx) {
+        // This is not a extract_subreg but it looks like one.
+        // e.g. %cl = MOV16rr %reg1024:1
+        isExtSubReg = true;
+        if (DstIsPhys) {
+          if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx,RealDstReg))
+            return false; // Not coalescable
+          SubIdx = 0;
+        }
+      }
+    }
+
+    // Now determine the register class of the joined register.
+    if (!SrcIsPhys && !DstIsPhys) {
+      if (isExtSubReg) {
+        NewRC =
+          SubIdx ? tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx) : SrcRC;
+      } else if (isInsSubReg) {
+        NewRC =
+          SubIdx ? tri_->getMatchingSuperRegClass(DstRC, SrcRC, SubIdx) : DstRC;
+      } else {
+        NewRC = getCommonSubClass(SrcRC, DstRC);
+      }
+
+      if (!NewRC) {
+        DEBUG(dbgs() << "\tDisjoint regclasses: "
+                     << SrcRC->getName() << ", "
+                     << DstRC->getName() << ".\n");
+        return false;           // Not coalescable.
+      }
+
+      // If we are joining two virtual registers and the resulting register
+      // class is more restrictive (fewer register, smaller size). Check if it's
+      // worth doing the merge.
+      if (!isWinToJoinCrossClass(SrcReg, DstReg, SrcRC, DstRC, NewRC)) {
         DEBUG(dbgs() << "\tAvoid coalescing to constrained register class: "
-                     << CP.getNewRC()->getName() << ".\n");
+                     << SrcRC->getName() << "/"
+                     << DstRC->getName() << " -> "
+                     << NewRC->getName() << ".\n");
+        // Allow the coalescer to try again in case either side gets coalesced to
+        // a physical register that's compatible with the other side. e.g.
+        // r1024 = MOV32to32_ r1025
+        // But later r1024 is assigned EAX then r1025 may be coalesced with EAX.
         Again = true;  // May be possible to coalesce later.
         return false;
       }
     }
-
-    // When possible, let DstReg be the larger interval.
-    if (!CP.getSubIdx() && li_->getInterval(CP.getSrcReg()).ranges.size() >
-                           li_->getInterval(CP.getDstReg()).ranges.size())
-      CP.flip();
   }
 
-  // We need to be careful about coalescing a source physical register with a
+  // Will it create illegal extract_subreg / insert_subreg?
-  // virtual register. Once the coalescing is done, it cannot be broken and
+  if (SrcIsPhys && HasIncompatibleSubRegDefUse(CopyMI, DstReg, SrcReg))
-  // these are not spillable! If the destination interval uses are far away,
+    return false;
-  // think twice about coalescing them!
+  if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg))
-  // FIXME: Why are we skipping this test for partial copies?
+    return false;
-  //        CodeGen/X86/phys_subreg_coalesce-3.ll needs it.
-  if (!CP.isPartial() && CP.isPhys()) {
-    LiveInterval &JoinVInt = li_->getInterval(CP.getSrcReg());
 
-    // Don't join with physregs that have a ridiculous number of live
+  LiveInterval &SrcInt = li_->getInterval(SrcReg);
-    // ranges. The data structure performance is really bad when that
+  LiveInterval &DstInt = li_->getInterval(DstReg);
-    // happens.
+  assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
-    if (li_->hasInterval(CP.getDstReg()) &&
+         "Register mapping is horribly broken!");
-        li_->getInterval(CP.getDstReg()).ranges.size() > 1000) {
-      mri_->setRegAllocationHint(CP.getSrcReg(), 0, CP.getDstReg());
-      ++numAborts;
-      DEBUG(dbgs()
-           << "\tPhysical register live interval too complicated, abort!\n");
-      return false;
-    }
 
-    const TargetRegisterClass *RC = mri_->getRegClass(CP.getSrcReg());
+  DEBUG({
-    unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
+      dbgs() << "\t\tInspecting ";
-    unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
+      if (SrcRC) dbgs() << SrcRC->getName() << ": ";
-    if (Length > Threshold &&
+      SrcInt.print(dbgs(), tri_);
-        std::distance(mri_->use_nodbg_begin(CP.getSrcReg()),
+      dbgs() << "\n\t\t       and ";
-                      mri_->use_nodbg_end()) * Threshold < Length) {
+      if (DstRC) dbgs() << DstRC->getName() << ": ";
-      // Before giving up coalescing, if definition of source is defined by
+      DstInt.print(dbgs(), tri_);
-      // trivial computation, try rematerializing it.
+      dbgs() << "\n";
-      if (!CP.isFlipped() &&
+    });
-          ReMaterializeTrivialDef(JoinVInt, CP.getDstReg(), 0, CopyMI))
-        return true;
 
-      mri_->setRegAllocationHint(CP.getSrcReg(), 0, CP.getDstReg());
+  // Save a copy of the virtual register live interval. We'll manually
-      ++numAborts;
+  // merge this into the "real" physical register live interval this is
-      DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
+  // coalesced with.
-      Again = true;  // May be possible to coalesce later.
-      return false;
-    }
-  }
-
-  // We may need the source interval after JoinIntervals has destroyed it.
   OwningPtr<LiveInterval> SavedLI;
-  if (CP.getOrigDstReg() != CP.getDstReg())
+  if (RealDstReg)
-    SavedLI.reset(li_->dupInterval(&li_->getInterval(CP.getSrcReg())));
+    SavedLI.reset(li_->dupInterval(&SrcInt));
+  else if (RealSrcReg)
+    SavedLI.reset(li_->dupInterval(&DstInt));
+
+  if (!isExtSubReg && !isInsSubReg && !isSubRegToReg) {
+    // Check if it is necessary to propagate "isDead" property.
+    MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
+    bool isDead = mopd->isDead();
+
+    // We need to be careful about coalescing a source physical register with a
+    // virtual register. Once the coalescing is done, it cannot be broken and
+    // these are not spillable! If the destination interval uses are far away,
+    // think twice about coalescing them!
+    if (!isDead && (SrcIsPhys || DstIsPhys)) {
+      // If the virtual register live interval is long but it has low use
+      // density, do not join them, instead mark the physical register as its
+      // allocation preference.
+      LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
+      LiveInterval &JoinPInt = SrcIsPhys ? SrcInt : DstInt;
+      unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
+      unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
+
+      // Don't join with physregs that have a ridiculous number of live
+      // ranges. The data structure performance is really bad when that
+      // happens.
+      if (JoinPInt.ranges.size() > 1000) {
+        mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
+        ++numAborts;
+        DEBUG(dbgs()
+              << "\tPhysical register live interval too complicated, abort!\n");
+        return false;
+      }
+
+      const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
+      unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
+      unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
+      if (Length > Threshold &&
+          std::distance(mri_->use_nodbg_begin(JoinVReg),
+                        mri_->use_nodbg_end()) * Threshold < Length) {
+        // Before giving up coalescing, if definition of source is defined by
+        // trivial computation, try rematerializing it.
+        if (ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI))
+          return true;
+
+        mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
+        ++numAborts;
+        DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
+        Again = true;  // May be possible to coalesce later.
+        return false;
+      }
+    }
+  }
 
   // Okay, attempt to join these two intervals.  On failure, this returns false.
   // Otherwise, if one of the intervals being joined is a physreg, this method
   // always canonicalizes DstInt to be it.  The output "SrcInt" will not have
   // been modified, so we can use this information below to update aliases.
-  if (!JoinIntervals(CP)) {
+  bool Swapped = false;
+  // If SrcInt is implicitly defined, it's safe to coalesce.
+  if (SrcInt.empty()) {
+    if (!CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
+      // Only coalesce an empty interval (defined by implicit_def) with
+      // another interval which has a valno defined by the CopyMI and the CopyMI
+      // is a kill of the implicit def.
+      DEBUG(dbgs() << "\tNot profitable!\n");
+      return false;
+    }
+  } else if (!JoinIntervals(DstInt, SrcInt, Swapped, CP)) {
     // Coalescing failed.
 
     // If definition of source is defined by trivial computation, try
     // rematerializing it.
-    if (!CP.isFlipped() &&
+    if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
-        ReMaterializeTrivialDef(li_->getInterval(CP.getSrcReg()),
+        ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI))
-                                CP.getDstReg(), 0, CopyMI))
       return true;
 
     // If we can eliminate the copy without merging the live ranges, do so now.
-    if (!CP.isPartial()) {
+    if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
-      LiveInterval *UseInt = &li_->getInterval(CP.getSrcReg());
+        (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
-      LiveInterval *DefInt = &li_->getInterval(CP.getDstReg());
+         RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
-      if (CP.isFlipped())
+      JoinedCopies.insert(CopyMI);
-        std::swap(UseInt, DefInt);
+      DEBUG(dbgs() << "\tTrivial!\n");
-      if (AdjustCopiesBackFrom(*UseInt, *DefInt, CopyMI) ||
+      return true;
-          RemoveCopyByCommutingDef(*UseInt, *DefInt, CopyMI)) {
-        JoinedCopies.insert(CopyMI);
-        DEBUG(dbgs() << "\tTrivial!\n");
-        return true;
-      }
     }
 
     // Otherwise, we are unable to join the intervals.
@@ -1344,15 +1639,25 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
     return false;
   }
 
-  if (CP.isPhys()) {
+  LiveInterval *ResSrcInt = &SrcInt;
+  LiveInterval *ResDstInt = &DstInt;
+  if (Swapped) {
+    std::swap(SrcReg, DstReg);
+    std::swap(ResSrcInt, ResDstInt);
+  }
+  assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
+         "LiveInterval::join didn't work right!");
+
+  // If we're about to merge live ranges into a physical register live interval,
+  // we have to update any aliased register's live ranges to indicate that they
+  // have clobbered values for this range.
+  if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
     // If this is a extract_subreg where dst is a physical register, e.g.
     // cl = EXTRACT_SUBREG reg1024, 1
     // then create and update the actual physical register allocated to RHS.
-    unsigned LargerDstReg = CP.getDstReg();
+    if (RealDstReg || RealSrcReg) {
-    if (CP.getOrigDstReg() != CP.getDstReg()) {
+      LiveInterval &RealInt =
-      if (tri_->isSubRegister(CP.getOrigDstReg(), LargerDstReg))
+        li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg);
-        LargerDstReg = CP.getOrigDstReg();
-      LiveInterval &RealInt = li_->getOrCreateInterval(CP.getDstReg());
       for (LiveInterval::const_vni_iterator I = SavedLI->vni_begin(),
              E = SavedLI->vni_end(); I != E; ++I) {
         const VNInfo *ValNo = *I;
@@ -1364,45 +1669,56 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
         RealInt.MergeValueInAsValue(*SavedLI, ValNo, NewValNo);
       }
       RealInt.weight += SavedLI->weight;
+      DstReg = RealDstReg ? RealDstReg : RealSrcReg;
     }
 
     // Update the liveintervals of sub-registers.
-    LiveInterval &LargerInt = li_->getInterval(LargerDstReg);
+    for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
-    for (const unsigned *AS = tri_->getSubRegisters(LargerDstReg); *AS; ++AS) {
+      li_->getOrCreateInterval(*AS).MergeInClobberRanges(*li_, *ResSrcInt,
-      LiveInterval &SRI = li_->getOrCreateInterval(*AS);
+                                                 li_->getVNInfoAllocator());
-      SRI.MergeInClobberRanges(*li_, LargerInt, li_->getVNInfoAllocator());
+  }
-      DEBUG({
+
-        dbgs() << "\t\tsubreg: "; SRI.print(dbgs(), tri_); dbgs() << "\n";
+  // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
-      });
+  // larger super-register.
+  if ((isExtSubReg || isInsSubReg || isSubRegToReg) &&
+      !SrcIsPhys && !DstIsPhys) {
+    if ((isExtSubReg && !Swapped) ||
+        ((isInsSubReg || isSubRegToReg) && Swapped)) {
+      ResSrcInt->Copy(*ResDstInt, mri_, li_->getVNInfoAllocator());
+      std::swap(SrcReg, DstReg);
+      std::swap(ResSrcInt, ResDstInt);
     }
   }
 
   // Coalescing to a virtual register that is of a sub-register class of the
   // other. Make sure the resulting register is set to the right register class.
-  if (CP.isCrossClass()) {
+  if (CrossRC)
     ++numCrossRCs;
-    mri_->setRegClass(CP.getDstReg(), CP.getNewRC());
+
-  }
+  // This may happen even if it's cross-rc coalescing. e.g.
+  // %reg1026<def> = SUBREG_TO_REG 0, %reg1037<kill>, 4
+  // reg1026 -> GR64, reg1037 -> GR32_ABCD. The resulting register will have to
+  // be allocate a register from GR64_ABCD.
+  if (NewRC)
+    mri_->setRegClass(DstReg, NewRC);
 
   // Remember to delete the copy instruction.
   JoinedCopies.insert(CopyMI);
 
-  UpdateRegDefsUses(CP);
+  UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
 
   // If we have extended the live range of a physical register, make sure we
   // update live-in lists as well.
-  if (CP.isPhys()) {
+  if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
+    const LiveInterval &VRegInterval = li_->getInterval(SrcReg);
     SmallVector<MachineBasicBlock*, 16> BlockSeq;
-    // JoinIntervals invalidates the VNInfos in SrcInt, but we only need the
+    for (LiveInterval::const_iterator I = VRegInterval.begin(),
-    // ranges for this, and they are preserved.
+           E = VRegInterval.end(); I != E; ++I ) {
-    LiveInterval &SrcInt = li_->getInterval(CP.getSrcReg());
-    for (LiveInterval::const_iterator I = SrcInt.begin(), E = SrcInt.end();
-         I != E; ++I ) {
       li_->findLiveInMBBs(I->start, I->end, BlockSeq);
       for (unsigned idx = 0, size = BlockSeq.size(); idx != size; ++idx) {
         MachineBasicBlock &block = *BlockSeq[idx];
-        if (!block.isLiveIn(CP.getDstReg()))
+        if (!block.isLiveIn(DstReg))
-          block.addLiveIn(CP.getDstReg());
+          block.addLiveIn(DstReg);
       }
       BlockSeq.clear();
     }
@@ -1410,17 +1726,32 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
 
   // SrcReg is guarateed to be the register whose live interval that is
   // being merged.
-  li_->removeInterval(CP.getSrcReg());
+  li_->removeInterval(SrcReg);
 
   // Update regalloc hint.
-  tri_->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *mf_);
+  tri_->UpdateRegAllocHint(SrcReg, DstReg, *mf_);
+
+  // Manually deleted the live interval copy.
+  if (SavedLI) {
+    SavedLI->clear();
+    SavedLI.reset();
+  }
+
+  // If resulting interval has a preference that no longer fits because of subreg
+  // coalescing, just clear the preference.
+  unsigned Preference = getRegAllocPreference(ResDstInt->reg, *mf_, mri_, tri_);
+  if (Preference && (isExtSubReg || isInsSubReg || isSubRegToReg) &&
+      TargetRegisterInfo::isVirtualRegister(ResDstInt->reg)) {
+    const TargetRegisterClass *RC = mri_->getRegClass(ResDstInt->reg);
+    if (!RC->contains(Preference))
+      mri_->setRegAllocationHint(ResDstInt->reg, 0, 0);
+  }
 
   DEBUG({
-    LiveInterval &DstInt = li_->getInterval(CP.getDstReg());
+      dbgs() << "\t\tJoined. Result = ";
-    dbgs() << "\tJoined. Result = ";
+      ResDstInt->print(dbgs(), tri_);
-    DstInt.print(dbgs(), tri_);
+      dbgs() << "\n";
-    dbgs() << "\n";
+    });
-  });
 
   ++numJoins;
   return true;
@@ -1478,24 +1809,26 @@ static unsigned ComputeUltimateVN(VNInfo *VNI,
 }
 
 /// JoinIntervals - Attempt to join these two intervals.  On failure, this
-/// returns false.
+/// returns false.  Otherwise, if one of the intervals being joined is a
-bool SimpleRegisterCoalescing::JoinIntervals(CoalescerPair &CP) {
+/// physreg, this method always canonicalizes LHS to be it.  The output
-  LiveInterval &RHS = li_->getInterval(CP.getSrcReg());
+/// "RHS" will not have been modified, so we can use this information
-  DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), tri_); dbgs() << "\n"; });
+/// below to update aliases.
-
+bool
-  // FIXME: Join into CP.getDstReg instead of CP.getOrigDstReg.
+SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
-  // When looking at
+                                        bool &Swapped, CoalescerPair &CP) {
-  //   %reg2000 = EXTRACT_SUBREG %EAX, sub_16bit
+  // Compute the final value assignment, assuming that the live ranges can be
-  // we really want to join %reg2000 with %AX ( = CP.getDstReg). We are actually
+  // coalesced.
-  // joining into %EAX ( = CP.getOrigDstReg) because it is guaranteed to have an
+  SmallVector<int, 16> LHSValNoAssignments;
-  // existing live interval, and we are better equipped to handle interference.
+  SmallVector<int, 16> RHSValNoAssignments;
-  // JoinCopy cleans up the mess by taking a copy of RHS before calling here,
+  DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
-  // and merging that copy into CP.getDstReg after.
+  DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
+  SmallVector<VNInfo*, 16> NewVNInfo;
 
   // If a live interval is a physical register, conservatively check if any
   // of its sub-registers is overlapping the live interval of the virtual
   // register. If so, do not coalesce.
-  if (CP.isPhys() && *tri_->getSubRegisters(CP.getOrigDstReg())) {
+  if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
+      *tri_->getSubRegisters(LHS.reg)) {
     // If it's coalescing a virtual register to a physical register, estimate
     // its live interval length. This is the *cost* of scanning an entire live
     // interval. If the cost is low, we'll do an exhaustive check instead.
@@ -1515,11 +1848,10 @@ bool SimpleRegisterCoalescing::JoinIntervals(CoalescerPair &CP) {
         li_->intervalIsInOneMBB(RHS) &&
         li_->getApproximateInstructionCount(RHS) <= 10) {
       // Perform a more exhaustive check for some common cases.
-      if (li_->conflictsWithAliasRef(RHS, CP.getOrigDstReg(), JoinedCopies))
+      if (li_->conflictsWithSubPhysRegRef(RHS, LHS.reg, true, JoinedCopies))
         return false;
     } else {
-      for (const unsigned* SR = tri_->getAliasSet(CP.getOrigDstReg()); *SR;
+      for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
-           ++SR)
         if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
           DEBUG({
               dbgs() << "\tInterfere with sub-register ";
@@ -1528,19 +1860,25 @@ bool SimpleRegisterCoalescing::JoinIntervals(CoalescerPair &CP) {
           return false;
         }
     }
+  } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
+             *tri_->getSubRegisters(RHS.reg)) {
+    if (LHS.containsOneValue() &&
+        li_->getApproximateInstructionCount(LHS) <= 10) {
+      // Perform a more exhaustive check for some common cases.
+      if (li_->conflictsWithSubPhysRegRef(LHS, RHS.reg, false, JoinedCopies))
+        return false;
+    } else {
+      for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
+        if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
+          DEBUG({
+              dbgs() << "\tInterfere with sub-register ";
+              li_->getInterval(*SR).print(dbgs(), tri_);
+            });
+          return false;
+        }
+    }
   }
 
-  // Compute the final value assignment, assuming that the live ranges can be
-  // coalesced.
-  SmallVector<int, 16> LHSValNoAssignments;
-  SmallVector<int, 16> RHSValNoAssignments;
-  DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
-  DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
-  SmallVector<VNInfo*, 16> NewVNInfo;
-
-  LiveInterval &LHS = li_->getInterval(CP.getOrigDstReg());
-  DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), tri_); dbgs() << "\n"; });
-
   // Loop over the value numbers of the LHS, seeing if any are defined from
   // the RHS.
   for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
@@ -1629,17 +1967,15 @@ bool SimpleRegisterCoalescing::JoinIntervals(CoalescerPair &CP) {
   LiveInterval::const_iterator JE = RHS.end();
 
   // Skip ahead until the first place of potential sharing.
-  if (I != IE && J != JE) {
+  if (I->start < J->start) {
-    if (I->start < J->start) {
+    I = std::upper_bound(I, IE, J->start);
-      I = std::upper_bound(I, IE, J->start);
+    if (I != LHS.begin()) --I;
-      if (I != LHS.begin()) --I;
+  } else if (J->start < I->start) {
-    } else if (J->start < I->start) {
+    J = std::upper_bound(J, JE, I->start);
-      J = std::upper_bound(J, JE, I->start);
+    if (J != RHS.begin()) --J;
-      if (J != RHS.begin()) --J;
-    }
   }
 
-  while (I != IE && J != JE) {
+  while (1) {
     // Determine if these two live ranges overlap.
     bool Overlaps;
     if (I->start < J->start) {
@@ -1661,10 +1997,13 @@ bool SimpleRegisterCoalescing::JoinIntervals(CoalescerPair &CP) {
         return false;
     }
 
-    if (I->end < J->end)
+    if (I->end < J->end) {
       ++I;
-    else
+      if (I == IE) break;
+    } else {
       ++J;
+      if (J == JE) break;
+    }
   }
 
   // Update kill info. Some live ranges are extended due to copy coalescing.
@@ -1689,15 +2028,19 @@ bool SimpleRegisterCoalescing::JoinIntervals(CoalescerPair &CP) {
     LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
   }
 
-  if (LHSValNoAssignments.empty())
-    LHSValNoAssignments.push_back(-1);
-  if (RHSValNoAssignments.empty())
-    RHSValNoAssignments.push_back(-1);
-
   // If we get here, we know that we can coalesce the live ranges.  Ask the
   // intervals to coalesce themselves now.
-  LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
+  if ((RHS.ranges.size() > LHS.ranges.size() &&
-           mri_);
+      TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
+      TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
+    RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo,
+             mri_);
+    Swapped = true;
+  } else {
+    LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
+             mri_);
+    Swapped = false;
+  }
   return true;
 }
 
@@ -1977,8 +2320,8 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
         if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
           assert((MI->isExtractSubreg() || MI->isInsertSubreg() ||
                   MI->isSubregToReg()) && "Unrecognized copy instruction");
-          SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
+          DstReg = MI->getOperand(0).getReg();
-          if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
+          if (TargetRegisterInfo::isPhysicalRegister(DstReg))
             // Do not delete extract_subreg, insert_subreg of physical
             // registers unless the definition is dead. e.g.
             // %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
@@ -1987,7 +2330,7 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
             DoDelete = false;
         }
         if (MI->allDefsAreDead()) {
-          LiveInterval &li = li_->getInterval(SrcReg);
+          LiveInterval &li = li_->getInterval(DstReg);
           if (!ShortenDeadCopySrcLiveRange(li, MI))
             ShortenDeadCopyLiveRange(li, MI);
           DoDelete = true;
@@ -2045,11 +2388,6 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
           if (MI->registerDefIsDead(DstReg)) {
             if (!ShortenDeadCopySrcLiveRange(RegInt, MI))
               ShortenDeadCopyLiveRange(RegInt, MI);
-          } else {
-            // If a value is killed here remove the marker.
-            SlotIndex UseIdx = li_->getInstructionIndex(MI).getUseIndex();
-            if (const LiveRange *LR = RegInt.getLiveRangeContaining(UseIdx))
-              LR->valno->removeKill(UseIdx.getDefIndex());
           }
         }
         li_->RemoveMachineInstrFromMaps(MI);

lib/CodeGen/SimpleRegisterCoalescing.h

@@ -105,11 +105,14 @@ namespace llvm {
     /// possible to coalesce this interval, but it may be possible if other
     /// things get coalesced, then it returns true by reference in 'Again'.
     bool JoinCopy(CopyRec &TheCopy, bool &Again);
-
+    
     /// JoinIntervals - Attempt to join these two intervals.  On failure, this
-    /// returns false.  The output "SrcInt" will not have been modified, so we can
+    /// returns false.  Otherwise, if one of the intervals being joined is a
-    /// use this information below to update aliases.
+    /// physreg, this method always canonicalizes DestInt to be it.  The output
-    bool JoinIntervals(CoalescerPair &CP);
+    /// "SrcInt" will not have been modified, so we can use this information
+    /// below to update aliases.
+    bool JoinIntervals(LiveInterval &LHS, LiveInterval &RHS, bool &Swapped,
+                       CoalescerPair &CP);
 
     /// Return true if the two specified registers belong to different register
     /// classes.  The registers may be either phys or virt regs.
@@ -146,6 +149,11 @@ namespace llvm {
     bool ReMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg,
                                  unsigned DstSubIdx, MachineInstr *CopyMI);
 
+    /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
+    /// from an implicit def to another register can be coalesced away.
+    bool CanCoalesceWithImpDef(MachineInstr *CopyMI,
+                               LiveInterval &li, LiveInterval &ImpLi) const;
+
     /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
     /// two virtual registers from different register classes.
     bool isWinToJoinCrossClass(unsigned SrcReg,
@@ -178,7 +186,7 @@ namespace llvm {
     /// physical register and the existing subregister number of the def / use
     /// being updated is not zero, make sure to set it to the correct physical
     /// subregister.
-    void UpdateRegDefsUses(const CoalescerPair &CP);
+    void UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
 
     /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
     /// Return true if live interval is removed.

test/CodeGen/ARM/vget_lane.ll

@@ -204,8 +204,8 @@ define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind {
 
 define arm_aapcs_vfpcc <2 x float> @test_vset_lanef32(float %arg0_float32_t, <2 x float> %arg1_float32x2_t) nounwind {
 ;CHECK: test_vset_lanef32:
-;CHECK: vmov.f32 s3, s0
+;CHECK: vmov.f32
-;CHECK: vmov.f64 d0, d1
+;CHECK: vmov.f32
 entry:
   %0 = insertelement <2 x float> %arg1_float32x2_t, float %arg0_float32_t, i32 1 ; <<2 x float>> [#uses=1]
   ret <2 x float> %0