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[X86] Remove PCOMMIT instruction support since Intel has deprecated this instruction with no plans to release products with it.

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Intel's documentation for the deprecation https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction

llvm-svn: 294405
This commit is contained in:
Craig Topper 2017-02-08 05:45:39 +00:00
parent 4d5a27ef2a
commit 1cb14e7d5f
7 changed files with 2 additions and 17 deletions
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1
lib/Support/Host.cpp
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@ -1369,7 +1369,6 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1);
Features["smap"] = HasLeaf7 && ((EBX >> 20) & 1); Features["smap"] = HasLeaf7 && ((EBX >> 20) & 1);
Features["pcommit"] = HasLeaf7 && ((EBX >> 22) & 1);
Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1); Features["clflushopt"] = HasLeaf7 && ((EBX >> 23) & 1);
Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1); Features["clwb"] = HasLeaf7 && ((EBX >> 24) & 1);
Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1); Features["sha"] = HasLeaf7 && ((EBX >> 29) & 1);

3
lib/Target/X86/X86.td
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@ -225,8 +225,6 @@ def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true",
"Enable Software Guard Extensions">; "Enable Software Guard Extensions">;
def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true", def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
"Flush A Cache Line Optimized">; "Flush A Cache Line Optimized">;
def FeaturePCOMMIT : SubtargetFeature<"pcommit", "HasPCOMMIT", "true",
"Enable Persistent Commit">;
def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true", def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true",
"Cache Line Write Back">; "Cache Line Write Back">;
// TODO: This feature ought to be renamed. // TODO: This feature ought to be renamed.
@ -558,7 +556,6 @@ def SKXFeatures : ProcessorFeatures<SKLFeatures.Value, [
FeatureBWI, FeatureBWI,
FeatureVLX, FeatureVLX,
FeaturePKU, FeaturePKU,
FeaturePCOMMIT,
FeatureCLWB FeatureCLWB
]>; ]>;

1
lib/Target/X86/X86InstrInfo.td
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@ -2532,7 +2532,6 @@ let Predicates = [HasTBM] in {
def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
"clflushopt\t$src", [(int_x86_clflushopt addr:$src)]>, PD; "clflushopt\t$src", [(int_x86_clflushopt addr:$src)]>, PD;
def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", []>, PD; def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", []>, PD;
def PCOMMIT : I<0xAE, MRM_F8, (outs), (ins), "pcommit", []>, PD;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

3
lib/Target/X86/X86Subtarget.h
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@ -286,9 +286,6 @@ protected:
/// Processor supports Flush Cache Line instruction /// Processor supports Flush Cache Line instruction
bool HasCLFLUSHOPT; bool HasCLFLUSHOPT;
/// Processor has Persistent Commit feature
bool HasPCOMMIT;
/// Processor supports Cache Line Write Back instruction /// Processor supports Cache Line Write Back instruction
bool HasCLWB; bool HasCLWB;

3
test/MC/Disassembler/X86/x86-32.txt
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@ -517,9 +517,6 @@
# CHECK: clwb (%eax) # CHECK: clwb (%eax)
0x66 0x0f 0xae 0x30 0x66 0x0f 0xae 0x30
# CHECK: pcommit
0x66 0x0f 0xae 0xf8
# CHECK: vcvtph2ps %xmm0, %xmm0 # CHECK: vcvtph2ps %xmm0, %xmm0
0xc4 0xe2 0x79 0x13 0xc0 0xc4 0xe2 0x79 0x13 0xc0

4
test/MC/X86/x86-32-coverage.s
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@ -10654,10 +10654,6 @@ btcq $4, (%eax)
// CHECK: encoding: [0x66,0x0f,0xae,0x35,0x78,0x56,0x34,0x12] // CHECK: encoding: [0x66,0x0f,0xae,0x35,0x78,0x56,0x34,0x12]
clwb 0x12345678 clwb 0x12345678
// CHECK: pcommit
// CHECK: encoding: [0x66,0x0f,0xae,0xf8]
pcommit
// CHECK: xsave 3735928559(%ebx,%ecx,8) // CHECK: xsave 3735928559(%ebx,%ecx,8)
// CHECK: encoding: [0x0f,0xae,0xa4,0xcb,0xef,0xbe,0xad,0xde] // CHECK: encoding: [0x0f,0xae,0xa4,0xcb,0xef,0xbe,0xad,0xde]
xsave 0xdeadbeef(%ebx,%ecx,8) xsave 0xdeadbeef(%ebx,%ecx,8)

4
test/Transforms/LoopVectorize/X86/int128_no_gather.ll
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@ -71,6 +71,6 @@ declare i32 @printf(i8*, ...) #1
; Function Attrs: nounwind ; Function Attrs: nounwind
declare i32 @puts(i8* nocapture readonly) #2 declare i32 @puts(i8* nocapture readonly) #2
attributes #0 = { noinline nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+mpx,+pclmul,+pcommit,+pku,+popcnt,+rdrnd,+rdseed,+rtm,+sgx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { noinline nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+mpx,+pclmul,+pku,+popcnt,+rdrnd,+rdseed,+rtm,+sgx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+mpx,+pclmul,+pcommit,+pku,+popcnt,+rdrnd,+rdseed,+rtm,+sgx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="skylake-avx512" "target-features"="+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+mpx,+pclmul,+pku,+popcnt,+rdrnd,+rdseed,+rtm,+sgx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #2 = { nounwind } attributes #2 = { nounwind }