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Improve the compression of the tablegen DiffLists by introducing a new sort
algorithm when assigning EnumValues to the synthesized registers. The current algorithm, LessRecord, uses the StringRef compare_numeric function. This function compares strings, while handling embedded numbers. For example, the R600 backend registers are sorted as follows: T1 T1_W T1_X T1_XYZW T1_Y T1_Z T2 T2_W T2_X T2_XYZW T2_Y T2_Z In this example, the 'scaling factor' is dEnum/dN = 6 because T0, T1, T2 have an EnumValue offset of 6 from one another. However, in other parts of the register bank, the scaling factors are different: dEnum/dN = 5: KC0_128_W KC0_128_X KC0_128_XYZW KC0_128_Y KC0_128_Z KC0_129_W KC0_129_X KC0_129_XYZW KC0_129_Y KC0_129_Z The diff lists do not work correctly because different kinds of registers have different 'scaling factors'. This new algorithm, LessRecordRegister, tries to enforce a scaling factor of 1. For example, the registers are now sorted as follows: T1 T2 T3 ... T0_W T1_W T2_W ... T0_X T1_X T2_X ... KC0_128_W KC0_129_W KC0_130_W ... For the Mips and R600 I see a 19% and 6% reduction in size, respectively. I did see a few small regressions, but the differences were on the order of a few bytes (e.g., AArch64 was 16 bytes). I suspect there will be even greater wins for targets with larger register files. Patch reviewed by Jakob. rdar://14006013 llvm-svn: 185094
This commit is contained in:
Chad Rosier
parent
2a46a546c1
commit
1ce13129c7
@ -1731,6 +1731,86 @@ struct LessRecordFieldName {
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}
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};
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struct LessRecordRegister {
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static size_t min(size_t a, size_t b) { return a < b ? a : b; }
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static bool ascii_isdigit(char x) { return x >= '0' && x <= '9'; }
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struct RecordParts {
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SmallVector<std::pair< bool, StringRef>, 4> Parts;
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RecordParts(StringRef Rec) {
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if (Rec.empty())
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return;
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size_t Len = 0;
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const char *Start = Rec.data();
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const char *Curr = Start;
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bool isDigitPart = ascii_isdigit(Curr[0]);
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for (size_t I = 0, E = Rec.size(); I != E; ++I, ++Len) {
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bool isDigit = ascii_isdigit(Curr[I]);
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if (isDigit != isDigitPart) {
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Parts.push_back(std::make_pair(isDigitPart, StringRef(Start, Len)));
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Len = 0;
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Start = &Curr[I];
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isDigitPart = ascii_isdigit(Curr[I]);
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}
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}
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// Push the last part.
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Parts.push_back(std::make_pair(isDigitPart, StringRef(Start, Len)));
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}
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size_t size() { return Parts.size(); }
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std::pair<bool, StringRef> getPart(size_t i) {
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assert (i < Parts.size() && "Invalid idx!");
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return Parts[i];
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}
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};
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bool operator()(const Record *Rec1, const Record *Rec2) const {
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RecordParts LHSParts(StringRef(Rec1->getName()));
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RecordParts RHSParts(StringRef(Rec2->getName()));
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size_t LHSNumParts = LHSParts.size();
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size_t RHSNumParts = RHSParts.size();
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assert (LHSNumParts && RHSNumParts && "Expected at least one part!");
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if (LHSNumParts != RHSNumParts)
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return LHSNumParts < RHSNumParts;
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// We expect the registers to be of the form [_a-zA-z]+([0-9]*[_a-zA-Z]*)*.
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for (size_t I = 0, E = LHSNumParts; I < E; I+=2) {
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std::pair<bool, StringRef> LHSPart = LHSParts.getPart(I);
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std::pair<bool, StringRef> RHSPart = RHSParts.getPart(I);
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if ((I & 1) == 0) { // Expect even part to always be alpha.
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assert (LHSPart.first == false && RHSPart.first == false &&
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"Expected both parts to be alpha.");
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if (int Res = LHSPart.second.compare(RHSPart.second))
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return Res < 0;
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}
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}
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for (size_t I = 1, E = LHSNumParts; I < E; I+=2) {
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std::pair<bool, StringRef> LHSPart = LHSParts.getPart(I);
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std::pair<bool, StringRef> RHSPart = RHSParts.getPart(I);
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if (I & 1) { // Expect odd part to always be numeric.
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assert (LHSPart.first == true && RHSPart.first == true &&
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"Expected both parts to be numeric.");
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if (LHSPart.second.size() != RHSPart.second.size())
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return LHSPart.second.size() < RHSPart.second.size();
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unsigned LHSVal, RHSVal;
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if (LHSPart.second.getAsInteger(10, LHSVal))
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assert("Unable to convert LHS to integer.");
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if (RHSPart.second.getAsInteger(10, RHSVal))
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assert("Unable to convert RHS to integer.");
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if (LHSVal != RHSVal)
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return LHSVal < RHSVal;
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}
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}
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return LHSNumParts < RHSNumParts;
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}
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};
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raw_ostream &operator<<(raw_ostream &OS, const RecordKeeper &RK);
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/// QualifyName - Return an Init with a qualifier prefix referring
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@ -897,17 +897,17 @@ Lforward:
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ldm r0, {r0, r2, lr}^
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ldm sp!, {r0-r3, pc}^
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@ CHECK: ldm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8]
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@ CHECK: ldm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8]
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@ CHECK: ldmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe9]
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@ CHECK: ldmda r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x12,0xe8]
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@ CHECK: ldmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x12,0xe9]
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@ CHECK: ldm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8]
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@ CHECK: ldm r2, {sp, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x20,0x92,0xe8]
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@ CHECK: ldm r2, {sp, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x20,0x92,0xe8]
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@ CHECK: ldmib r2, {sp, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x20,0x92,0xe9]
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@ CHECK: ldmda r2, {sp, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x20,0x12,0xe8]
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@ CHECK: ldmdb r2, {sp, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x20,0x12,0xe9]
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@ CHECK: ldm r2, {sp, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x20,0x92,0xe8]
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@ CHECK: ldm r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe8]
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@ CHECK: ldmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe9]
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@ CHECK: ldmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe8]
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@ CHECK: ldmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x32,0xe9]
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@ CHECK: ldm r2!, {sp, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x20,0xb2,0xe8]
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@ CHECK: ldmib r2!, {sp, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x20,0xb2,0xe9]
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@ CHECK: ldmda r2!, {sp, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x20,0x32,0xe8]
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@ CHECK: ldmdb r2!, {sp, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x20,0x32,0xe9]
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@ CHECK: ldm r0, {lr, r0, r2} ^ @ encoding: [0x05,0x40,0xd0,0xe8]
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@ CHECK: ldm sp!, {pc, r0, r1, r2, r3} ^ @ encoding: [0x0f,0x80,0xfd,0xe8]
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@ -2332,17 +2332,17 @@ Lforward:
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stmda sp!, {r1,r3-r6}
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stmdb r0!, {r1,r5,r7,sp}
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@ CHECK: stm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8]
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@ CHECK: stm r2, {sp, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x20,0x82,0xe8]
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@ CHECK: stm r3, {lr, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x40,0x83,0xe8]
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@ CHECK: stmib r4, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x84,0xe9]
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@ CHECK: stmda r5, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x05,0xe8]
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@ CHECK: stmib r4, {sp, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x20,0x84,0xe9]
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@ CHECK: stmda r5, {sp, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x20,0x05,0xe8]
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@ CHECK: stmdb r6, {r1, r3, r4, r5, r6, r8} @ encoding: [0x7a,0x01,0x06,0xe9]
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@ CHECK: stmdb sp, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x0d,0xe9]
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@ CHECK: stmdb sp, {sp, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x20,0x0d,0xe9]
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@ CHECK: stm r8!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa8,0xe8]
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@ CHECK: stmib r9!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa9,0xe9]
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@ CHECK: stm r8!, {sp, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x20,0xa8,0xe8]
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@ CHECK: stmib r9!, {sp, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x20,0xa9,0xe9]
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@ CHECK: stmda sp!, {r1, r3, r4, r5, r6} @ encoding: [0x7a,0x00,0x2d,0xe8]
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@ CHECK: stmdb r0!, {r1, r5, r7, sp} @ encoding: [0xa2,0x20,0x20,0xe9]
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@ CHECK: stmdb r0!, {sp, r1, r5, r7} @ encoding: [0xa2,0x20,0x20,0xe9]
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@------------------------------------------------------------------------------
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@ -938,7 +938,7 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) {
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// Read in the register definitions.
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std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
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std::sort(Regs.begin(), Regs.end(), LessRecord());
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std::sort(Regs.begin(), Regs.end(), LessRecordRegister());
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Registers.reserve(Regs.size());
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// Assign the enumeration values.
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for (unsigned i = 0, e = Regs.size(); i != e; ++i)
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@ -947,10 +947,16 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) {
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// Expand tuples and number the new registers.
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std::vector<Record*> Tups =
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Records.getAllDerivedDefinitions("RegisterTuples");
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std::vector<Record*> TupRegsCopy;
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for (unsigned i = 0, e = Tups.size(); i != e; ++i) {
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const std::vector<Record*> *TupRegs = Sets.expand(Tups[i]);
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for (unsigned j = 0, je = TupRegs->size(); j != je; ++j)
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getReg((*TupRegs)[j]);
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TupRegsCopy.reserve(TupRegs->size());
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TupRegsCopy.assign(TupRegs->begin(), TupRegs->end());
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std::sort(TupRegsCopy.begin(), TupRegsCopy.end(), LessRecordRegister());
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for (unsigned j = 0, je = TupRegsCopy.size(); j != je; ++j)
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getReg((TupRegsCopy)[j]);
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TupRegsCopy.clear();
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}
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// Now all the registers are known. Build the object graph of explicit
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@ -309,7 +309,7 @@ RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS,
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const std::vector<CodeGenRegister*> &Regs,
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bool isCtor) {
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// Collect all information about dwarf register numbers
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typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
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typedef std::map<Record*, std::vector<int64_t>, LessRecordRegister> DwarfRegNumsMapTy;
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DwarfRegNumsMapTy DwarfRegNums;
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// First, just pull all provided information to the map
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