RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-08 04:11:27 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

R600/SI: Add promotion of e32 to e64 in operand folding

Browse Source 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 176105
This commit is contained in:
Christian Konig 2013-02-26 17:52:47 +00:00
parent e5dbe6105f
commit 1d0c9b5395
1 changed files with 34 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
lib/Target/R600/SIISelLowering.cpp
View File

@ -501,6 +501,13 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
unsigned NumDefs = Desc->getNumDefs(); unsigned NumDefs = Desc->getNumDefs();
unsigned NumOps = Desc->getNumOperands(); unsigned NumOps = Desc->getNumOperands();
// e64 version if available, -1 otherwise
int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? 0 : &TII->get(OpcodeE64);
assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
assert(!DescE64 || DescE64->getNumOperands() == (NumOps + 4));
int32_t Immediate = Desc->getSize() == 4 ? 0 : -1; int32_t Immediate = Desc->getSize() == 4 ? 0 : -1;
bool HaveVSrc = false, HaveSSrc = false; bool HaveVSrc = false, HaveSSrc = false;
@ -532,6 +539,7 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
// Second go over the operands and try to fold them // Second go over the operands and try to fold them
std::vector<SDValue> Ops; std::vector<SDValue> Ops;
bool Promote2e64 = false;
for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs; for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
i != e && Op < NumOps; ++i, ++Op) { i != e && Op < NumOps; ++i, ++Op) {
@ -558,6 +566,20 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
SDValue Tmp = Ops[1]; SDValue Tmp = Ops[1];
Ops[1] = Ops[0]; Ops[1] = Ops[0];
Ops[0] = Tmp; Ops[0] = Tmp;
} else if (DescE64 && !Immediate) {
// Test if it makes sense to switch to e64 encoding
RegClass = DescE64->OpInfo[Op].RegClass;
int32_t TmpImm = -1;
if ((isVSrc(RegClass) || isSSrc(RegClass)) &&
foldImm(Ops[i], TmpImm, ScalarSlotUsed)) {
Immediate = -1;
Promote2e64 = true;
Desc = DescE64;
DescE64 = 0;
}
} }
continue; continue;
} }
@ -569,10 +591,20 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
} }
} }
if (Promote2e64) {
// Add the modifier flags while promoting
for (unsigned i = 0; i < 4; ++i)
Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
}
// Add optional chain and glue // Add optional chain and glue
for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i) for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i)
Ops.push_back(Node->getOperand(i)); Ops.push_back(Node->getOperand(i));
// Update the instruction parameters // Either create a complete new or update the current instruction
if (Promote2e64)
return DAG.getMachineNode(OpcodeE64, Node->getDebugLoc(),
Node->getVTList(), Ops.data(), Ops.size());
else
return DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size()); return DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size());
} }