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[AArch64] Add patterns for zext/sext of shift amount.
Not sure this is the best fix, but it saves an instruction for certain constructs involving variable shifts. Differential Revision: https://reviews.llvm.org/D55572 llvm-svn: 351768
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@ -1817,6 +1817,14 @@ multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
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def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (sext GPR32:$Rm)))),
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(!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
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def : Pat<(i64 (OpNode GPR64:$Rn, (i64 (sext GPR32:$Rm)))),
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(!cast<Instruction>(NAME # "Xr") GPR64:$Rn,
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(SUBREG_TO_REG (i32 0), GPR32:$Rm, sub_32))>;
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def : Pat<(i64 (OpNode GPR64:$Rn, (i64 (zext GPR32:$Rm)))),
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(!cast<Instruction>(NAME # "Xr") GPR64:$Rn,
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(SUBREG_TO_REG (i32 0), GPR32:$Rm, sub_32))>;
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}
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class ShiftAlias<string asm, Instruction inst, RegisterClass regtype>
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@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
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; Check that we optimize out AND instructions and ADD/SUB instructions
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@ -6,8 +7,9 @@
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define i32 @test1(i32 %x, i64 %y) {
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; CHECK-LABEL: test1:
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; CHECK-NOT: and
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; CHECK: lsr
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr w0, w0, w1
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; CHECK-NEXT: ret
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%sh_prom = trunc i64 %y to i32
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%shr = lshr i32 %x, %sh_prom
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ret i32 %shr
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@ -15,10 +17,10 @@ define i32 @test1(i32 %x, i64 %y) {
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define i64 @test2(i32 %x, i64 %y) {
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; CHECK-LABEL: test2:
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; CHECK-NOT: orr
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; CHECK-NOT: sub
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; CHECK: neg
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; CHECK: asr
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg w[[REG:[0-9]+]], w0
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; CHECK-NEXT: asr x0, x1, x[[REG]]
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; CHECK-NEXT: ret
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%sub9 = sub nsw i32 64, %x
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%sh_prom12.i = zext i32 %sub9 to i64
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%shr.i = ashr i64 %y, %sh_prom12.i
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@ -27,9 +29,46 @@ define i64 @test2(i32 %x, i64 %y) {
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define i64 @test3(i64 %x, i64 %y) {
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; CHECK-LABEL: test3:
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; CHECK-NOT: add
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; CHECK: lsl
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl x0, x1, x0
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; CHECK-NEXT: ret
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%add = add nsw i64 64, %x
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%shl = shl i64 %y, %add
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ret i64 %shl
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}
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}
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define i64 @test4(i64 %y, i32 %s) {
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; CHECK-LABEL: test4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
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; CHECK-NEXT: asr x0, x0, x1
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; CHECK-NEXT: ret
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entry:
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%sh_prom = zext i32 %s to i64
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%shr = ashr i64 %y, %sh_prom
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ret i64 %shr
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}
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define i64 @test5(i64 %y, i32 %s) {
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; CHECK-LABEL: test5:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
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; CHECK-NEXT: asr x0, x0, x1
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; CHECK-NEXT: ret
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entry:
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%sh_prom = sext i32 %s to i64
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%shr = ashr i64 %y, %sh_prom
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ret i64 %shr
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}
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define i64 @test6(i64 %y, i32 %s) {
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; CHECK-LABEL: test6:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
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; CHECK-NEXT: lsl x0, x0, x1
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; CHECK-NEXT: ret
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entry:
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%sh_prom = sext i32 %s to i64
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%shr = shl i64 %y, %sh_prom
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ret i64 %shr
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}
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