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[AArch64] Implement aarch64_vector_pcs codegen support.
This patch adds codegen support for the saving/restoring V8-V23 for functions specified with the aarch64_vector_pcs calling convention attribute, as added in patch D51477. Reviewers: t.p.northover, gberry, thegameg, rengolin, javed.absar, MatzeB Reviewed By: thegameg Differential Revision: https://reviews.llvm.org/D51479 llvm-svn: 342049
This commit is contained in:
Sander de Smalen
parent
c366257a21
commit
1e20d76347
@ -288,6 +288,12 @@ def CSR_AArch64_AAPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, X22,
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D8, D9, D10, D11,
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D12, D13, D14, D15)>;
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// AArch64 PCS for vector functions (VPCS)
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// must (additionally) preserve full Q8-Q23 registers
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def CSR_AArch64_AAVPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, X22,
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X23, X24, X25, X26, X27, X28,
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(sequence "Q%u", 8, 23))>;
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// Constructors and destructors return 'this' in the iOS 64-bit C++ ABI; since
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// 'this' and the pointer return value are both passed in X0 in these cases,
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// this can be partially modelled by treating X0 as a callee-saved register;
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@ -362,5 +368,7 @@ def CSR_AArch64_AAPCS_SwiftError_SCS
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: CalleeSavedRegs<(add CSR_AArch64_AAPCS_SwiftError, X18)>;
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def CSR_AArch64_RT_MostRegs_SCS
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: CalleeSavedRegs<(add CSR_AArch64_RT_MostRegs, X18)>;
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def CSR_AArch64_AAVPCS_SCS
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: CalleeSavedRegs<(add CSR_AArch64_AAVPCS, X18)>;
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def CSR_AArch64_AAPCS_SCS
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: CalleeSavedRegs<(add CSR_AArch64_AAPCS, X18)>;
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@ -461,12 +461,19 @@ static MachineBasicBlock::iterator convertCalleeSaveRestoreToSPPrePostIncDec(
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NewOpc = AArch64::STPDpre;
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Scale = 8;
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break;
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case AArch64::STPQi:
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NewOpc = AArch64::STPQpre;
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Scale = 16;
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break;
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case AArch64::STRXui:
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NewOpc = AArch64::STRXpre;
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break;
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case AArch64::STRDui:
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NewOpc = AArch64::STRDpre;
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break;
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case AArch64::STRQui:
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NewOpc = AArch64::STRQpre;
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break;
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case AArch64::LDPXi:
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NewOpc = AArch64::LDPXpost;
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Scale = 8;
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@ -475,12 +482,19 @@ static MachineBasicBlock::iterator convertCalleeSaveRestoreToSPPrePostIncDec(
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NewOpc = AArch64::LDPDpost;
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Scale = 8;
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break;
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case AArch64::LDPQi:
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NewOpc = AArch64::LDPQpost;
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Scale = 16;
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break;
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case AArch64::LDRXui:
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NewOpc = AArch64::LDRXpost;
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break;
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case AArch64::LDRDui:
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NewOpc = AArch64::LDRDpost;
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break;
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case AArch64::LDRQui:
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NewOpc = AArch64::LDRQpost;
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break;
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}
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc));
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@ -531,6 +545,12 @@ static void fixupCalleeSaveRestoreStackOffset(MachineInstr &MI,
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case AArch64::LDRDui:
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Scale = 8;
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break;
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case AArch64::STPQi:
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case AArch64::STRQui:
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case AArch64::LDPQi:
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case AArch64::LDRQui:
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Scale = 16;
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break;
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default:
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llvm_unreachable("Unexpected callee-save save/restore opcode!");
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}
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@ -541,7 +561,7 @@ static void fixupCalleeSaveRestoreStackOffset(MachineInstr &MI,
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// Last operand is immediate offset that needs fixing.
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MachineOperand &OffsetOpnd = MI.getOperand(OffsetIdx);
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// All generated opcodes have scaled offsets.
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assert(LocalStackSize % 8 == 0);
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assert(LocalStackSize % Scale == 0);
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OffsetOpnd.setImm(OffsetOpnd.getImm() + LocalStackSize / Scale);
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}
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@ -1208,7 +1228,7 @@ struct RegPairInfo {
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unsigned Reg2 = AArch64::NoRegister;
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int FrameIdx;
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int Offset;
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enum RegType { GPR, FPR64 } Type;
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enum RegType { GPR, FPR64, FPR128 } Type;
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RegPairInfo() = default;
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@ -1246,6 +1266,8 @@ static void computeCalleeSaveRegisterPairs(
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RPI.Type = RegPairInfo::GPR;
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else if (AArch64::FPR64RegClass.contains(RPI.Reg1))
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RPI.Type = RegPairInfo::FPR64;
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else if (AArch64::FPR128RegClass.contains(RPI.Reg1))
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RPI.Type = RegPairInfo::FPR128;
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else
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llvm_unreachable("Unsupported register class.");
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@ -1261,6 +1283,10 @@ static void computeCalleeSaveRegisterPairs(
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if (AArch64::FPR64RegClass.contains(NextReg))
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RPI.Reg2 = NextReg;
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break;
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case RegPairInfo::FPR128:
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if (AArch64::FPR128RegClass.contains(NextReg))
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RPI.Reg2 = NextReg;
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break;
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}
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}
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@ -1294,17 +1320,21 @@ static void computeCalleeSaveRegisterPairs(
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RPI.FrameIdx = CSI[i].getFrameIdx();
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if (Count * 8 != AFI->getCalleeSavedStackSize() && !RPI.isPaired()) {
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// Round up size of non-pair to pair size if we need to pad the
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// callee-save area to ensure 16-byte alignment.
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Offset -= 16;
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int Scale = RPI.Type == RegPairInfo::FPR128 ? 16 : 8;
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Offset -= RPI.isPaired() ? 2 * Scale : Scale;
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// Round up size of non-pair to pair size if we need to pad the
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// callee-save area to ensure 16-byte alignment.
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if (AFI->hasCalleeSaveStackFreeSpace() &&
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RPI.Type != RegPairInfo::FPR128 && !RPI.isPaired()) {
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Offset -= 8;
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assert(Offset % 16 == 0);
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assert(MFI.getObjectAlignment(RPI.FrameIdx) <= 16);
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MFI.setObjectAlignment(RPI.FrameIdx, 16);
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AFI->setCalleeSaveStackHasFreeSpace(true);
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} else
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Offset -= RPI.isPaired() ? 16 : 8;
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assert(Offset % 8 == 0);
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RPI.Offset = Offset / 8;
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}
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assert(Offset % Scale == 0);
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RPI.Offset = Offset / Scale;
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assert((RPI.Offset >= -64 && RPI.Offset <= 63) &&
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"Offset out of bounds for LDP/STP immediate");
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@ -1370,6 +1400,11 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
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Size = 8;
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Align = 8;
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break;
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case RegPairInfo::FPR128:
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StrOpc = RPI.isPaired() ? AArch64::STPQi : AArch64::STRQui;
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Size = 16;
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Align = 16;
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break;
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}
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LLVM_DEBUG(dbgs() << "CSR spill: (" << printReg(Reg1, TRI);
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if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI);
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@ -1441,6 +1476,11 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters(
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Size = 8;
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Align = 8;
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break;
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case RegPairInfo::FPR128:
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LdrOpc = RPI.isPaired() ? AArch64::LDPQi : AArch64::LDRQui;
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Size = 16;
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Align = 16;
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break;
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}
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LLVM_DEBUG(dbgs() << "CSR restore: (" << printReg(Reg1, TRI);
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if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI);
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@ -1507,24 +1547,6 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
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? RegInfo->getBaseRegister()
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: (unsigned)AArch64::NoRegister;
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unsigned SpillEstimate = SavedRegs.count();
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for (unsigned i = 0; CSRegs[i]; ++i) {
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unsigned Reg = CSRegs[i];
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unsigned PairedReg = CSRegs[i ^ 1];
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if (Reg == BasePointerReg)
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SpillEstimate++;
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if (produceCompactUnwindFrame(MF) && !SavedRegs.test(PairedReg))
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SpillEstimate++;
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}
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SpillEstimate += 2; // Conservatively include FP+LR in the estimate
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unsigned StackEstimate = MFI.estimateStackSize(MF) + 8 * SpillEstimate;
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// The frame record needs to be created by saving the appropriate registers
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if (hasFP(MF) || windowsRequiresStackProbe(MF, StackEstimate)) {
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SavedRegs.set(AArch64::FP);
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SavedRegs.set(AArch64::LR);
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}
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unsigned ExtraCSSpill = 0;
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// Figure out which callee-saved registers to save/restore.
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for (unsigned i = 0; CSRegs[i]; ++i) {
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@ -1548,7 +1570,8 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
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// MachO's compact unwind format relies on all registers being stored in
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// pairs.
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// FIXME: the usual format is actually better if unwinding isn't needed.
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if (produceCompactUnwindFrame(MF) && !SavedRegs.test(PairedReg)) {
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if (produceCompactUnwindFrame(MF) && PairedReg != AArch64::NoRegister &&
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!SavedRegs.test(PairedReg)) {
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SavedRegs.set(PairedReg);
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if (AArch64::GPR64RegClass.contains(PairedReg) &&
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!RegInfo->isReservedReg(MF, PairedReg))
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@ -1556,6 +1579,24 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
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}
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}
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// Calculates the callee saved stack size.
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unsigned CSStackSize = 0;
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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for (unsigned Reg : SavedRegs.set_bits())
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CSStackSize += TRI->getRegSizeInBits(Reg, MRI) / 8;
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// Save number of saved regs, so we can easily update CSStackSize later.
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unsigned NumSavedRegs = SavedRegs.count();
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// The frame record needs to be created by saving the appropriate registers
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unsigned EstimatedStackSize = MFI.estimateStackSize(MF);
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if (hasFP(MF) ||
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windowsRequiresStackProbe(MF, EstimatedStackSize + CSStackSize + 16)) {
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SavedRegs.set(AArch64::FP);
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SavedRegs.set(AArch64::LR);
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}
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LLVM_DEBUG(dbgs() << "*** determineCalleeSaves\nUsed CSRs:";
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for (unsigned Reg
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: SavedRegs.set_bits()) dbgs()
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@ -1563,15 +1604,12 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
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dbgs() << "\n";);
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// If any callee-saved registers are used, the frame cannot be eliminated.
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unsigned NumRegsSpilled = SavedRegs.count();
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bool CanEliminateFrame = NumRegsSpilled == 0;
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bool CanEliminateFrame = SavedRegs.count() == 0;
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// The CSR spill slots have not been allocated yet, so estimateStackSize
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// won't include them.
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unsigned CFSize = MFI.estimateStackSize(MF) + 8 * NumRegsSpilled;
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LLVM_DEBUG(dbgs() << "Estimated stack frame size: " << CFSize << " bytes.\n");
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unsigned EstimatedStackSizeLimit = estimateRSStackSizeLimit(MF);
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bool BigStack = (CFSize > EstimatedStackSizeLimit);
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bool BigStack = (EstimatedStackSize + CSStackSize) > EstimatedStackSizeLimit;
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if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF))
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AFI->setHasStackFrame(true);
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@ -1592,7 +1630,6 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
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if (produceCompactUnwindFrame(MF))
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SavedRegs.set(UnspilledCSGPRPaired);
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ExtraCSSpill = UnspilledCSGPRPaired;
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NumRegsSpilled = SavedRegs.count();
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}
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// If we didn't find an extra callee-saved register to spill, create
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@ -1609,9 +1646,17 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
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}
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}
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// Adding the size of additional 64bit GPR saves.
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CSStackSize += 8 * (SavedRegs.count() - NumSavedRegs);
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unsigned AlignedCSStackSize = alignTo(CSStackSize, 16);
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LLVM_DEBUG(dbgs() << "Estimated stack frame size: "
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<< EstimatedStackSize + AlignedCSStackSize
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<< " bytes.\n");
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// Round up to register pair alignment to avoid additional SP adjustment
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// instructions.
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AFI->setCalleeSavedStackSize(alignTo(8 * NumRegsSpilled, 16));
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AFI->setCalleeSavedStackSize(AlignedCSStackSize);
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AFI->setCalleeSaveStackHasFreeSpace(AlignedCSStackSize != CSStackSize);
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}
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bool AArch64FrameLowering::enableStackSlotScavenging(
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@ -50,8 +50,7 @@ AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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if (MF->getFunction().getCallingConv() == CallingConv::AnyReg)
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return CSR_AArch64_AllRegs_SaveList;
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if (MF->getFunction().getCallingConv() == CallingConv::AArch64_VectorCall)
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// FIXME: default to AAPCS until we add full support.
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return CSR_AArch64_AAPCS_SaveList;
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return CSR_AArch64_AAVPCS_SaveList;
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if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS)
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return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?
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CSR_AArch64_CXX_TLS_Darwin_PE_SaveList :
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@ -102,8 +101,7 @@ AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
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return SCS ? CSR_AArch64_CXX_TLS_Darwin_SCS_RegMask
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: CSR_AArch64_CXX_TLS_Darwin_RegMask;
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if (CC == CallingConv::AArch64_VectorCall)
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// FIXME: default to AAPCS until we add full support.
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return SCS ? CSR_AArch64_AAPCS_SCS_RegMask : CSR_AArch64_AAPCS_RegMask;
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return SCS ? CSR_AArch64_AAVPCS_SCS_RegMask : CSR_AArch64_AAVPCS_RegMask;
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if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering()
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->supportSwiftError() &&
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MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
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253
test/CodeGen/AArch64/aarch64-vector-pcs.mir
Normal file
253
test/CodeGen/AArch64/aarch64-vector-pcs.mir
Normal file
@ -0,0 +1,253 @@
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# RUN: llc -mtriple=aarch64-linux-gnu -run-pass=prologepilog %s -o - | FileCheck %s
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# The tests below test the allocation of 128bit callee-saves
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# on the stack, specifically their offsets.
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# Padding of GPR64-registers is needed to ensure 16 byte alignment of
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# the stack pointer after the GPR64/FPR64 block (which is also needed
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# for the FPR128 saves when present).
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# This file also tests whether an emergency stack slot is allocated
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# when the stack frame is over a given size, caused by a series of
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# FPR128 saves. The alignment can leave a gap that can be scavenged
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# for stack slot scavenging, so it is important that the stack size
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# is properly estimated.
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--- |
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; ModuleID = '<stdin>'
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source_filename = "<stdin>"
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-unknown-linux-gnu"
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; Function Attrs: nounwind
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define aarch64_vector_pcs void @test_q10_q11_x19() nounwind { entry: unreachable }
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; Function Attrs: nounwind
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define aarch64_vector_pcs void @test_q10_q11_x19_x20() nounwind { entry: unreachable }
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; Function Attrs: nounwind
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define aarch64_vector_pcs void @test_q10_q11_x19_x20_x21() nounwind { entry: unreachable }
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; Function Attrs: nounwind
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define aarch64_vector_pcs void @test_q8_to_q23_x19_to_x30() nounwind { entry: unreachable }
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; Function Attrs: nounwind
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define aarch64_vector_pcs void @test_q8_to_q23_x19_to_x30_preinc() nounwind { entry: unreachable }
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...
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---
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name: test_q10_q11_x19
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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$x19 = IMPLICIT_DEF
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$q10 = IMPLICIT_DEF
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$q11 = IMPLICIT_DEF
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; Check that the alignment gap for the 8-byte x19 is padded
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; with another 8 bytes. The CSR region will look like this:
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; +-------------------+
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; |/////padding///////| (8 bytes)
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; | X19 | (8 bytes)
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; +-------------------+ <- SP -16
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; | Q10, Q11 | (32 bytes)
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; +-------------------+ <- SP -48
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; CHECK-LABEL: test_q10_q11_x19{{[[:space:]]}}
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; CHECK-DAG: $sp = frame-setup STPQpre killed $q11, killed $q10, $sp, -3 :: (store 16 into %stack.[[Q11:[0-9]+]]), (store 16 into %stack.[[Q10:[0-9]+]])
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; CHECK-DAG: - { id: [[Q11]], {{.*}}, offset: -48, size: 16, alignment: 16
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; CHECK-DAG: - { id: [[Q10]], {{.*}}, offset: -32, size: 16, alignment: 16
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; CHECK-DAG: frame-setup STRXui killed $x19, $sp, 4 :: (store 8 into %stack.[[X19:[0-9]+]])
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; CHECK-DAG: - { id: [[X19]], {{.*}}, offset: -16, size: 8, alignment: 16
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...
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---
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name: test_q10_q11_x19_x20
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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$x19 = IMPLICIT_DEF
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$x20 = IMPLICIT_DEF
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$q10 = IMPLICIT_DEF
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$q11 = IMPLICIT_DEF
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; +-------------------+
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; | X19, X20 | (16 bytes)
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; +-------------------+ <- SP -16
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; | Q10, Q11 | (32 bytes)
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; +-------------------+ <- SP -48
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; CHECK-LABEL: test_q10_q11_x19_x20{{[[:space:]]}}
|
||||
; CHECK-DAG: $sp = frame-setup STPQpre killed $q11, killed $q10, $sp, -3 :: (store 16 into %stack.[[Q11:[0-9]+]]), (store 16 into %stack.[[Q10:[0-9]+]])
|
||||
; CHECK-DAG: frame-setup STPXi killed $x20, killed $x19, $sp, 4 :: (store 8 into %stack.[[X20:[0-9]+]]), (store 8 into %stack.[[X19:[0-9]+]])
|
||||
; CHECK-DAG: - { id: [[Q11]], {{.*}}, offset: -48, size: 16, alignment: 16
|
||||
; CHECK-DAG: - { id: [[Q10]], {{.*}}, offset: -32, size: 16, alignment: 16
|
||||
; CHECK-DAG: - { id: [[X20]], {{.*}}, offset: -16, size: 8, alignment: 8
|
||||
; CHECK-DAG: - { id: [[X19]], {{.*}}, offset: -8, size: 8, alignment: 8
|
||||
|
||||
...
|
||||
---
|
||||
name: test_q10_q11_x19_x20_x21
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
$x19 = IMPLICIT_DEF
|
||||
$x20 = IMPLICIT_DEF
|
||||
$x21 = IMPLICIT_DEF
|
||||
$q10 = IMPLICIT_DEF
|
||||
$q11 = IMPLICIT_DEF
|
||||
|
||||
; Check that the alignment gap is padded with another 8 bytes.
|
||||
; The CSR region will look like this:
|
||||
; +-------------------+
|
||||
; | X19, X20 | (16 bytes)
|
||||
; +-------------------+ <- SP -16
|
||||
; |/////padding///////| (8 bytes)
|
||||
; | X21 | (8 bytes)
|
||||
; +-------------------+ <- SP -32
|
||||
; | Q10, Q11 | (32 bytes)
|
||||
; +-------------------+ <- SP -64
|
||||
|
||||
; CHECK-LABEL: test_q10_q11_x19_x20_x21
|
||||
; CHECK-DAG: $sp = frame-setup STPQpre killed $q11, killed $q10, $sp, -4 :: (store 16 into %stack.[[Q11:[0-9]+]]), (store 16 into %stack.[[Q10:[0-9]+]])
|
||||
; CHECK-DAG: frame-setup STRXui killed $x21, $sp, 4 :: (store 8 into %stack.[[X21:[0-9]+]])
|
||||
; CHECK-DAG: frame-setup STPXi killed $x20, killed $x19, $sp, 6
|
||||
; CHECK-DAG: - { id: [[Q11]], {{.*}}, offset: -64, size: 16, alignment: 16
|
||||
; CHECK-DAG: - { id: [[Q10]], {{.*}}, offset: -48, size: 16, alignment: 16
|
||||
; CHECK-DAG: - { id: [[X21]], {{.*}}, offset: -32, size: 8, alignment: 16
|
||||
|
||||
...
|
||||
---
|
||||
name: test_q8_to_q23_x19_to_x30
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0.entry:
|
||||
$x19 = IMPLICIT_DEF
|
||||
$x20 = IMPLICIT_DEF
|
||||
$x21 = IMPLICIT_DEF
|
||||
$x22 = IMPLICIT_DEF
|
||||
$x23 = IMPLICIT_DEF
|
||||
$x24 = IMPLICIT_DEF
|
||||
$x25 = IMPLICIT_DEF
|
||||
$x26 = IMPLICIT_DEF
|
||||
$x27 = IMPLICIT_DEF
|
||||
$x28 = IMPLICIT_DEF
|
||||
$fp = IMPLICIT_DEF
|
||||
$lr = IMPLICIT_DEF
|
||||
$q8 = IMPLICIT_DEF
|
||||
$q9 = IMPLICIT_DEF
|
||||
$q10 = IMPLICIT_DEF
|
||||
$q11 = IMPLICIT_DEF
|
||||
$q12 = IMPLICIT_DEF
|
||||
$q13 = IMPLICIT_DEF
|
||||
$q14 = IMPLICIT_DEF
|
||||
$q15 = IMPLICIT_DEF
|
||||
$q16 = IMPLICIT_DEF
|
||||
$q17 = IMPLICIT_DEF
|
||||
$q18 = IMPLICIT_DEF
|
||||
$q19 = IMPLICIT_DEF
|
||||
$q20 = IMPLICIT_DEF
|
||||
$q21 = IMPLICIT_DEF
|
||||
$q22 = IMPLICIT_DEF
|
||||
$q23 = IMPLICIT_DEF
|
||||
|
||||
; Test with more callee saves, which triggers 'BigStack' in
|
||||
; AArch64FrameLowering which in turn causes an emergency spill
|
||||
; slot to be allocated. The emergency spill slot is allocated
|
||||
; as close as possible to SP, so at SP + 0.
|
||||
; +-------------------+
|
||||
; | X19..X30 | (96 bytes)
|
||||
; +-------------------+ <- SP -96
|
||||
; | Q8..Q23 | (256 bytes)
|
||||
; +-------------------+ <- SP -352
|
||||
; | emergency slot | (16 bytes)
|
||||
; +-------------------+ <- SP -368
|
||||
|
||||
; CHECK-LABEL: test_q8_to_q23_x19_to_x30
|
||||
; CHECK: $sp = frame-setup SUBXri $sp, 368, 0
|
||||
; CHECK-NEXT: frame-setup STPQi killed $q23, killed $q22, $sp, 1 :: (store 16 into %stack.{{[0-9]+}}), (store 16 into %stack.{{[0-9]+}})
|
||||
; CHECK-NEXT: frame-setup STPQi killed $q21, killed $q20, $sp, 3
|
||||
; CHECK-NEXT: frame-setup STPQi killed $q19, killed $q18, $sp, 5
|
||||
; CHECK-NEXT: frame-setup STPQi killed $q17, killed $q16, $sp, 7
|
||||
; CHECK-NEXT: frame-setup STPQi killed $q15, killed $q14, $sp, 9
|
||||
; CHECK-NEXT: frame-setup STPQi killed $q13, killed $q12, $sp, 11
|
||||
; CHECK-NEXT: frame-setup STPQi killed $q11, killed $q10, $sp, 13
|
||||
; CHECK-NEXT: frame-setup STPQi killed $q9, killed $q8, $sp, 15
|
||||
; CHECK-NEXT: frame-setup STPXi killed $x28, killed $x27, $sp, 34 :: (store 8 into %stack.{{[0-9]+}}), (store 8 into %stack.{{[0-9]+}})
|
||||
; CHECK-NEXT: frame-setup STPXi killed $x26, killed $x25, $sp, 36
|
||||
; CHECK-NEXT: frame-setup STPXi killed $x24, killed $x23, $sp, 38
|
||||
; CHECK-NEXT: frame-setup STPXi killed $x22, killed $x21, $sp, 40
|
||||
; CHECK-NEXT: frame-setup STPXi killed $x20, killed $x19, $sp, 42
|
||||
; CHECK-NEXT: frame-setup STPXi killed $fp, killed $lr, $sp, 44
|
||||
|
||||
...
|
||||
---
|
||||
name: test_q8_to_q23_x19_to_x30_preinc
|
||||
tracksRegLiveness: true
|
||||
stack:
|
||||
- { id: 0, size: 160, alignment: 4, local-offset: 0 }
|
||||
constants:
|
||||
body: |
|
||||
bb.0.entry:
|
||||
$x19 = IMPLICIT_DEF
|
||||
$x20 = IMPLICIT_DEF
|
||||
$x21 = IMPLICIT_DEF
|
||||
$x22 = IMPLICIT_DEF
|
||||
$x23 = IMPLICIT_DEF
|
||||
$x24 = IMPLICIT_DEF
|
||||
$x25 = IMPLICIT_DEF
|
||||
$x26 = IMPLICIT_DEF
|
||||
$x27 = IMPLICIT_DEF
|
||||
$x28 = IMPLICIT_DEF
|
||||
$fp = IMPLICIT_DEF
|
||||
$lr = IMPLICIT_DEF
|
||||
$q8 = IMPLICIT_DEF
|
||||
$q9 = IMPLICIT_DEF
|
||||
$q10 = IMPLICIT_DEF
|
||||
$q11 = IMPLICIT_DEF
|
||||
$q12 = IMPLICIT_DEF
|
||||
$q13 = IMPLICIT_DEF
|
||||
$q14 = IMPLICIT_DEF
|
||||
$q15 = IMPLICIT_DEF
|
||||
$q16 = IMPLICIT_DEF
|
||||
$q17 = IMPLICIT_DEF
|
||||
$q18 = IMPLICIT_DEF
|
||||
$q19 = IMPLICIT_DEF
|
||||
$q20 = IMPLICIT_DEF
|
||||
$q21 = IMPLICIT_DEF
|
||||
$q22 = IMPLICIT_DEF
|
||||
$q23 = IMPLICIT_DEF
|
||||
|
||||
; When the total stack size >= 512, it will use the pre-increment
|
||||
; rather than the 'sub sp, sp, <size>'.
|
||||
; +-------------------+
|
||||
; | X19..X30 | (96 bytes)
|
||||
; +-------------------+ <- SP -96
|
||||
; | Q8..Q23 | (256 bytes)
|
||||
; +-------------------+ <- SP -352
|
||||
; | 'obj' | (32 bytes)
|
||||
; +-------------------+ <- SP -384
|
||||
; | emergency slot | (16 bytes)
|
||||
; +-------------------+ <- SP -400
|
||||
|
||||
; CHECK-LABEL: test_q8_to_q23_x19_to_x30_preinc
|
||||
; CHECK: $sp = frame-setup STPQpre killed $q23, killed $q22, $sp, -22 :: (store 16 into %stack.{{[0-9]+}}), (store 16 into %stack.{{[0-9]+}})
|
||||
; CHECK-NEXT: frame-setup STPQi killed $q21, killed $q20, $sp, 2
|
||||
; CHECK-NEXT: frame-setup STPQi killed $q19, killed $q18, $sp, 4
|
||||
; CHECK-NEXT: frame-setup STPQi killed $q17, killed $q16, $sp, 6
|
||||
; CHECK-NEXT: frame-setup STPQi killed $q15, killed $q14, $sp, 8
|
||||
; CHECK-NEXT: frame-setup STPQi killed $q13, killed $q12, $sp, 10
|
||||
; CHECK-NEXT: frame-setup STPQi killed $q11, killed $q10, $sp, 12
|
||||
; CHECK-NEXT: frame-setup STPQi killed $q9, killed $q8, $sp, 14
|
||||
; CHECK-NEXT: frame-setup STPXi killed $x28, killed $x27, $sp, 32 :: (store 8 into %stack.{{[0-9]+}}), (store 8 into %stack.{{[0-9]+}})
|
||||
; CHECK-NEXT: frame-setup STPXi killed $x26, killed $x25, $sp, 34
|
||||
; CHECK-NEXT: frame-setup STPXi killed $x24, killed $x23, $sp, 36
|
||||
; CHECK-NEXT: frame-setup STPXi killed $x22, killed $x21, $sp, 38
|
||||
; CHECK-NEXT: frame-setup STPXi killed $x20, killed $x19, $sp, 40
|
||||
; CHECK-NEXT: frame-setup STPXi killed $fp, killed $lr, $sp, 42
|
||||
; CHECK-NEXT: $sp = frame-setup SUBXri $sp, 176, 0
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue
Block a user