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AArch64: Fix XSeqPairs/WSeqPairs problems
- Fix spill/reloads of XSeqPairs failing with vregs (only physregs worked correctly) - Add missing spill/reload code for WSeqPairs class Differential Revision: https://reviews.llvm.org/D52761 llvm-svn: 343799
This commit is contained in:
Matthias Braun
parent
c2106b631d
commit
1f941370f1
@ -2744,6 +2744,29 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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llvm_unreachable("unimplemented reg-to-reg copy");
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}
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static void storeRegPairToStackSlot(const TargetRegisterInfo &TRI,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertBefore,
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const MCInstrDesc &MCID,
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unsigned SrcReg, bool IsKill,
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unsigned SubIdx0, unsigned SubIdx1, int FI,
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MachineMemOperand *MMO) {
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unsigned SrcReg0 = SrcReg;
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unsigned SrcReg1 = SrcReg;
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if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
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SrcReg0 = TRI.getSubReg(SrcReg, SubIdx0);
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SubIdx0 = 0;
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SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1);
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SubIdx1 = 0;
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}
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BuildMI(MBB, InsertBefore, DebugLoc(), MCID)
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.addReg(SrcReg0, getKillRegState(IsKill), SubIdx0)
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.addReg(SrcReg1, getKillRegState(IsKill), SubIdx1)
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.addFrameIndex(FI)
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.addImm(0)
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.addMemOperand(MMO);
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}
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void AArch64InstrInfo::storeRegToStackSlot(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
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bool isKill, int FI, const TargetRegisterClass *RC,
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@ -2786,8 +2809,14 @@ void AArch64InstrInfo::storeRegToStackSlot(
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MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass);
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else
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assert(SrcReg != AArch64::SP);
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} else if (AArch64::FPR64RegClass.hasSubClassEq(RC))
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} else if (AArch64::FPR64RegClass.hasSubClassEq(RC)) {
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Opc = AArch64::STRDui;
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} else if (AArch64::WSeqPairsClassRegClass.hasSubClassEq(RC)) {
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storeRegPairToStackSlot(getRegisterInfo(), MBB, MBBI,
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get(AArch64::STPWi), SrcReg, isKill,
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AArch64::sube32, AArch64::subo32, FI, MMO);
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return;
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}
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break;
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case 16:
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if (AArch64::FPR128RegClass.hasSubClassEq(RC))
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@ -2797,14 +2826,9 @@ void AArch64InstrInfo::storeRegToStackSlot(
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Opc = AArch64::ST1Twov1d;
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Offset = false;
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} else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {
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BuildMI(MBB, MBBI, DL, get(AArch64::STPXi))
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.addReg(TRI->getSubReg(SrcReg, AArch64::sube64),
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getKillRegState(isKill))
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.addReg(TRI->getSubReg(SrcReg, AArch64::subo64),
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getKillRegState(isKill))
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.addFrameIndex(FI)
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.addImm(0)
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.addMemOperand(MMO);
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storeRegPairToStackSlot(getRegisterInfo(), MBB, MBBI,
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get(AArch64::STPXi), SrcReg, isKill,
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AArch64::sube64, AArch64::subo64, FI, MMO);
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return;
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}
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break;
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@ -2852,6 +2876,31 @@ void AArch64InstrInfo::storeRegToStackSlot(
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MI.addMemOperand(MMO);
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}
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static void loadRegPairFromStackSlot(const TargetRegisterInfo &TRI,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertBefore,
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const MCInstrDesc &MCID,
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unsigned DestReg, unsigned SubIdx0,
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unsigned SubIdx1, int FI,
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MachineMemOperand *MMO) {
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unsigned DestReg0 = DestReg;
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unsigned DestReg1 = DestReg;
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bool IsUndef = true;
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if (TargetRegisterInfo::isPhysicalRegister(DestReg)) {
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DestReg0 = TRI.getSubReg(DestReg, SubIdx0);
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SubIdx0 = 0;
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DestReg1 = TRI.getSubReg(DestReg, SubIdx1);
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SubIdx1 = 0;
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IsUndef = false;
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}
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BuildMI(MBB, InsertBefore, DebugLoc(), MCID)
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.addReg(DestReg0, RegState::Define | getUndefRegState(IsUndef), SubIdx0)
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.addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1)
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.addFrameIndex(FI)
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.addImm(0)
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.addMemOperand(MMO);
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}
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void AArch64InstrInfo::loadRegFromStackSlot(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
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int FI, const TargetRegisterClass *RC,
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@ -2894,8 +2943,14 @@ void AArch64InstrInfo::loadRegFromStackSlot(
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MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass);
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else
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assert(DestReg != AArch64::SP);
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} else if (AArch64::FPR64RegClass.hasSubClassEq(RC))
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} else if (AArch64::FPR64RegClass.hasSubClassEq(RC)) {
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Opc = AArch64::LDRDui;
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} else if (AArch64::WSeqPairsClassRegClass.hasSubClassEq(RC)) {
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loadRegPairFromStackSlot(getRegisterInfo(), MBB, MBBI,
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get(AArch64::LDPWi), DestReg, AArch64::sube32,
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AArch64::subo32, FI, MMO);
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return;
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}
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break;
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case 16:
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if (AArch64::FPR128RegClass.hasSubClassEq(RC))
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@ -2905,14 +2960,9 @@ void AArch64InstrInfo::loadRegFromStackSlot(
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Opc = AArch64::LD1Twov1d;
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Offset = false;
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} else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {
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BuildMI(MBB, MBBI, DL, get(AArch64::LDPXi))
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.addReg(TRI->getSubReg(DestReg, AArch64::sube64),
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getDefRegState(true))
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.addReg(TRI->getSubReg(DestReg, AArch64::subo64),
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getDefRegState(true))
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.addFrameIndex(FI)
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.addImm(0)
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.addMemOperand(MMO);
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loadRegPairFromStackSlot(getRegisterInfo(), MBB, MBBI,
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get(AArch64::LDPXi), DestReg, AArch64::sube64,
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AArch64::subo64, FI, MMO);
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return;
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}
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break;
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42
test/CodeGen/AArch64/seqpairspill.mir
Normal file
42
test/CodeGen/AArch64/seqpairspill.mir
Normal file
@ -0,0 +1,42 @@
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# RUN: llc -o - %s -mtriple=aarch64-- -mattr=+v8.1a -run-pass=greedy,virtregrewriter | FileCheck %s
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# Make sure spills/reloads from xseqpairs and wseqpairs work correctly.
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---
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# CHECK-LABEL: name: spill_reload_xseqpairs
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name: spill_reload_xseqpairs
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body: |
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bb.0:
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; Check the spill/reload sequence for the %0 register
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; CHECK: renamable $[[REG0:[a-z0-9]+]]_[[REG1:[a-z0-9]+]] = CASPALX
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; CHECK-NEXT: STPXi renamable $[[REG0]], renamable $[[REG1]], %stack.0, 0, implicit killed $[[REG0]]_[[REG1]] :: (store 16 into %stack.0, align 8)
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; CHECK: INLINEASM
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; CHECK: renamable $[[REG2:[a-z0-9]+]], renamable $[[REG3:[a-z0-9]+]] = LDPXi %stack.0, 0, implicit-def $[[REG2]]_[[REG3]] :: (load 16 from %stack.0, align 8)
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; CHECK-NEXT: $xzr = COPY renamable $[[REG2]]
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; CHECK-NEXT: $xzr = COPY renamable $[[REG3]]
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%0 : xseqpairsclass = IMPLICIT_DEF
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%1 : xseqpairsclass = IMPLICIT_DEF
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%2 : gpr64common = IMPLICIT_DEF
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%0 = CASPALX %0, %1, %2
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INLINEASM &" ", 0, 0, implicit def dead $x0, implicit def dead $x1, implicit def dead $x2, implicit def dead $x3, implicit def dead $x4, implicit def dead $x5, implicit def dead $x6, implicit def dead $x7, implicit def dead $x8, implicit def dead $x9, implicit def dead $x10, implicit def dead $x11, implicit def dead $x12, implicit def dead $x13, implicit def dead $x14, implicit def dead $x15, implicit def dead $x16, implicit def dead $x17, implicit def dead $x18, implicit def dead $x19, implicit def dead $x20, implicit def dead $x21, implicit def dead $x22, implicit def dead $x23, implicit def dead $x24, implicit def dead $x25, implicit def dead $x26, implicit def dead $x27, implicit def dead $x28, implicit def dead $fp, implicit def dead $lr
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$xzr = COPY %0.sube64
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$xzr = COPY %0.subo64
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...
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---
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# CHECK-LABEL: name: spill_reload_wseqpairs
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name: spill_reload_wseqpairs
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body: |
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bb.0:
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; Check the spill/reload sequence for the %0 register
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; CHECK: $[[REG0:[a-z0-9]+]]_[[REG1:[a-z0-9]+]] = CASPALW
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; CHECK-NEXT: STPWi renamable $[[REG0]], renamable $[[REG1]], %stack.0, 0, implicit killed $[[REG0]]_[[REG1]] :: (store 8 into %stack.0, align 4)
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; CHECK: INLINEASM
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; CHECK: renamable $[[REG2:[a-z0-9]+]], renamable $[[REG3:[a-z0-9]+]] = LDPWi %stack.0, 0, implicit-def $[[REG2]]_[[REG3]] :: (load 8 from %stack.0, align 4)
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; CHECK-NEXT: $xzr = COPY renamable $[[REG2]]
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; CHECK-NEXT: $xzr = COPY renamable $[[REG3]]
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%0 : wseqpairsclass = IMPLICIT_DEF
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%1 : wseqpairsclass = IMPLICIT_DEF
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%2 : gpr64common = IMPLICIT_DEF
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%0 = CASPALW %0, %1, %2
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INLINEASM &" ", 0, 0, implicit def dead $x0, implicit def dead $x1, implicit def dead $x2, implicit def dead $x3, implicit def dead $x4, implicit def dead $x5, implicit def dead $x6, implicit def dead $x7, implicit def dead $x8, implicit def dead $x9, implicit def dead $x10, implicit def dead $x11, implicit def dead $x12, implicit def dead $x13, implicit def dead $x14, implicit def dead $x15, implicit def dead $x16, implicit def dead $x17, implicit def dead $x18, implicit def dead $x19, implicit def dead $x20, implicit def dead $x21, implicit def dead $x22, implicit def dead $x23, implicit def dead $x24, implicit def dead $x25, implicit def dead $x26, implicit def dead $x27, implicit def dead $x28, implicit def dead $fp, implicit def dead $lr
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$xzr = COPY %0.sube32
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$xzr = COPY %0.subo32
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...
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