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Revert "[DAG] Extend visitSCALAR_TO_VECTOR optimization to truncated vector."

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This reverts commit r309680 which appears to be raising an assertion
in the test-suite.

llvm-svn: 309717
This commit is contained in:
Nirav Dave 2017-08-01 18:09:25 +00:00
parent d056e401d1
commit 2076795f08
3 changed files with 19 additions and 31 deletions
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37
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -15713,38 +15713,23 @@ SDValue DAGCombiner::visitSCALAR_TO_VECTOR(SDNode *N) {
EVT VT = N->getValueType(0);
// Replace a SCALAR_TO_VECTOR(EXTRACT_VECTOR_ELT(V,C0)) pattern
// with a VECTOR_SHUFFLE and possible truncate.
// with a VECTOR_SHUFFLE.
if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
SDValue InVec = InVal->getOperand(0);
SDValue EltNo = InVal->getOperand(1);
auto InVecT = InVec.getValueType();
ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(EltNo);
if (C0) {
SmallVector<int, 8> NewMask(InVecT.getVectorNumElements(), -1);
// FIXME: We could support implicit truncation if the shuffle can be
// scaled to a smaller vector scalar type.
ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(EltNo);
if (C0 && VT == InVec.getValueType() &&
VT.getScalarType() == InVal.getValueType()) {
SmallVector<int, 8> NewMask(VT.getVectorNumElements(), -1);
int Elt = C0->getZExtValue();
NewMask[0] = Elt;
SDValue Val;
if (VT.getVectorNumElements() <= InVecT.getVectorNumElements() &&
TLI.isShuffleMaskLegal(NewMask, VT)) {
Val = DAG.getVectorShuffle(InVecT, SDLoc(N), InVec,
DAG.getUNDEF(InVecT), NewMask);
// If the initial vector is the correct size this shuffle is a
// valid result.
if (VT == InVecT)
return Val;
// If not we must truncate the vector.
if (VT.getVectorNumElements() != InVecT.getVectorNumElements()) {
MVT IdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
SDValue ZeroIdx = DAG.getConstant(0, SDLoc(N), IdxTy);
EVT SubVT =
EVT::getVectorVT(*DAG.getContext(), InVecT.getVectorElementType(),
VT.getVectorNumElements());
Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), SubVT, Val,
ZeroIdx);
return Val;
}
}
if (TLI.isShuffleMaskLegal(NewMask, VT))
return DAG.getVectorShuffle(VT, SDLoc(N), InVec, DAG.getUNDEF(VT),
NewMask);
}
}

2
test/CodeGen/AArch64/arm64-neon-copy.ll
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@ -188,7 +188,7 @@ define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) {
define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) {
; CHECK-LABEL: ins2f1:
; CHECK: dup {{v[0-9]+}}.2d, {{v[0-9]+}}.d[1]
; CHECK: mov {{d[0-9]+}}, {{v[0-9]+}}.d[1]
%tmp3 = extractelement <2 x double> %tmp1, i32 1
%tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
ret <1 x double> %tmp4

11
test/CodeGen/AArch64/neon-scalar-copy.ll
View File

@ -79,7 +79,8 @@ define half @test_dup_hv8H_0(<8 x half> %v) #0 {
define <1 x i8> @test_vector_dup_bv16B(<16 x i8> %v1) #0 {
; CHECK-LABEL: test_vector_dup_bv16B:
; CHECK-NEXT: dup v0.16b, v0.b[14]
; CHECK-NEXT: umov [[W:w[0-9]+]], v0.b[14]
; CHECK-NEXT: fmov s0, [[W]]
; CHECK-NEXT: ret
%shuffle.i = shufflevector <16 x i8> %v1, <16 x i8> undef, <1 x i32> <i32 14>
ret <1 x i8> %shuffle.i
@ -95,7 +96,8 @@ define <1 x i8> @test_vector_dup_bv8B(<8 x i8> %v1) #0 {
define <1 x i16> @test_vector_dup_hv8H(<8 x i16> %v1) #0 {
; CHECK-LABEL: test_vector_dup_hv8H:
; CHECK-NEXT: dup v0.8h, v0.h[7]
; CHECK-NEXT: umov [[W:w[0-9]+]], v0.h[7]
; CHECK-NEXT: fmov s0, [[W]]
; CHECK-NEXT: ret
%shuffle.i = shufflevector <8 x i16> %v1, <8 x i16> undef, <1 x i32> <i32 7>
ret <1 x i16> %shuffle.i
@ -111,7 +113,8 @@ define <1 x i16> @test_vector_dup_hv4H(<4 x i16> %v1) #0 {
define <1 x i32> @test_vector_dup_sv4S(<4 x i32> %v1) #0 {
; CHECK-LABEL: test_vector_dup_sv4S:
; CHECK-NEXT: dup v0.4s, v0.s[3]
; CHECK-NEXT: mov [[W:w[0-9]+]], v0.s[3]
; CHECK-NEXT: fmov s0, [[W]]
; CHECK-NEXT: ret
%shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <1 x i32> <i32 3>
ret <1 x i32> %shuffle
@ -135,7 +138,7 @@ define <1 x i64> @test_vector_dup_dv2D(<2 x i64> %v1) #0 {
define <1 x i64> @test_vector_copy_dup_dv2D(<1 x i64> %a, <2 x i64> %c) #0 {
; CHECK-LABEL: test_vector_copy_dup_dv2D:
; CHECK-NEXT: dup v0.2d, v1.d[1]
; CHECK-NEXT: {{dup|mov}} {{d[0-9]+}}, {{v[0-9]+}}.d[1]
; CHECK-NEXT: ret
%vget_lane = extractelement <2 x i64> %c, i32 1
%vset_lane = insertelement <1 x i64> undef, i64 %vget_lane, i32 0