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[DebugInfo] Examine all uses of isDebugValue() for debug instructions.

Browse Source 
Because we create a new kind of debug instruction, DBG_LABEL, we need to
check all passes which use isDebugValue() to check MachineInstr is debug
instruction or not. When expelling debug instructions, we should expel
both DBG_VALUE and DBG_LABEL. So, I create a new function,
isDebugInstr(), in MachineInstr to check whether the MachineInstr is
debug instruction or not.

This patch has no new test case. I have run regression test and there is
no difference in regression test.

Differential Revision: https://reviews.llvm.org/D45342

Patch by Hsiangkai Wang.

llvm-svn: 331844
This commit is contained in:
Shiva Chen 2018-05-09 02:42:00 +00:00
parent 1127e5026d
commit 208c23a5a2
106 changed files with 233 additions and 217 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
include/llvm/CodeGen/MachineBasicBlock.h
View File

@ -700,7 +700,7 @@ public:
bool IsCond);
/// Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE
/// instructions. Return UnknownLoc if there is none.
/// and DBG_LABEL instructions. Return UnknownLoc if there is none.
DebugLoc findDebugLoc(instr_iterator MBBI);
DebugLoc findDebugLoc(iterator MBBI) {
return findDebugLoc(MBBI.getInstrIterator());
@ -897,7 +897,7 @@ public:
/// const_instr_iterator} and the respective reverse iterators.
template<typename IterT>
inline IterT skipDebugInstructionsForward(IterT It, IterT End) {
while (It != End && It->isDebugValue())
while (It != End && It->isDebugInstr())
It++;
return It;
}
@ -908,7 +908,7 @@ inline IterT skipDebugInstructionsForward(IterT It, IterT End) {
/// const_instr_iterator} and the respective reverse iterators.
template<class IterT>
inline IterT skipDebugInstructionsBackward(IterT It, IterT Begin) {
while (It != Begin && It->isDebugValue())
while (It != Begin && It->isDebugInstr())
It--;
return It;
}

3
include/llvm/CodeGen/MachineInstrBuilder.h
View File

@ -220,6 +220,9 @@ public:
assert((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable())
: true) &&
"first MDNode argument of a DBG_VALUE not a variable");
assert((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel())
: true) &&
"first MDNode argument of a DBG_LABEL not a label");
return *this;
}

4
include/llvm/CodeGen/SlotIndexes.h
View File

@ -578,9 +578,9 @@ class raw_ostream;
assert(!MI.isInsideBundle() &&
"Instructions inside bundles should use bundle start's slot.");
assert(mi2iMap.find(&MI) == mi2iMap.end() && "Instr already indexed.");
// Numbering DBG_VALUE instructions could cause code generation to be
// Numbering debug instructions could cause code generation to be
// affected by debug information.
assert(!MI.isDebugValue() && "Cannot number DBG_VALUE instructions.");
assert(!MI.isDebugInstr() && "Cannot number debug instructions.");
assert(MI.getParent() != nullptr && "Instr must be added to function.");

2
lib/CodeGen/AggressiveAntiDepBreaker.cpp
View File

@ -808,7 +808,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
I != E; --Count) {
MachineInstr &MI = *--I;
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
DEBUG(dbgs() << "Anti: ");

2
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
View File

@ -1059,7 +1059,7 @@ void AsmPrinter::EmitFunctionBody() {
for (auto &MI : MBB) {
// Print the assembly for the instruction.
if (!MI.isPosition() && !MI.isImplicitDef() && !MI.isKill() &&
!MI.isDebugValue()) {
!MI.isDebugInstr()) {
HasAnyRealCode = true;
++NumInstsInFunction;
}

6
lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
View File

@ -2589,8 +2589,8 @@ void CodeViewDebug::endFunctionImpl(const MachineFunction *MF) {
void CodeViewDebug::beginInstruction(const MachineInstr *MI) {
DebugHandlerBase::beginInstruction(MI);
// Ignore DBG_VALUE locations and function prologue.
if (!Asm || !CurFn || MI->isDebugValue() ||
// Ignore DBG_VALUE and DBG_LABEL locations and function prologue.
if (!Asm || !CurFn || MI->isDebugInstr() ||
MI->getFlag(MachineInstr::FrameSetup))
return;
@ -2599,7 +2599,7 @@ void CodeViewDebug::beginInstruction(const MachineInstr *MI) {
DebugLoc DL = MI->getDebugLoc();
if (!DL && MI->getParent() != PrevInstBB) {
for (const auto &NextMI : *MI->getParent()) {
if (NextMI.isDebugValue())
if (NextMI.isDebugInstr())
continue;
DL = NextMI.getDebugLoc();
if (DL)

6
lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp
View File

@ -198,7 +198,7 @@ void llvm::calculateDbgValueHistory(const MachineFunction *MF,
RegDescribedVarsMap RegVars;
for (const auto &MBB : *MF) {
for (const auto &MI : MBB) {
if (!MI.isDebugValue()) {
if (!MI.isDebugInstr()) {
// Not a DBG_VALUE instruction. It may clobber registers which describe
// some variables.
for (const MachineOperand &MO : MI.operands()) {
@ -234,6 +234,10 @@ void llvm::calculateDbgValueHistory(const MachineFunction *MF,
continue;
}
// Skip DBG_LABEL instructions.
if (MI.isDebugLabel())
continue;
assert(MI.getNumOperands() > 1 && "Invalid DBG_VALUE instruction!");
// Use the base variable (without any DW_OP_piece expressions)
// as index into History. The full variables including the

6
lib/CodeGen/BranchFolding.cpp
View File

@ -358,7 +358,7 @@ static unsigned ComputeCommonTailLength(MachineBasicBlock *MBB1,
// I1==MBB1->begin() work as expected.)
if (I1 == MBB1->begin() && I2 != MBB2->begin()) {
--I2;
while (I2->isDebugValue()) {
while (I2->isDebugInstr()) {
if (I2 == MBB2->begin())
return TailLen;
--I2;
@ -367,7 +367,7 @@ static unsigned ComputeCommonTailLength(MachineBasicBlock *MBB1,
}
if (I2 == MBB2->begin() && I1 != MBB1->begin()) {
--I1;
while (I1->isDebugValue()) {
while (I1->isDebugInstr()) {
if (I1 == MBB1->begin())
return TailLen;
--I1;
@ -1499,7 +1499,7 @@ ReoptimizeBlock:
// Check if DBG_VALUE at the end of PrevBB is identical to the
// DBG_VALUE at the beginning of MBB.
while (PrevBBIter != PrevBB.begin() && MBBIter != MBB->end()
&& PrevBBIter->isDebugValue() && MBBIter->isDebugValue()) {
&& PrevBBIter->isDebugInstr() && MBBIter->isDebugInstr()) {
if (!MBBIter->isIdenticalTo(*PrevBBIter))
break;
MachineInstr &DuplicateDbg = *MBBIter;

4
lib/CodeGen/BreakFalseDeps.cpp
View File

@ -176,7 +176,7 @@ bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx,
}
void BreakFalseDeps::processDefs(MachineInstr *MI) {
assert(!MI->isDebugValue() && "Won't process debug values");
assert(!MI->isDebugInstr() && "Won't process debug values");
// Break dependence on undef uses. Do this before updating LiveRegs below.
unsigned OpNum;
@ -244,7 +244,7 @@ void BreakFalseDeps::processBasicBlock(MachineBasicBlock *MBB) {
// and by then we'll have better information, so we can avoid doing the work
// to try and break dependencies now.
for (MachineInstr &MI : *MBB) {
if (!MI.isDebugValue())
if (!MI.isDebugInstr())
processDefs(&MI);
}
processUndefReads(MBB);

2
lib/CodeGen/CalcSpillWeights.cpp
View File

@ -236,7 +236,7 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &li, SlotIndex *start,
continue;
numInstr++;
if (mi->isIdentityCopy() || mi->isImplicitDef() || mi->isDebugValue())
if (mi->isIdentityCopy() || mi->isImplicitDef() || mi->isDebugInstr())
continue;
if (!visited.insert(mi).second)
continue;

4
lib/CodeGen/CriticalAntiDepBreaker.cpp
View File

@ -113,7 +113,7 @@ void CriticalAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count,
// FIXME: It may be possible to remove the isKill() restriction once PR18663
// has been properly fixed. There can be value in processing kills as seen in
// the AggressiveAntiDepBreaker class.
if (MI.isDebugValue() || MI.isKill())
if (MI.isDebugInstr() || MI.isKill())
return;
assert(Count < InsertPosIndex && "Instruction index out of expected range!");
@ -534,7 +534,7 @@ BreakAntiDependencies(const std::vector<SUnit> &SUnits,
// FIXME: It may be possible to remove the isKill() restriction once PR18663
// has been properly fixed. There can be value in processing kills as seen
// in the AggressiveAntiDepBreaker class.
if (MI.isDebugValue() || MI.isKill())
if (MI.isDebugInstr() || MI.isKill())
continue;
// Check if this instruction has a dependence on the critical path that

2
lib/CodeGen/EarlyIfConversion.cpp
View File

@ -195,7 +195,7 @@ bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) {
// terminators never have side effects or define any used register values.
for (MachineBasicBlock::iterator I = MBB->begin(),
E = MBB->getFirstTerminator(); I != E; ++I) {
if (I->isDebugValue())
if (I->isDebugInstr())
continue;
if (++InstrCount > BlockInstrLimit && !Stress) {

4
lib/CodeGen/ExecutionDomainFix.cpp
View File

@ -233,7 +233,7 @@ bool ExecutionDomainFix::visitInstr(MachineInstr *MI) {
}
void ExecutionDomainFix::processDefs(MachineInstr *MI, bool Kill) {
assert(!MI->isDebugValue() && "Won't process debug values");
assert(!MI->isDebugInstr() && "Won't process debug values");
const MCInstrDesc &MCID = MI->getDesc();
for (unsigned i = 0,
e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
@ -401,7 +401,7 @@ void ExecutionDomainFix::processBasicBlock(
// and by then we'll have better information, so we can avoid doing the work
// to try and break dependencies now.
for (MachineInstr &MI : *TraversedMBB.MBB) {
if (!MI.isDebugValue()) {
if (!MI.isDebugInstr()) {
bool Kill = false;
if (TraversedMBB.PrimaryPass)
Kill = visitInstr(&MI);

18
lib/CodeGen/IfConversion.cpp
View File

@ -948,7 +948,7 @@ void IfConverter::ScanInstructions(BBInfo &BBI,
BBI.ExtraCost2 = 0;
BBI.ClobbersPred = false;
for (MachineInstr &MI : make_range(Begin, End)) {
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
// It's unsafe to duplicate convergent instructions in this context, so set
@ -1726,14 +1726,14 @@ bool IfConverter::IfConvertDiamondCommon(
for (unsigned i = 0; i < NumDups1; ++DI1) {
if (DI1 == MBB1.end())
break;
if (!DI1->isDebugValue())
if (!DI1->isDebugInstr())
++i;
}
while (NumDups1 != 0) {
++DI2;
if (DI2 == MBB2.end())
break;
if (!DI2->isDebugValue())
if (!DI2->isDebugInstr())
--NumDups1;
}
@ -1767,7 +1767,7 @@ bool IfConverter::IfConvertDiamondCommon(
assert(DI1 != MBB1.begin());
--DI1;
// skip dbg_value instructions
if (!DI1->isDebugValue())
if (!DI1->isDebugInstr())
++i;
}
MBB1.erase(DI1, MBB1.end());
@ -1782,7 +1782,7 @@ bool IfConverter::IfConvertDiamondCommon(
// instructions could be found.
while (DI2 != MBB2.begin()) {
MachineBasicBlock::iterator Prev = std::prev(DI2);
if (!Prev->isBranch() && !Prev->isDebugValue())
if (!Prev->isBranch() && !Prev->isDebugInstr())
break;
DI2 = Prev;
}
@ -1793,7 +1793,7 @@ bool IfConverter::IfConvertDiamondCommon(
assert(DI2 != MBB2.begin());
--DI2;
// skip dbg_value instructions
if (!DI2->isDebugValue())
if (!DI2->isDebugInstr())
--NumDups2;
}
@ -1809,7 +1809,7 @@ bool IfConverter::IfConvertDiamondCommon(
SmallSet<unsigned, 4> ExtUses;
if (TII->isProfitableToUnpredicate(MBB1, MBB2)) {
for (const MachineInstr &FI : make_range(MBB2.begin(), DI2)) {
if (FI.isDebugValue())
if (FI.isDebugInstr())
continue;
SmallVector<unsigned, 4> Defs;
for (const MachineOperand &MO : FI.operands()) {
@ -2002,7 +2002,7 @@ void IfConverter::PredicateBlock(BBInfo &BBI,
bool AnyUnpred = false;
bool MaySpec = LaterRedefs != nullptr;
for (MachineInstr &I : make_range(BBI.BB->begin(), E)) {
if (I.isDebugValue() || TII->isPredicated(I))
if (I.isDebugInstr() || TII->isPredicated(I))
continue;
// It may be possible not to predicate an instruction if it's the 'true'
// side of a diamond and the 'false' side may re-define the instruction's
@ -2058,7 +2058,7 @@ void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
ToBBI.ExtraCost += NumCycles-1;
ToBBI.ExtraCost2 += ExtraPredCost;
if (!TII->isPredicated(I) && !MI->isDebugValue()) {
if (!TII->isPredicated(I) && !MI->isDebugInstr()) {
if (!TII->PredicateInstruction(*MI, Cond)) {
#ifndef NDEBUG
dbgs() << "Unable to predicate " << I << "!\n";

4
lib/CodeGen/InlineSpiller.cpp
View File

@ -617,7 +617,7 @@ void InlineSpiller::reMaterializeAll() {
MachineInstr &MI = *RegI++;
// Debug values are not allowed to affect codegen.
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
anyRemat |= reMaterializeFor(LI, MI);
@ -932,7 +932,7 @@ void InlineSpiller::spillAroundUses(unsigned Reg) {
MachineInstr *MI = &*(RegI++);
// Debug values are not allowed to affect codegen.
if (MI->isDebugValue()) {
if (MI->isDebugInstr()) {
// Modify DBG_VALUE now that the value is in a spill slot.
MachineBasicBlock *MBB = MI->getParent();
DEBUG(dbgs() << "Modifying debug info due to spill:\t" << *MI);

6
lib/CodeGen/LiveIntervals.cpp
View File

@ -1391,7 +1391,7 @@ private:
MachineBasicBlock::iterator Begin = MBB->begin();
while (MII != Begin) {
if ((--MII)->isDebugValue())
if ((--MII)->isDebugInstr())
continue;
SlotIndex Idx = Indexes->getInstructionIndex(*MII);
@ -1453,7 +1453,7 @@ void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin,
for (MachineBasicBlock::iterator I = End; I != Begin;) {
--I;
MachineInstr &MI = *I;
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
SlotIndex instrIdx = getInstructionIndex(MI);
@ -1550,7 +1550,7 @@ LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
for (MachineBasicBlock::iterator I = End; I != Begin;) {
--I;
MachineInstr &MI = *I;
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(),
MOE = MI.operands_end();

4
lib/CodeGen/LiveRangeShrink.cpp
View File

@ -130,7 +130,7 @@ bool LiveRangeShrink::runOnMachineFunction(MachineFunction &MF) {
for (MachineBasicBlock::iterator Next = MBB.begin(); Next != MBB.end();) {
MachineInstr &MI = *Next;
++Next;
if (MI.isPHI() || MI.isDebugValue())
if (MI.isPHI() || MI.isDebugInstr())
continue;
if (MI.mayStore())
SawStore = true;
@ -218,7 +218,7 @@ bool LiveRangeShrink::runOnMachineFunction(MachineFunction &MF) {
if (DefMO && Insert && NumEligibleUse > 1 && Barrier <= IOM[Insert]) {
MachineBasicBlock::iterator I = std::next(Insert->getIterator());
// Skip all the PHI and debug instructions.
while (I != MBB.end() && (I->isPHI() || I->isDebugValue()))
while (I != MBB.end() && (I->isPHI() || I->isDebugInstr()))
I = std::next(I);
if (I == MI.getIterator())
continue;

4
lib/CodeGen/LiveVariables.cpp
View File

@ -499,7 +499,7 @@ void LiveVariables::UpdatePhysRegDefs(MachineInstr &MI,
void LiveVariables::runOnInstr(MachineInstr &MI,
SmallVectorImpl<unsigned> &Defs) {
assert(!MI.isDebugValue());
assert(!MI.isDebugInstr());
// Process all of the operands of the instruction...
unsigned NumOperandsToProcess = MI.getNumOperands();
@ -576,7 +576,7 @@ void LiveVariables::runOnBlock(MachineBasicBlock *MBB, const unsigned NumRegs) {
DistanceMap.clear();
unsigned Dist = 0;
for (MachineInstr &MI : *MBB) {
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
DistanceMap.insert(std::make_pair(&MI, Dist++));

2
lib/CodeGen/LocalStackSlotAllocation.cpp
View File

@ -304,7 +304,7 @@ bool LocalStackSlotPass::insertFrameReferenceRegisters(MachineFunction &Fn) {
for (MachineInstr &MI : BB) {
// Debug value, stackmap and patchpoint instructions can't be out of
// range, so they don't need any updates.
if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STATEPOINT ||
if (MI.isDebugInstr() || MI.getOpcode() == TargetOpcode::STATEPOINT ||
MI.getOpcode() == TargetOpcode::STACKMAP ||
MI.getOpcode() == TargetOpcode::PATCHPOINT)
continue;

10
lib/CodeGen/MachineBasicBlock.cpp
View File

@ -174,7 +174,7 @@ MachineBasicBlock::SkipPHIsLabelsAndDebug(MachineBasicBlock::iterator I) {
const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
iterator E = end();
while (I != E && (I->isPHI() || I->isPosition() || I->isDebugValue() ||
while (I != E && (I->isPHI() || I->isPosition() || I->isDebugInstr() ||
TII->isBasicBlockPrologue(*I)))
++I;
// FIXME: This needs to change if we wish to bundle labels / dbg_values
@ -187,7 +187,7 @@ MachineBasicBlock::SkipPHIsLabelsAndDebug(MachineBasicBlock::iterator I) {
MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
iterator B = begin(), E = end(), I = E;
while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
while (I != B && ((--I)->isTerminator() || I->isDebugInstr()))
; /*noop */
while (I != E && !I->isTerminator())
++I;
@ -196,7 +196,7 @@ MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
MachineBasicBlock::instr_iterator MachineBasicBlock::getFirstInstrTerminator() {
instr_iterator B = instr_begin(), E = instr_end(), I = E;
while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
while (I != B && ((--I)->isTerminator() || I->isDebugInstr()))
; /*noop */
while (I != E && !I->isTerminator())
++I;
@ -214,7 +214,7 @@ MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() {
while (I != B) {
--I;
// Return instruction that starts a bundle.
if (I->isDebugValue() || I->isInsideBundle())
if (I->isDebugInstr() || I->isInsideBundle())
continue;
return I;
}
@ -1271,7 +1271,7 @@ DebugLoc MachineBasicBlock::findPrevDebugLoc(instr_iterator MBBI) {
if (MBBI == instr_begin()) return {};
// Skip debug declarations, we don't want a DebugLoc from them.
MBBI = skipDebugInstructionsBackward(std::prev(MBBI), instr_begin());
if (!MBBI->isDebugValue()) return MBBI->getDebugLoc();
if (!MBBI->isDebugInstr()) return MBBI->getDebugLoc();
return {};
}

4
lib/CodeGen/MachineCSE.cpp
View File

@ -314,7 +314,7 @@ bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
unsigned LookAheadLeft = LookAheadLimit;
while (LookAheadLeft) {
// Skip over dbg_value's.
while (I != E && I != EE && I->isDebugValue())
while (I != E && I != EE && I->isDebugInstr())
++I;
if (I == EE) {
@ -353,7 +353,7 @@ bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
bool MachineCSE::isCSECandidate(MachineInstr *MI) {
if (MI->isPosition() || MI->isPHI() || MI->isImplicitDef() || MI->isKill() ||
MI->isInlineAsm() || MI->isDebugValue())
MI->isInlineAsm() || MI->isDebugInstr())
return false;
// Ignore copies.

7
lib/CodeGen/MachineInstr.cpp
View File

@ -467,8 +467,8 @@ bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
return false;
}
}
// If DebugLoc does not match then two dbg.values are not identical.
if (isDebugValue())
// If DebugLoc does not match then two debug instructions are not identical.
if (isDebugInstr())
if (getDebugLoc() && Other.getDebugLoc() &&
getDebugLoc() != Other.getDebugLoc())
return false;
@ -975,7 +975,7 @@ bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
return false;
}
if (isPosition() || isDebugValue() || isTerminator() ||
if (isPosition() || isDebugInstr() || isTerminator() ||
hasUnmodeledSideEffects())
return false;
@ -1534,6 +1534,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
if (isIndirectDebugValue())
OS << " indirect";
}
// TODO: DBG_LABEL
if (AddNewLine)
OS << '\n';

8
lib/CodeGen/MachineScheduler.cpp
View File

@ -272,7 +272,7 @@ priorNonDebug(MachineBasicBlock::const_iterator I,
MachineBasicBlock::const_iterator Beg) {
assert(I != Beg && "reached the top of the region, cannot decrement");
while (--I != Beg) {
if (!I->isDebugValue())
if (!I->isDebugInstr())
break;
}
return I;
@ -292,7 +292,7 @@ static MachineBasicBlock::const_iterator
nextIfDebug(MachineBasicBlock::const_iterator I,
MachineBasicBlock::const_iterator End) {
for(; I != End; ++I) {
if (!I->isDebugValue())
if (!I->isDebugInstr())
break;
}
return I;
@ -482,7 +482,7 @@ getSchedRegions(MachineBasicBlock *MBB,
MachineInstr &MI = *std::prev(I);
if (isSchedBoundary(&MI, &*MBB, MF, TII))
break;
if (!MI.isDebugValue())
if (!MI.isDebugInstr())
// MBB::size() uses instr_iterator to count. Here we need a bundle to
// count as a single instruction.
++NumRegionInstrs;
@ -1055,7 +1055,7 @@ void ScheduleDAGMILive::initRegPressure() {
);
assert((BotRPTracker.getPos() == RegionEnd ||
(RegionEnd->isDebugValue() &&
(RegionEnd->isDebugInstr() &&
BotRPTracker.getPos() == priorNonDebug(RegionEnd, RegionBegin))) &&
"Can't find the region bottom");

2
lib/CodeGen/MachineSink.cpp
View File

@ -372,7 +372,7 @@ bool MachineSinking::ProcessBlock(MachineBasicBlock &MBB) {
if (!ProcessedBegin)
--I;
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
bool Joined = PerformTrivialForwardCoalescing(MI, &MBB);

2
lib/CodeGen/MachineTraceMetrics.cpp
View File

@ -653,7 +653,7 @@ static bool getDataDeps(const MachineInstr &UseMI,
SmallVectorImpl<DataDep> &Deps,
const MachineRegisterInfo *MRI) {
// Debug values should not be included in any calculations.
if (UseMI.isDebugValue())
if (UseMI.isDebugInstr())
return false;
bool HasPhysRegs = false;

2
lib/CodeGen/MachineVerifier.cpp
View File

@ -902,7 +902,7 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
// Other instructions must have one, unless they are inside a bundle.
if (LiveInts) {
bool mapped = !LiveInts->isNotInMIMap(*MI);
if (MI->isDebugValue()) {
if (MI->isDebugInstr()) {
if (mapped)
report("Debug instruction has a slot index", MI);
} else if (MI->isInsideBundle()) {

4
lib/CodeGen/PHIElimination.cpp
View File

@ -452,7 +452,7 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
KillInst = FirstTerm;
while (KillInst != opBlock.begin()) {
--KillInst;
if (KillInst->isDebugValue())
if (KillInst->isDebugInstr())
continue;
if (KillInst->readsRegister(SrcReg))
break;
@ -512,7 +512,7 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
KillInst = FirstTerm;
while (KillInst != opBlock.begin()) {
--KillInst;
if (KillInst->isDebugValue())
if (KillInst->isDebugInstr())
continue;
if (KillInst->readsRegister(SrcReg))
break;

4
lib/CodeGen/PeepholeOptimizer.cpp
View File

@ -1643,8 +1643,8 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
++MII;
LocalMIs.insert(MI);
// Skip debug values. They should not affect this peephole optimization.
if (MI->isDebugValue())
// Skip debug instructions. They should not affect this peephole optimization.
if (MI->isDebugInstr())
continue;
if (MI->isPosition())

4
lib/CodeGen/ReachingDefAnalysis.cpp
View File

@ -93,7 +93,7 @@ void ReachingDefAnalysis::leaveBasicBlock(
}
void ReachingDefAnalysis::processDefs(MachineInstr *MI) {
assert(!MI->isDebugValue() && "Won't process debug values");
assert(!MI->isDebugInstr() && "Won't process debug instructions");
unsigned MBBNumber = MI->getParent()->getNumber();
assert(MBBNumber < MBBReachingDefs.size() &&
@ -125,7 +125,7 @@ void ReachingDefAnalysis::processBasicBlock(
const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
enterBasicBlock(TraversedMBB);
for (MachineInstr &MI : *TraversedMBB.MBB) {
if (!MI.isDebugValue())
if (!MI.isDebugInstr())
processDefs(&MI);
}
leaveBasicBlock(TraversedMBB);

3
lib/CodeGen/RegAllocFast.cpp
View File

@ -910,6 +910,9 @@ void RegAllocFast::allocateBasicBlock(MachineBasicBlock &MBB) {
continue;
}
if (MI.isDebugLabel())
continue;
// If this is a copy, we may be able to coalesce.
unsigned CopySrcReg = 0;
unsigned CopyDstReg = 0;

2
lib/CodeGen/RegisterCoalescer.cpp
View File

@ -2578,7 +2578,7 @@ taintExtent(unsigned ValNo, LaneBitmask TaintedLanes, JoinVals &Other,
bool JoinVals::usesLanes(const MachineInstr &MI, unsigned Reg, unsigned SubIdx,
LaneBitmask Lanes) const {
if (MI.isDebugValue())
if (MI.isDebugInstr())
return false;
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || MO.isDef() || MO.getReg() != Reg)

6
lib/CodeGen/RegisterPressure.cpp
View File

@ -748,7 +748,7 @@ void RegPressureTracker::bumpDeadDefs(ArrayRef<RegisterMaskPair> DeadDefs) {
/// instruction independent of liveness.
void RegPressureTracker::recede(const RegisterOperands &RegOpers,
SmallVectorImpl<RegisterMaskPair> *LiveUses) {
assert(!CurrPos->isDebugValue());
assert(!CurrPos->isDebugInstr());
// Boost pressure for all dead defs together.
bumpDeadDefs(RegOpers.DeadDefs);
@ -1019,7 +1019,7 @@ static void computeMaxPressureDelta(ArrayRef<unsigned> OldMaxPressureVec,
/// This is intended for speculative queries. It leaves pressure inconsistent
/// with the current position, so must be restored by the caller.
void RegPressureTracker::bumpUpwardPressure(const MachineInstr *MI) {
assert(!MI->isDebugValue() && "Expect a nondebug instruction.");
assert(!MI->isDebugInstr() && "Expect a nondebug instruction.");
SlotIndex SlotIdx;
if (RequireIntervals)
@ -1260,7 +1260,7 @@ LaneBitmask RegPressureTracker::getLiveThroughAt(unsigned RegUnit,
/// This is intended for speculative queries. It leaves pressure inconsistent
/// with the current position, so must be restored by the caller.
void RegPressureTracker::bumpDownwardPressure(const MachineInstr *MI) {
assert(!MI->isDebugValue() && "Expect a nondebug instruction.");
assert(!MI->isDebugInstr() && "Expect a nondebug instruction.");
SlotIndex SlotIdx;
if (RequireIntervals)

8
lib/CodeGen/RegisterScavenging.cpp
View File

@ -111,7 +111,7 @@ void RegScavenger::determineKillsAndDefs() {
assert(Tracking && "Must be tracking to determine kills and defs");
MachineInstr &MI = *MBBI;
assert(!MI.isDebugValue() && "Debug values have no kills or defs");
assert(!MI.isDebugInstr() && "Debug values have no kills or defs");
// Find out which registers are early clobbered, killed, defined, and marked
// def-dead in this instruction.
@ -158,7 +158,7 @@ void RegScavenger::unprocess() {
assert(Tracking && "Cannot unprocess because we're not tracking");
MachineInstr &MI = *MBBI;
if (!MI.isDebugValue()) {
if (!MI.isDebugInstr()) {
determineKillsAndDefs();
// Commit the changes.
@ -195,7 +195,7 @@ void RegScavenger::forward() {
I->Restore = nullptr;
}
if (MI.isDebugValue())
if (MI.isDebugInstr())
return;
determineKillsAndDefs();
@ -318,7 +318,7 @@ unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
bool inVirtLiveRange = false;
for (++MI; InstrLimit > 0 && MI != ME; ++MI, --InstrLimit) {
if (MI->isDebugValue()) {
if (MI->isDebugInstr()) {
++InstrLimit; // Don't count debug instructions
continue;
}

9
lib/CodeGen/ScheduleDAGInstrs.cpp
View File

@ -533,7 +533,7 @@ void ScheduleDAGInstrs::initSUnits() {
SUnits.reserve(NumRegionInstrs);
for (MachineInstr &MI : make_range(RegionBegin, RegionEnd)) {
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
SUnit *SU = newSUnit(&MI);
@ -764,6 +764,9 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
DbgMI = &MI;
continue;
}
if (MI.isDebugLabel())
continue;
SUnit *SU = MISUnitMap[&MI];
assert(SU && "No SUnit mapped to this MI");
@ -1052,7 +1055,7 @@ void ScheduleDAGInstrs::fixupKills(MachineBasicBlock &MBB) {
// Examine block from end to start...
for (MachineInstr &MI : make_range(MBB.rbegin(), MBB.rend())) {
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
// Update liveness. Registers that are defed but not used in this
@ -1088,7 +1091,7 @@ void ScheduleDAGInstrs::fixupKills(MachineBasicBlock &MBB) {
while (I->isBundledWithSucc())
++I;
do {
if (!I->isDebugValue())
if (!I->isDebugInstr())
toggleKills(MRI, LiveRegs, *I, true);
--I;
} while(I != First);

4
lib/CodeGen/SlotIndexes.cpp
View File

@ -74,7 +74,7 @@ bool SlotIndexes::runOnMachineFunction(MachineFunction &fn) {
SlotIndex blockStartIndex(&indexList.back(), SlotIndex::Slot_Block);
for (MachineInstr &MI : MBB) {
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
// Insert a store index for the instr.
@ -245,7 +245,7 @@ void SlotIndexes::repairIndexesInRange(MachineBasicBlock *MBB,
for (MachineBasicBlock::iterator I = End; I != Begin;) {
--I;
MachineInstr &MI = *I;
if (!MI.isDebugValue() && mi2iMap.find(&MI) == mi2iMap.end())
if (!MI.isDebugInstr() && mi2iMap.find(&MI) == mi2iMap.end())
insertMachineInstrInMaps(MI);
}
}

2
lib/CodeGen/SplitKit.cpp
View File

@ -860,7 +860,7 @@ void SplitEditor::removeBackCopies(SmallVectorImpl<VNInfo*> &Copies) {
MachineBasicBlock::iterator MBBI(MI);
bool AtBegin;
do AtBegin = MBBI == MBB->begin();
while (!AtBegin && (--MBBI)->isDebugValue());
while (!AtBegin && (--MBBI)->isDebugInstr());
DEBUG(dbgs() << "Removing " << Def << '\t' << *MI);
LIS.removeVRegDefAt(*LI, Def);

6
lib/CodeGen/StackColoring.cpp
View File

@ -606,7 +606,7 @@ bool StackColoring::isLifetimeStartOrEnd(const MachineInstr &MI,
return true;
}
} else if (LifetimeStartOnFirstUse && !ProtectFromEscapedAllocas) {
if (!MI.isDebugValue()) {
if (!MI.isDebugInstr()) {
bool found = false;
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isFI())
@ -1000,7 +1000,7 @@ void StackColoring::remapInstructions(DenseMap<int, int> &SlotRemap) {
bool TouchesMemory = I.mayLoad() || I.mayStore();
// If we *don't* protect the user from escaped allocas, don't bother
// validating the instructions.
if (!I.isDebugValue() && TouchesMemory && ProtectFromEscapedAllocas) {
if (!I.isDebugInstr() && TouchesMemory && ProtectFromEscapedAllocas) {
SlotIndex Index = Indexes->getInstructionIndex(I);
const LiveInterval *Interval = &*Intervals[FromSlot];
assert(Interval->find(Index) != Interval->end() &&
@ -1074,7 +1074,7 @@ void StackColoring::removeInvalidSlotRanges() {
for (MachineBasicBlock &BB : *MF)
for (MachineInstr &I : BB) {
if (I.getOpcode() == TargetOpcode::LIFETIME_START ||
I.getOpcode() == TargetOpcode::LIFETIME_END || I.isDebugValue())
I.getOpcode() == TargetOpcode::LIFETIME_END || I.isDebugInstr())
continue;
// Some intervals are suspicious! In some cases we find address

2
lib/CodeGen/StackSlotColoring.cpp
View File

@ -423,7 +423,7 @@ bool StackSlotColoring::RemoveDeadStores(MachineBasicBlock* MBB) {
if (!(LoadReg = TII->isLoadFromStackSlot(*I, FirstSS, LoadSize)))
continue;
// Skip the ...pseudo debugging... instructions between a load and store.
while ((NextMI != E) && NextMI->isDebugValue()) {
while ((NextMI != E) && NextMI->isDebugInstr()) {
++NextMI;
++I;
}

20
lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -290,8 +290,8 @@ sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
unsigned NumVisited = 0;
for (MachineInstr &OtherMI : make_range(std::next(OldPos), KillPos)) {
// DBG_VALUE cannot be counted against the limit.
if (OtherMI.isDebugValue())
// Debug instructions cannot be counted against the limit.
if (OtherMI.isDebugInstr())
continue;
if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
return false;
@ -940,8 +940,8 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
MachineBasicBlock::iterator KillPos = KillMI;
++KillPos;
for (MachineInstr &OtherMI : make_range(End, KillPos)) {
// DBG_VALUE cannot be counted against the limit.
if (OtherMI.isDebugValue())
// Debug instructions cannot be counted against the limit.
if (OtherMI.isDebugInstr())
continue;
if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
return false;
@ -985,7 +985,7 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
}
// Move debug info as well.
while (Begin != MBB->begin() && std::prev(Begin)->isDebugValue())
while (Begin != MBB->begin() && std::prev(Begin)->isDebugInstr())
--Begin;
nmi = End;
@ -1114,8 +1114,8 @@ rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
unsigned NumVisited = 0;
for (MachineInstr &OtherMI :
make_range(mi, MachineBasicBlock::iterator(KillMI))) {
// DBG_VALUE cannot be counted against the limit.
if (OtherMI.isDebugValue())
// Debug instructions cannot be counted against the limit.
if (OtherMI.isDebugInstr())
continue;
if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
return false;
@ -1162,11 +1162,11 @@ rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
// Move the old kill above MI, don't forget to move debug info as well.
MachineBasicBlock::iterator InsertPos = mi;
while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugValue())
while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugInstr())
--InsertPos;
MachineBasicBlock::iterator From = KillMI;
MachineBasicBlock::iterator To = std::next(From);
while (std::prev(From)->isDebugValue())
while (std::prev(From)->isDebugInstr())
--From;
MBB->splice(InsertPos, MBB, From, To);
@ -1699,7 +1699,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
MachineBasicBlock::iterator nmi = std::next(mi);
// Don't revisit an instruction previously converted by target. It may
// contain undef register operands (%noreg), which are not handled.
if (mi->isDebugValue() || SunkInstrs.count(&*mi)) {
if (mi->isDebugInstr() || SunkInstrs.count(&*mi)) {
mi = nmi;
continue;
}

2
lib/Target/AArch64/AArch64ConditionalCompares.cpp
View File

@ -392,7 +392,7 @@ bool SSACCmpConv::canSpeculateInstrs(MachineBasicBlock *MBB,
// Check all instructions, except the terminators. It is assumed that
// terminators never have side effects or define any used register values.
for (auto &I : make_range(MBB->begin(), MBB->getFirstTerminator())) {
if (I.isDebugValue())
if (I.isDebugInstr())
continue;
if (++InstrCount > BlockInstrLimit && !Stress) {

2
lib/Target/AArch64/AArch64FrameLowering.cpp
View File

@ -162,7 +162,7 @@ static unsigned estimateRSStackSizeLimit(MachineFunction &MF) {
// realistically that's not a big deal at this stage of the game.
for (MachineBasicBlock &MBB : MF) {
for (MachineInstr &MI : MBB) {
if (MI.isDebugValue() || MI.isPseudo() ||
if (MI.isDebugInstr() || MI.isPseudo() ||
MI.getOpcode() == AArch64::ADDXri ||
MI.getOpcode() == AArch64::ADDSXri)
continue;

2
lib/Target/AArch64/AArch64InstrInfo.cpp
View File

@ -5044,7 +5044,7 @@ AArch64InstrInfo::getOutliningType(MachineBasicBlock::iterator &MIT,
return MachineOutlinerInstrType::Illegal;
// Don't allow debug values to impact outlining type.
if (MI.isDebugValue() || MI.isIndirectDebugValue())
if (MI.isDebugInstr() || MI.isIndirectDebugValue())
return MachineOutlinerInstrType::Invisible;
// At this point, KILL instructions don't really tell us much so we can go

4
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
View File

@ -511,7 +511,7 @@ uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const
// TODO: CodeSize should account for multiple functions.
// TODO: Should we count size of debug info?
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
CodeSize += TII->getInstSizeInBytes(MI);
@ -652,7 +652,7 @@ AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
continue;
case AMDGPU::NoRegister:
assert(MI.isDebugValue());
assert(MI.isDebugInstr());
continue;
case AMDGPU::VCC:

2
lib/Target/AMDGPU/GCNHazardRecognizer.cpp
View File

@ -634,7 +634,7 @@ int GCNHazardRecognizer::checkRFEHazards(MachineInstr *RFE) {
}
int GCNHazardRecognizer::checkAnyInstHazards(MachineInstr *MI) {
if (MI->isDebugValue())
if (MI->isDebugInstr())
return 0;
const SIRegisterInfo *TRI = ST.getRegisterInfo();

8
lib/Target/AMDGPU/GCNIterativeScheduler.cpp
View File

@ -69,14 +69,14 @@ static void printRegion(raw_ostream &OS,
auto I = Begin;
MaxInstNum = std::max(MaxInstNum, 1u);
for (; I != End && MaxInstNum; ++I, --MaxInstNum) {
if (!I->isDebugValue() && LIS)
if (!I->isDebugInstr() && LIS)
OS << LIS->getInstructionIndex(*I);
OS << '\t' << *I;
}
if (I != End) {
OS << "\t...\n";
I = std::prev(End);
if (!I->isDebugValue() && LIS)
if (!I->isDebugInstr() && LIS)
OS << LIS->getInstructionIndex(*I);
OS << '\t' << *I;
}
@ -384,10 +384,10 @@ void GCNIterativeScheduler::scheduleRegion(Region &R, Range &&Schedule,
if (MI != &*Top) {
BB->remove(MI);
BB->insert(Top, MI);
if (!MI->isDebugValue())
if (!MI->isDebugInstr())
LIS->handleMove(*MI, true);
}
if (!MI->isDebugValue()) {
if (!MI->isDebugInstr()) {
// Reset read - undef flags and update them later.
for (auto &Op : MI->operands())
if (Op.isReg() && Op.isDef())

2
lib/Target/AMDGPU/GCNRegPressure.cpp
View File

@ -301,7 +301,7 @@ void GCNUpwardRPTracker::recede(const MachineInstr &MI) {
LastTrackedMI = &MI;
if (MI.isDebugValue())
if (MI.isDebugInstr())
return;
auto const RegUses = collectVirtualRegUses(MI, LIS, *MRI);

6
lib/Target/AMDGPU/GCNSchedStrategy.cpp
View File

@ -388,13 +388,13 @@ void GCNScheduleDAGMILive::schedule() {
DEBUG(dbgs() << "Attempting to revert scheduling.\n");
RegionEnd = RegionBegin;
for (MachineInstr *MI : Unsched) {
if (MI->isDebugValue())
if (MI->isDebugInstr())
continue;
if (MI->getIterator() != RegionEnd) {
BB->remove(MI);
BB->insert(RegionEnd, MI);
if (!MI->isDebugValue())
if (!MI->isDebugInstr())
LIS->handleMove(*MI, true);
}
// Reset read-undef flags and update them later.
@ -403,7 +403,7 @@ void GCNScheduleDAGMILive::schedule() {
Op.setIsUndef(false);
RegisterOperands RegOpers;
RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false);
if (!MI->isDebugValue()) {
if (!MI->isDebugInstr()) {
if (ShouldTrackLaneMasks) {
// Adjust liveness and add missing dead+read-undef flags.
SlotIndex SlotIdx = LIS->getInstructionIndex(*MI).getRegSlot();

4
lib/Target/AMDGPU/SIDebuggerInsertNops.cpp
View File

@ -78,8 +78,8 @@ bool SIDebuggerInsertNops::runOnMachineFunction(MachineFunction &MF) {
for (auto &MBB : MF) {
for (auto MI = MBB.begin(); MI != MBB.end(); ++MI) {
// Skip DBG_VALUE instructions and instructions without location.
if (MI->isDebugValue() || !MI->getDebugLoc())
// Skip debug instructions and instructions without location.
if (MI->isDebugInstr() || !MI->getDebugLoc())
continue;
// Insert nop instruction if line number does not have nop inserted.

2
lib/Target/AMDGPU/SIInsertWaitcnts.cpp
View File

@ -897,7 +897,7 @@ void SIInsertWaitcnts::generateWaitcntInstBefore(
setForceEmitWaitcnt();
bool IsForceEmitWaitcnt = isForceEmitWaitcnt();
if (MI.isDebugValue() &&
if (MI.isDebugInstr() &&
// TODO: any other opcode?
!NeedLineMapping) {
return;

2
lib/Target/AMDGPU/SIMachineScheduler.cpp
View File

@ -1280,7 +1280,7 @@ static MachineBasicBlock::iterator
nextIfDebug(MachineBasicBlock::iterator I,
MachineBasicBlock::const_iterator End) {
for (; I != End; ++I) {
if (!I->isDebugValue())
if (!I->isDebugInstr())
break;
}
return I;

2
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
View File

@ -134,7 +134,7 @@ bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) {
}
while (I != E) {
if (I->isDebugValue()) {
if (I->isDebugInstr()) {
I = std::next(I);
continue;
}

2
lib/Target/ARC/ARCInstrInfo.cpp
View File

@ -173,7 +173,7 @@ bool ARCInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
bool CantAnalyze = false;
// Skip over DEBUG values and predicated nonterminators.
while (I->isDebugValue() || !I->isTerminator()) {
while (I->isDebugInstr() || !I->isTerminator()) {
if (I == MBB.begin())
return false;
--I;

8
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -331,7 +331,7 @@ bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
bool CantAnalyze = false;
// Skip over DEBUG values and predicated nonterminators.
while (I->isDebugValue() || !I->isTerminator()) {
while (I->isDebugInstr() || !I->isTerminator()) {
if (I == MBB.begin())
return false;
--I;
@ -1815,7 +1815,7 @@ bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
// considered a scheduling hazard, which is wrong. It should be the actual
// instruction preceding the dbg_value instruction(s), just like it is
// when debug info is not present.
if (MI.isDebugValue())
if (MI.isDebugInstr())
return false;
// Terminators and labels can't be scheduled around.
@ -1829,8 +1829,8 @@ bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
// to the t2IT instruction. The added compile time and complexity does not
// seem worth it.
MachineBasicBlock::const_iterator I = MI;
// Make sure to skip any dbg_value instructions
while (++I != MBB->end() && I->isDebugValue())
// Make sure to skip any debug instructions
while (++I != MBB->end() && I->isDebugInstr())
;
if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
return true;

2
lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -701,7 +701,7 @@ initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
WaterList.push_back(&MBB);
for (MachineInstr &I : MBB) {
if (I.isDebugValue())
if (I.isDebugInstr())
continue;
unsigned Opc = I.getOpcode();

4
lib/Target/ARM/ARMHazardRecognizer.cpp
View File

@ -37,7 +37,7 @@ ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
MachineInstr *MI = SU->getInstr();
if (!MI->isDebugValue()) {
if (!MI->isDebugInstr()) {
// Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following
// a VMLA / VMLS will cause 4 cycle stall.
const MCInstrDesc &MCID = MI->getDesc();
@ -81,7 +81,7 @@ void ARMHazardRecognizer::Reset() {
void ARMHazardRecognizer::EmitInstruction(SUnit *SU) {
MachineInstr *MI = SU->getInstr();
if (!MI->isDebugValue()) {
if (!MI->isDebugInstr()) {
LastMI = MI;
FpMLxStalls = 0;
}

16
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -1198,7 +1198,7 @@ findIncDecBefore(MachineBasicBlock::iterator MBBI, unsigned Reg,
// Skip debug values.
MachineBasicBlock::iterator PrevMBBI = std::prev(MBBI);
while (PrevMBBI->isDebugValue() && PrevMBBI != BeginMBBI)
while (PrevMBBI->isDebugInstr() && PrevMBBI != BeginMBBI)
--PrevMBBI;
Offset = isIncrementOrDecrement(*PrevMBBI, Reg, Pred, PredReg);
@ -1214,7 +1214,7 @@ findIncDecAfter(MachineBasicBlock::iterator MBBI, unsigned Reg,
MachineBasicBlock::iterator EndMBBI = MBB.end();
MachineBasicBlock::iterator NextMBBI = std::next(MBBI);
// Skip debug values.
while (NextMBBI != EndMBBI && NextMBBI->isDebugValue())
while (NextMBBI != EndMBBI && NextMBBI->isDebugInstr())
++NextMBBI;
if (NextMBBI == EndMBBI)
return EndMBBI;
@ -1807,7 +1807,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
MBBI = I;
--Position;
// Fallthrough to look into existing chain.
} else if (MBBI->isDebugValue()) {
} else if (MBBI->isDebugInstr()) {
continue;
} else if (MBBI->getOpcode() == ARM::t2LDRDi8 ||
MBBI->getOpcode() == ARM::t2STRDi8) {
@ -1891,8 +1891,8 @@ bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) {
MBBI->getOpcode() == ARM::tBX_RET ||
MBBI->getOpcode() == ARM::MOVPCLR)) {
MachineBasicBlock::iterator PrevI = std::prev(MBBI);
// Ignore any DBG_VALUE instructions.
while (PrevI->isDebugValue() && PrevI != MBB.begin())
// Ignore any debug instructions.
while (PrevI->isDebugInstr() && PrevI != MBB.begin())
--PrevI;
MachineInstr &PrevMI = *PrevI;
unsigned Opcode = PrevMI.getOpcode();
@ -2063,7 +2063,7 @@ static bool IsSafeAndProfitableToMove(bool isLd, unsigned Base,
// Are there stores / loads / calls between them?
SmallSet<unsigned, 4> AddedRegPressure;
while (++I != E) {
if (I->isDebugValue() || MemOps.count(&*I))
if (I->isDebugInstr() || MemOps.count(&*I))
continue;
if (I->isCall() || I->isTerminator() || I->hasUnmodeledSideEffects())
return false;
@ -2253,7 +2253,7 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
// This is the new location for the loads / stores.
MachineBasicBlock::iterator InsertPos = isLd ? FirstOp : LastOp;
while (InsertPos != MBB->end() &&
(MemOps.count(&*InsertPos) || InsertPos->isDebugValue()))
(MemOps.count(&*InsertPos) || InsertPos->isDebugInstr()))
++InsertPos;
// If we are moving a pair of loads / stores, see if it makes sense
@ -2355,7 +2355,7 @@ ARMPreAllocLoadStoreOpt::RescheduleLoadStoreInstrs(MachineBasicBlock *MBB) {
break;
}
if (!MI.isDebugValue())
if (!MI.isDebugInstr())
MI2LocMap[&MI] = ++Loc;
if (!isMemoryOp(MI))

4
lib/Target/ARM/Thumb2ITBlockPass.cpp
View File

@ -183,7 +183,7 @@ Thumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI,
// If not, then there is nothing to be gained by moving the copy.
MachineBasicBlock::iterator I = MI; ++I;
MachineBasicBlock::iterator E = MI->getParent()->end();
while (I != E && I->isDebugValue())
while (I != E && I->isDebugInstr())
++I;
if (I != E) {
unsigned NPredReg = 0;
@ -237,7 +237,7 @@ bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) {
// block so check the instruction we just put in the block.
for (; MBBI != E && Pos &&
(!MI->isBranch() && !MI->isReturn()) ; ++MBBI) {
if (MBBI->isDebugValue())
if (MBBI->isDebugInstr())
continue;
MachineInstr *NMI = &*MBBI;

4
lib/Target/ARM/Thumb2InstrInfo.cpp
View File

@ -82,7 +82,7 @@ Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
MachineBasicBlock::iterator E = MBB->begin();
unsigned Count = 4; // At most 4 instructions in an IT block.
while (Count && MBBI != E) {
if (MBBI->isDebugValue()) {
if (MBBI->isDebugInstr()) {
--MBBI;
continue;
}
@ -109,7 +109,7 @@ Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
bool
Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) const {
while (MBBI->isDebugValue()) {
while (MBBI->isDebugInstr()) {
++MBBI;
if (MBBI == MBB.end())
return false;

2
lib/Target/ARM/Thumb2SizeReduction.cpp
View File

@ -1033,7 +1033,7 @@ bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
BundleMI = MI;
continue;
}
if (MI->isDebugValue())
if (MI->isDebugInstr())
continue;
LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR);

2
lib/Target/ARM/ThumbRegisterInfo.cpp
View File

@ -475,7 +475,7 @@ bool ThumbRegisterInfo::saveScavengerRegister(
// before that instead and adjust the UseMI.
bool done = false;
for (MachineBasicBlock::iterator II = I; !done && II != UseMI ; ++II) {
if (II->isDebugValue())
if (II->isDebugInstr())
continue;
// If this instruction affects R12, adjust our restore point.
for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) {

4
lib/Target/AVR/AVRInstrInfo.cpp
View File

@ -273,7 +273,7 @@ bool AVRInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
while (I != MBB.begin()) {
--I;
if (I->isDebugValue()) {
if (I->isDebugInstr()) {
continue;
}
@ -444,7 +444,7 @@ unsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB,
while (I != MBB.begin()) {
--I;
if (I->isDebugValue()) {
if (I->isDebugInstr()) {
continue;
}
//:TODO: add here the missing jmp instructions once they are implemented

4
lib/Target/BPF/BPFInstrInfo.cpp
View File

@ -93,7 +93,7 @@ bool BPFInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I = MBB.end();
while (I != MBB.begin()) {
--I;
if (I->isDebugValue())
if (I->isDebugInstr())
continue;
// Working from the bottom, when we see a non-terminator
@ -168,7 +168,7 @@ unsigned BPFInstrInfo::removeBranch(MachineBasicBlock &MBB,
while (I != MBB.begin()) {
--I;
if (I->isDebugValue())
if (I->isDebugInstr())
continue;
if (I->getOpcode() != BPF::JMP)
break;

2
lib/Target/Hexagon/BitTracker.cpp
View File

@ -843,7 +843,7 @@ void BT::visitPHI(const MachineInstr &PI) {
void BT::visitNonBranch(const MachineInstr &MI) {
if (Trace)
dbgs() << "Visit MI(" << printMBBReference(*MI.getParent()) << "): " << MI;
if (MI.isDebugValue())
if (MI.isDebugInstr())
return;
assert(!MI.isBranch() && "Unexpected branch instruction");

2
lib/Target/Hexagon/HexagonAsmPrinter.cpp
View File

@ -760,7 +760,7 @@ void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) {
MachineBasicBlock::const_instr_iterator MII = MI->getIterator();
for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
if (!MII->isDebugValue() && !MII->isImplicitDef())
if (!MII->isDebugInstr() && !MII->isImplicitDef())
HexagonLowerToMC(MCII, &*MII, MCB, *this);
} else {
HexagonLowerToMC(MCII, MI, MCB, *this);

4
lib/Target/Hexagon/HexagonBlockRanges.cpp
View File

@ -160,7 +160,7 @@ HexagonBlockRanges::InstrIndexMap::InstrIndexMap(MachineBasicBlock &B)
IndexType Idx = IndexType::First;
First = Idx;
for (auto &In : B) {
if (In.isDebugValue())
if (In.isDebugInstr())
continue;
assert(getIndex(&In) == IndexType::None && "Instruction already in map");
Map.insert(std::make_pair(Idx, &In));
@ -314,7 +314,7 @@ void HexagonBlockRanges::computeInitialLiveRanges(InstrIndexMap &IndexMap,
RegisterSet Defs, Clobbers;
for (auto &In : B) {
if (In.isDebugValue())
if (In.isDebugInstr())
continue;
IndexType Index = IndexMap.getIndex(&In);
// Process uses first.

8
lib/Target/Hexagon/HexagonConstPropagation.cpp
View File

@ -799,7 +799,7 @@ bool MachineConstPropagator::computeBlockSuccessors(const MachineBasicBlock *MB,
SetVector<const MachineBasicBlock*> &Targets) {
MachineBasicBlock::const_iterator FirstBr = MB->end();
for (const MachineInstr &MI : *MB) {
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
if (MI.isBranch()) {
FirstBr = MI.getIterator();
@ -814,7 +814,7 @@ bool MachineConstPropagator::computeBlockSuccessors(const MachineBasicBlock *MB,
for (MachineBasicBlock::const_iterator I = FirstBr; I != End; ++I) {
const MachineInstr &MI = *I;
// Can there be debug instructions between branches?
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
if (!InstrExec.count(&MI))
continue;
@ -896,7 +896,7 @@ void MachineConstPropagator::propagate(MachineFunction &MF) {
// If the successor block just became executable, visit all instructions.
// To see if this is the first time we're visiting it, check the first
// non-debug instruction to see if it is executable.
while (It != End && It->isDebugValue())
while (It != End && It->isDebugInstr())
++It;
assert(It == End || !It->isPHI());
// If this block has been visited, go on to the next one.
@ -905,7 +905,7 @@ void MachineConstPropagator::propagate(MachineFunction &MF) {
// For now, scan all non-branch instructions. Branches require different
// processing.
while (It != End && !It->isBranch()) {
if (!It->isDebugValue()) {
if (!It->isDebugInstr()) {
InstrExec.insert(&*It);
visitNonBranch(*It);
}

12
lib/Target/Hexagon/HexagonCopyToCombine.cpp
View File

@ -300,7 +300,7 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr &I1,
// * reads I2's def reg
// * or has unmodelled side effects
// we can't move I2 across it.
if (I->isDebugValue())
if (I->isDebugInstr())
continue;
if (isUnsafeToMoveAcross(*I, I2UseReg, I2DestReg, TRI)) {
@ -358,7 +358,7 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr &I1,
// to remove the implicit killed %d4 operand. For now, we are
// conservative and disallow the move.
// we can't move I1 across it.
if (MI.isDebugValue()) {
if (MI.isDebugInstr()) {
if (MI.readsRegister(I1DestReg, TRI)) // Move this instruction after I2.
DbgMItoMove.push_back(&MI);
continue;
@ -396,7 +396,7 @@ void
HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {
DenseMap<unsigned, MachineInstr *> LastDef;
for (MachineInstr &MI : BB) {
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
// Mark TFRs that feed a potential new value store as such.
@ -423,7 +423,7 @@ HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {
MachineBasicBlock::iterator It(DefInst);
unsigned NumInstsToDef = 0;
while (&*It != &MI) {
if (!It->isDebugValue())
if (!It->isDebugInstr())
++NumInstsToDef;
++It;
}
@ -489,7 +489,7 @@ bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {
MI != End;) {
MachineInstr &I1 = *MI++;
if (I1.isDebugValue())
if (I1.isDebugInstr())
continue;
// Don't combine a TFR whose user could be newified (instructions that
@ -526,7 +526,7 @@ MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr &I1,
bool &DoInsertAtI1,
bool AllowC64) {
MachineBasicBlock::iterator I2 = std::next(MachineBasicBlock::iterator(I1));
while (I2 != I1.getParent()->end() && I2->isDebugValue())
while (I2 != I1.getParent()->end() && I2->isDebugInstr())
++I2;
unsigned I1DestReg = I1.getOperand(0).getReg();

2
lib/Target/Hexagon/HexagonEarlyIfConv.cpp
View File

@ -367,7 +367,7 @@ bool HexagonEarlyIfConversion::isValidCandidate(const MachineBasicBlock *B)
return false;
for (auto &MI : *B) {
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
if (MI.isConditionalBranch())
return false;

2
lib/Target/Hexagon/HexagonGenMux.cpp
View File

@ -356,7 +356,7 @@ bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) {
return false;
};
for (auto I = B.rbegin(), E = B.rend(); I != E; ++I) {
if (I->isDebugValue())
if (I->isDebugInstr())
continue;
// This isn't 100% accurate, but it's safe.
// It won't detect (as a kill) a case like this

12
lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -134,7 +134,7 @@ static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB,
MachineBasicBlock::const_instr_iterator MIE) {
unsigned Count = 0;
for (; MIB != MIE; ++MIB) {
if (!MIB->isDebugValue())
if (!MIB->isDebugInstr())
++Count;
}
return Count;
@ -419,7 +419,7 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
I = MBB.instr_end();
--I;
while (I->isDebugValue()) {
while (I->isDebugInstr()) {
if (I == MBB.instr_begin())
return false;
--I;
@ -562,7 +562,7 @@ unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,
unsigned Count = 0;
while (I != MBB.begin()) {
--I;
if (I->isDebugValue())
if (I->isDebugInstr())
continue;
// Only removing branches from end of MBB.
if (!I->isBranch())
@ -1626,7 +1626,7 @@ bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
// considered a scheduling hazard, which is wrong. It should be the actual
// instruction preceding the dbg_value instruction(s), just like it is
// when debug info is not present.
if (MI.isDebugValue())
if (MI.isDebugInstr())
return false;
// Throwing call is a boundary.
@ -3164,7 +3164,7 @@ SmallVector<MachineInstr*, 2> HexagonInstrInfo::getBranchingInstrs(
I = MBB.instr_end();
--I;
while (I->isDebugValue()) {
while (I->isDebugInstr()) {
if (I == MBB.instr_begin())
return Jumpers;
--I;
@ -4201,7 +4201,7 @@ short HexagonInstrInfo::getRegForm(const MachineInstr &MI) const {
// use a constant extender, which requires another 4 bytes.
// For debug instructions and prolog labels, return 0.
unsigned HexagonInstrInfo::getSize(const MachineInstr &MI) const {
if (MI.isDebugValue() || MI.isPosition())
if (MI.isDebugInstr() || MI.isPosition())
return 0;
unsigned Size = MI.getDesc().getSize();

4
lib/Target/Hexagon/HexagonNewValueJump.cpp
View File

@ -302,7 +302,7 @@ static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
// and satisfy the following conditions.
++II;
for (MachineBasicBlock::iterator localII = II; localII != end; ++localII) {
if (localII->isDebugValue())
if (localII->isDebugInstr())
continue;
// Check 1.
@ -494,7 +494,7 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
MII != E;) {
MachineInstr &MI = *--MII;
if (MI.isDebugValue()) {
if (MI.isDebugInstr()) {
continue;
}

2
lib/Target/Hexagon/HexagonSplitDouble.cpp
View File

@ -163,7 +163,7 @@ bool HexagonSplitDoubleRegs::isFixedInstr(const MachineInstr *MI) const {
if (MI->mayLoad() || MI->mayStore())
if (MemRefsFixed || isVolatileInstr(MI))
return true;
if (MI->isDebugValue())
if (MI->isDebugInstr())
return false;
unsigned Opc = MI->getOpcode();

2
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
View File

@ -1037,7 +1037,7 @@ void HexagonPacketizerList::initPacketizerState() {
// Ignore bundling of pseudo instructions.
bool HexagonPacketizerList::ignorePseudoInstruction(const MachineInstr &MI,
const MachineBasicBlock *) {
if (MI.isDebugValue())
if (MI.isDebugInstr())
return true;
if (MI.isCFIInstruction())

2
lib/Target/Hexagon/RDFGraph.cpp
View File

@ -893,7 +893,7 @@ void DataFlowGraph::build(unsigned Options) {
NodeAddr<BlockNode*> BA = newBlock(Func, &B);
BlockNodes.insert(std::make_pair(&B, BA));
for (MachineInstr &I : B) {
if (I.isDebugValue())
if (I.isDebugInstr())
continue;
buildStmt(BA, I);
}

2
lib/Target/Hexagon/RDFLiveness.cpp
View File

@ -880,7 +880,7 @@ void Liveness::resetKills(MachineBasicBlock *B) {
for (auto I = B->rbegin(), E = B->rend(); I != E; ++I) {
MachineInstr *MI = &*I;
if (MI->isDebugValue())
if (MI->isDebugInstr())
continue;
MI->clearKillInfo();

2
lib/Target/Lanai/LanaiDelaySlotFiller.cpp
View File

@ -156,7 +156,7 @@ bool Filler::findDelayInstr(MachineBasicBlock &MBB,
for (MachineBasicBlock::reverse_instr_iterator I = ++Slot.getReverse();
I != MBB.instr_rend(); ++I) {
// skip debug value
if (I->isDebugValue())
if (I->isDebugInstr())
continue;
// Convert to forward iterator.

6
lib/Target/Lanai/LanaiInstrInfo.cpp
View File

@ -573,8 +573,8 @@ bool LanaiInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
while (Instruction != MBB.begin()) {
--Instruction;
// Skip over debug values.
if (Instruction->isDebugValue())
// Skip over debug instructions.
if (Instruction->isDebugInstr())
continue;
// Working from the bottom, when we see a non-terminator
@ -699,7 +699,7 @@ unsigned LanaiInstrInfo::removeBranch(MachineBasicBlock &MBB,
while (Instruction != MBB.begin()) {
--Instruction;
if (Instruction->isDebugValue())
if (Instruction->isDebugInstr())
continue;
if (Instruction->getOpcode() != Lanai::BT &&
Instruction->getOpcode() != Lanai::BRCC) {

2
lib/Target/Lanai/LanaiMemAluCombiner.cpp
View File

@ -343,7 +343,7 @@ MbbIterator LanaiMemAluCombiner::findClosestSuitableAluInstr(
break;
// Skip over debug instructions
if (First->isDebugValue())
if (First->isDebugInstr())
continue;
if (isSuitableAluInstr(IsSpls, First, *Base, *Offset)) {

4
lib/Target/MSP430/MSP430InstrInfo.cpp
View File

@ -113,7 +113,7 @@ unsigned MSP430InstrInfo::removeBranch(MachineBasicBlock &MBB,
while (I != MBB.begin()) {
--I;
if (I->isDebugValue())
if (I->isDebugInstr())
continue;
if (I->getOpcode() != MSP430::JMP &&
I->getOpcode() != MSP430::JCC &&
@ -183,7 +183,7 @@ bool MSP430InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I = MBB.end();
while (I != MBB.begin()) {
--I;
if (I->isDebugValue())
if (I->isDebugInstr())
continue;
// Working from the bottom, when we see a non-terminator

2
lib/Target/Mips/MipsAsmPrinter.cpp
View File

@ -160,6 +160,8 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
PrintDebugValueComment(MI, OS);
return;
}
if (MI->isDebugLabel())
return;
// If we just ended a constant pool, mark it as such.
if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) {

2
lib/Target/Mips/MipsConstantIslandPass.cpp
View File

@ -661,7 +661,7 @@ initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
if (!BBHasFallthrough(&MBB))
WaterList.push_back(&MBB);
for (MachineInstr &MI : MBB) {
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
int Opc = MI.getOpcode();

2
lib/Target/Mips/MipsDelaySlotFiller.cpp
View File

@ -679,7 +679,7 @@ bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
++I;
// skip debug value
if (CurrI->isDebugValue())
if (CurrI->isDebugInstr())
continue;
if (terminateSearch(*CurrI))

6
lib/Target/Mips/MipsInstrInfo.cpp
View File

@ -163,7 +163,7 @@ unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB,
// Note that indirect branches are not removed.
while (I != REnd && removed < 2) {
// Skip past debug instructions.
if (I->isDebugValue()) {
if (I->isDebugInstr()) {
++I;
continue;
}
@ -195,7 +195,7 @@ MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(
MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
// Skip all the debug instructions.
while (I != REnd && I->isDebugValue())
while (I != REnd && I->isDebugInstr())
++I;
if (I == REnd || !isUnpredicatedTerminator(*I)) {
@ -220,7 +220,7 @@ MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch(
// Skip past any debug instruction to see if the second last actual
// is a branch.
++I;
while (I != REnd && I->isDebugValue())
while (I != REnd && I->isDebugInstr())
++I;
if (I != REnd) {

2
lib/Target/Mips/MipsLongBranch.cpp
View File

@ -125,7 +125,7 @@ static MachineBasicBlock *getTargetMBB(const MachineInstr &Br) {
// found or it reaches E.
static ReverseIter getNonDebugInstr(ReverseIter B, const ReverseIter &E) {
for (; B != E; ++B)
if (!B->isDebugValue())
if (!B->isDebugInstr())
return B;
return E;

2
lib/Target/PowerPC/PPCEarlyReturn.cpp
View File

@ -128,7 +128,7 @@ protected:
if (J->getOperand(i).isMBB() &&
J->getOperand(i).getMBB() == &ReturnMBB)
OtherReference = true;
} else if (!J->isTerminator() && !J->isDebugValue())
} else if (!J->isTerminator() && !J->isDebugInstr())
break;
if (J == (*PI)->begin())

4
lib/Target/PowerPC/PPCHazardRecognizers.cpp
View File

@ -330,7 +330,7 @@ getHazardType(SUnit *SU, int Stalls) {
MachineInstr *MI = SU->getInstr();
if (MI->isDebugValue())
if (MI->isDebugInstr())
return NoHazard;
unsigned Opcode = MI->getOpcode();
@ -388,7 +388,7 @@ getHazardType(SUnit *SU, int Stalls) {
void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) {
MachineInstr *MI = SU->getInstr();
if (MI->isDebugValue())
if (MI->isDebugInstr())
return;
unsigned Opcode = MI->getOpcode();

4
lib/Target/PowerPC/PPCMIPeephole.cpp
View File

@ -232,7 +232,7 @@ bool PPCMIPeephole::simplifyCode(void) {
SomethingChanged = false;
for (MachineBasicBlock &MBB : *MF) {
for (MachineInstr &MI : MBB) {
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
if (TII->convertToImmediateForm(MI)) {
@ -261,7 +261,7 @@ bool PPCMIPeephole::simplifyCode(void) {
}
// Ignore debug instructions.
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
// Per-opcode peepholes.

2
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
View File

@ -249,7 +249,7 @@ bool PPCVSXSwapRemoval::gatherVectorInstructions() {
for (MachineBasicBlock &MBB : *MF) {
for (MachineInstr &MI : MBB) {
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
bool RelevantInstr = false;

4
lib/Target/Sparc/DelaySlotFiller.cpp
View File

@ -207,8 +207,8 @@ Filler::findDelayInstr(MachineBasicBlock &MBB,
if (!done)
--I;
// skip debug value
if (I->isDebugValue())
// skip debug instruction
if (I->isDebugInstr())
continue;
if (I->hasUnmodeledSideEffects() || I->isInlineAsm() || I->isPosition() ||

2
lib/Target/Sparc/SparcInstrInfo.cpp
View File

@ -280,7 +280,7 @@ unsigned SparcInstrInfo::removeBranch(MachineBasicBlock &MBB,
while (I != MBB.begin()) {
--I;
if (I->isDebugValue())
if (I->isDebugInstr())
continue;
if (I->getOpcode() != SP::BA

4
lib/Target/SystemZ/SystemZInstrInfo.cpp
View File

@ -389,7 +389,7 @@ bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I = MBB.end();
while (I != MBB.begin()) {
--I;
if (I->isDebugValue())
if (I->isDebugInstr())
continue;
// Working from the bottom, when we see a non-terminator instruction, we're
@ -479,7 +479,7 @@ unsigned SystemZInstrInfo::removeBranch(MachineBasicBlock &MBB,
while (I != MBB.begin()) {
--I;
if (I->isDebugValue())
if (I->isDebugInstr())
continue;
if (!I->isBranch())
break;

2
lib/Target/SystemZ/SystemZLongBranch.cpp
View File

@ -295,7 +295,7 @@ uint64_t SystemZLongBranch::initMBBInfo() {
// Add the terminators.
while (MI != End) {
if (!MI->isDebugValue()) {
if (!MI->isDebugInstr()) {
assert(MI->isTerminator() && "Terminator followed by non-terminator");
Terminators.push_back(describeTerminator(*MI));
skipTerminator(Position, Terminators.back(), false);

2
lib/Target/SystemZ/SystemZMachineScheduler.cpp
View File

@ -65,7 +65,7 @@ advanceTo(MachineBasicBlock::iterator NextBegin) {
std::next(LastEmittedMI) : MBB->begin());
for (; I != NextBegin; ++I) {
if (I->isPosition() || I->isDebugValue())
if (I->isPosition() || I->isDebugInstr())
continue;
HazardRec->emitInstruction(&*I);
}

2
lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
View File

@ -265,7 +265,7 @@ static void FixEndsAtEndOfFunction(
for (MachineBasicBlock &MBB : reverse(MF)) {
for (MachineInstr &MI : reverse(MBB)) {
if (MI.isPosition() || MI.isDebugValue())
if (MI.isPosition() || MI.isDebugInstr())
continue;
if (MI.getOpcode() == WebAssembly::END_BLOCK) {
BlockTops[&MI]->getOperand(0).setImm(int32_t(retType));

4
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
View File

@ -231,7 +231,7 @@ bool WebAssemblyExplicitLocals::runOnMachineFunction(MachineFunction &MF) {
MachineInstr &MI = *I++;
assert(!WebAssembly::isArgument(MI));
if (MI.isDebugValue() || MI.isLabel())
if (MI.isDebugInstr() || MI.isLabel())
continue;
// Replace tee instructions with tee_local. The difference is that tee
@ -375,7 +375,7 @@ bool WebAssemblyExplicitLocals::runOnMachineFunction(MachineFunction &MF) {
// Assert that all registers have been stackified at this point.
for (const MachineBasicBlock &MBB : MF) {
for (const MachineInstr &MI : MBB) {
if (MI.isDebugValue() || MI.isLabel())
if (MI.isDebugInstr() || MI.isLabel())
continue;
for (const MachineOperand &MO : MI.explicit_operands()) {
assert(

2
lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
View File

@ -151,7 +151,7 @@ unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB,
while (I != MBB.instr_begin()) {
--I;
if (I->isDebugValue())
if (I->isDebugInstr())
continue;
if (!I->isTerminator())
break;

4
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
View File

@ -163,7 +163,7 @@ static void Query(const MachineInstr &MI, AliasAnalysis &AA, bool &Read,
assert(!MI.isPosition());
assert(!MI.isTerminator());
if (MI.isDebugValue())
if (MI.isDebugInstr())
return;
// Check for loads.
@ -871,7 +871,7 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
SmallVector<unsigned, 0> Stack;
for (MachineBasicBlock &MBB : MF) {
for (MachineInstr &MI : MBB) {
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
for (MachineOperand &MO : reverse(MI.explicit_operands())) {
if (!MO.isReg())

2
lib/Target/X86/X86CallFrameOptimization.cpp
View File

@ -375,7 +375,7 @@ void X86CallFrameOptimization::collectCallInfo(MachineFunction &MF,
// Skip over DEBUG_VALUE.
// For globals in PIC mode, we can have some LEAs here. Skip them as well.
// TODO: Extend this to something that covers more cases.
while (I->getOpcode() == X86::LEA32r || I->isDebugValue())
while (I->getOpcode() == X86::LEA32r || I->isDebugInstr())
++I;
unsigned StackPtr = RegInfo.getStackRegister();

6
lib/Target/X86/X86CmovConversion.cpp
View File

@ -295,7 +295,7 @@ bool X86CmovConverterPass::collectCmovCandidates(
for (auto &I : *MBB) {
// Skip debug instructions.
if (I.isDebugValue())
if (I.isDebugInstr())
continue;
X86::CondCode CC = X86::getCondFromCMovOpc(I.getOpcode());
// Check if we found a X86::CMOVrr instruction.
@ -435,7 +435,7 @@ bool X86CmovConverterPass::checkForProfitableCmovCandidates(
RegDefMaps[PhyRegType].clear();
for (MachineInstr &MI : *MBB) {
// Skip debug instructions.
if (MI.isDebugValue())
if (MI.isDebugInstr())
continue;
unsigned MIDepth = 0;
unsigned MIDepthOpt = 0;
@ -605,7 +605,7 @@ static void packCmovGroup(MachineInstr *First, MachineInstr *Last) {
SmallVector<MachineInstr *, 2> DBGInstructions;
for (auto I = First->getIterator(), E = Last->getIterator(); I != E; I++) {
if (I->isDebugValue())
if (I->isDebugInstr())
DBGInstructions.push_back(&*I);
}

2
lib/Target/X86/X86FloatingPoint.cpp
View File

@ -1675,7 +1675,7 @@ void FPS::setKillFlags(MachineBasicBlock &MBB) const {
for (MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend();
I != E; ++I) {
if (I->isDebugValue())
if (I->isDebugInstr())
continue;
std::bitset<8> Defs;

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