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[X86] Don't select (cmp (and, imm), 0) to testw
Summary: X86ISelDAGToDAG tries to analyze ANDs compared with 0 to optimize to narrower immediates using subregisters. I don't think we should be optimizing to 16-bit test instructions. It goes against our normal behavior of promoting i16 operations to i32. It only saves one byte due to the need to add a 0x66 prefix. I think it would also be subject to a length changing prefix penalty in the decoders on Intel CPUs. Reviewers: RKSimon, zvi, spatel Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38273 llvm-svn: 314474
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@ -3025,7 +3025,10 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
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}
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// For example, "testl %eax, $32776" to "testw %ax, $32776".
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if (isUInt<16>(Mask) && N0.getValueType() != MVT::i16 &&
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// NOTE: We only want to form TESTW instructions if optimizing for
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// min size. Otherwise we only save one byte and possibly get a length
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// changing prefix penalty in the decoders.
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if (OptForMinSize && isUInt<16>(Mask) && N0.getValueType() != MVT::i16 &&
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(!(Mask & 0x8000) || hasNoSignedComparisonUses(Node))) {
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SDValue Imm = CurDAG->getTargetConstant(Mask, dl, MVT::i16);
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SDValue Reg = N0.getOperand(0);
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@ -53,7 +53,7 @@ define i32 @test_x86_tbm_bextri_u32_z2(i32 %a, i32 %b, i32 %c) nounwind {
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; CHECK-LABEL: test_x86_tbm_bextri_u32_z2:
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; CHECK: # BB#0:
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; CHECK-NEXT: shrl $4, %edi
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; CHECK-NEXT: testw $4095, %di # imm = 0xFFF
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; CHECK-NEXT: testl $4095, %edi # imm = 0xFFF
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; CHECK-NEXT: cmovnel %edx, %esi
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; CHECK-NEXT: movl %esi, %eax
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; CHECK-NEXT: retq
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@ -114,7 +114,7 @@ define i64 @test_x86_tbm_bextri_u64_z2(i64 %a, i64 %b, i64 %c) nounwind {
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; CHECK-LABEL: test_x86_tbm_bextri_u64_z2:
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; CHECK: # BB#0:
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; CHECK-NEXT: shrl $4, %edi
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; CHECK-NEXT: testw $4095, %di # imm = 0xFFF
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; CHECK-NEXT: testl $4095, %edi # imm = 0xFFF
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; CHECK-NEXT: cmovneq %rdx, %rsi
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: retq
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@ -3,7 +3,7 @@
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; Codegen shouldn't reduce the comparison down to testb $-1, %al
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; because that changes the result of the signed test.
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; PR5132
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; CHECK: testw $255, %ax
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; CHECK: testl $255, %eax
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
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target triple = "i386-apple-darwin10.0"
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@ -105,16 +105,33 @@ no:
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ret void
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}
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; CHECK-64-LABEL: g64x16:
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; CHECK-64: testw $-32640, %[[A0W:di|cx]]
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; CHECK-64: testl $32896, %[[A0D:edi|ecx]]
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; CHECK-64: ret
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; CHECK-32-LABEL: g64x16:
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; CHECK-32: testw $-32640, %ax
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; CHECK-32: testl $32896, %eax
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; CHECK-32: ret
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define void @g64x16(i64 inreg %x) nounwind {
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%t = and i64 %x, 32896
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%s = icmp eq i64 %t, 0
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br i1 %s, label %yes, label %no
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yes:
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call void @bar()
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ret void
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no:
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ret void
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}
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; CHECK-64-LABEL: g64x16minsize:
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; CHECK-64: testw $-32640, %[[A0W:di|cx]]
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; CHECK-64: ret
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; CHECK-32-LABEL: g64x16minsize:
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; CHECK-32: testw $-32640, %ax
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; CHECK-32: ret
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define void @g64x16minsize(i64 inreg %x) nounwind minsize {
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%t = and i64 %x, 32896
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%s = icmp eq i64 %t, 0
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br i1 %s, label %yes, label %no
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yes:
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call void @bar()
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ret void
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@ -122,16 +139,33 @@ no:
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ret void
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}
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; CHECK-64-LABEL: g32x16:
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; CHECK-64: testw $-32640, %[[A0W]]
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; CHECK-64: testl $32896, %[[A0D]]
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; CHECK-64: ret
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; CHECK-32-LABEL: g32x16:
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; CHECK-32: testw $-32640, %ax
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; CHECK-32: testl $32896, %eax
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; CHECK-32: ret
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define void @g32x16(i32 inreg %x) nounwind {
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%t = and i32 %x, 32896
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%s = icmp eq i32 %t, 0
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br i1 %s, label %yes, label %no
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yes:
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call void @bar()
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ret void
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no:
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ret void
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}
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; CHECK-64-LABEL: g32x16minsize:
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; CHECK-64: testw $-32640, %[[A0W]]
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; CHECK-64: ret
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; CHECK-32-LABEL: g32x16minsize:
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; CHECK-32: testw $-32640, %ax
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; CHECK-32: ret
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define void @g32x16minsize(i32 inreg %x) nounwind minsize {
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%t = and i32 %x, 32896
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%s = icmp eq i32 %t, 0
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br i1 %s, label %yes, label %no
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yes:
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call void @bar()
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ret void
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@ -139,7 +173,7 @@ no:
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ret void
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}
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; CHECK-64-LABEL: g64x32:
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; CHECK-64: testl $268468352, %e[[A0W]]
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; CHECK-64: testl $268468352, %[[A0D]]
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; CHECK-64: ret
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; CHECK-32-LABEL: g64x32:
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; CHECK-32: testl $268468352, %eax
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