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Minor wording tweak for memory model.

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llvm-svn: 136668
This commit is contained in:
Eli Friedman 2011-08-02 01:15:34 +00:00
parent 564f52b2bf
commit 22875e2d35
1 changed files with 4 additions and 4 deletions
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@ -1555,10 +1555,10 @@ emit more than one instruction to read the series of bytes.</p>
<p>Note that in cases where none of the atomic intrinsics are used, this model <p>Note that in cases where none of the atomic intrinsics are used, this model
places only one restriction on IR transformations on top of what is required places only one restriction on IR transformations on top of what is required
for single-threaded execution: introducing a store to a byte which might not for single-threaded execution: introducing a store to a byte which might not
otherwise be stored to can introduce undefined behavior. (Specifically, in otherwise be stored is not allowed in general. (Specifically, in the case
the case where another thread might write to and read from an address, where another thread might write to and read from an address, introducing a
introducing a store can change a load that may see exactly one write into store can change a load that may see exactly one write into a load that may
a load that may see multiple writes.)</p> see multiple writes.)</p>
<!-- FIXME: This model assumes all targets where concurrency is relevant have <!-- FIXME: This model assumes all targets where concurrency is relevant have
a byte-size store which doesn't affect adjacent bytes. As far as I can tell, a byte-size store which doesn't affect adjacent bytes. As far as I can tell,