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[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Sparc edition

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llvm-svn: 207502
This commit is contained in:
Craig Topper 2014-04-29 07:57:13 +00:00
parent 35c25e3649
commit 238308d7d5
19 changed files with 151 additions and 149 deletions
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28
lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
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@ -49,15 +49,15 @@ class SparcAsmParser : public MCTargetAsmParser {
bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out, unsigned &ErrorInfo,
bool MatchingInlineAsm);
bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
bool MatchingInlineAsm) override;
bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
SMLoc NameLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands);
bool ParseDirective(AsmToken DirectiveID);
SmallVectorImpl<MCParsedAsmOperand*> &Operands) override;
bool ParseDirective(AsmToken DirectiveID) override;
virtual unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
unsigned Kind);
unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
unsigned Kind) override;
// Custom parse functions for Sparc specific operands.
OperandMatchResultTy
@ -182,10 +182,10 @@ private:
struct MemOp Mem;
};
public:
bool isToken() const { return Kind == k_Token; }
bool isReg() const { return Kind == k_Register; }
bool isImm() const { return Kind == k_Immediate; }
bool isMem() const { return isMEMrr() || isMEMri(); }
bool isToken() const override { return Kind == k_Token; }
bool isReg() const override { return Kind == k_Register; }
bool isImm() const override { return Kind == k_Immediate; }
bool isMem() const override { return isMEMrr() || isMEMri(); }
bool isMEMrr() const { return Kind == k_MemoryReg; }
bool isMEMri() const { return Kind == k_MemoryImm; }
@ -204,7 +204,7 @@ public:
return StringRef(Tok.Data, Tok.Length);
}
unsigned getReg() const {
unsigned getReg() const override {
assert((Kind == k_Register) && "Invalid access!");
return Reg.RegNum;
}
@ -230,15 +230,15 @@ public:
}
/// getStartLoc - Get the location of the first token of this operand.
SMLoc getStartLoc() const {
SMLoc getStartLoc() const override {
return StartLoc;
}
/// getEndLoc - Get the location of the last token of this operand.
SMLoc getEndLoc() const {
SMLoc getEndLoc() const override {
return EndLoc;
}
virtual void print(raw_ostream &OS) const {
void print(raw_ostream &OS) const override {
switch (Kind) {
case k_Token: OS << "Token: " << getToken() << "\n"; break;
case k_Register: OS << "Reg: #" << getReg() << "\n"; break;

4
lib/Target/Sparc/DelaySlotFiller.cpp
View File

@ -50,12 +50,12 @@ namespace {
Subtarget(&TM.getSubtarget<SparcSubtarget>()) {
}
virtual const char *getPassName() const {
const char *getPassName() const override {
return "SPARC Delay Slot Filler";
}
bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
bool runOnMachineFunction(MachineFunction &F) {
bool runOnMachineFunction(MachineFunction &F) override {
bool Changed = false;
// This pass invalidates liveness information when it reorders

12
lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
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@ -38,12 +38,12 @@ public:
virtual ~SparcDisassembler() {}
/// getInstruction - See MCDisassembler.
virtual DecodeStatus getInstruction(MCInst &instr,
uint64_t &size,
const MemoryObject &region,
uint64_t address,
raw_ostream &vStream,
raw_ostream &cStream) const;
DecodeStatus getInstruction(MCInst &instr,
uint64_t &size,
const MemoryObject &region,
uint64_t address,
raw_ostream &vStream,
raw_ostream &cStream) const override;
};
}

4
lib/Target/Sparc/InstPrinter/SparcInstPrinter.h
View File

@ -30,8 +30,8 @@ public:
const MCSubtargetInfo &sti)
: MCInstPrinter(MAI, MII, MRI), STI(sti) {}
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
bool printSparcAliasInstr(const MCInst *MI, raw_ostream &OS);
bool isV9() const;

16
lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
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@ -102,11 +102,11 @@ namespace {
public:
SparcAsmBackend(const Target &T) : MCAsmBackend(), TheTarget(T) {}
unsigned getNumFixupKinds() const {
unsigned getNumFixupKinds() const override {
return Sparc::NumTargetFixupKinds;
}
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
const static MCFixupKindInfo Infos[Sparc::NumTargetFixupKinds] = {
// name offset bits flags
{ "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
@ -184,7 +184,7 @@ namespace {
}
}
bool mayNeedRelaxation(const MCInst &Inst) const {
bool mayNeedRelaxation(const MCInst &Inst) const override {
// FIXME.
return false;
}
@ -194,17 +194,17 @@ namespace {
bool fixupNeedsRelaxation(const MCFixup &Fixup,
uint64_t Value,
const MCRelaxableFragment *DF,
const MCAsmLayout &Layout) const {
const MCAsmLayout &Layout) const override {
// FIXME.
assert(0 && "fixupNeedsRelaxation() unimplemented");
return false;
}
void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {
// FIXME.
assert(0 && "relaxInstruction() unimplemented");
}
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override {
// Cannot emit NOP with size not multiple of 32 bits.
if (Count % 4 != 0)
return false;
@ -229,7 +229,7 @@ namespace {
SparcAsmBackend(T), OSType(OSType) { }
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
uint64_t Value, bool IsPCRel) const {
uint64_t Value, bool IsPCRel) const override {
Value = adjustFixupValue(Fixup.getKind(), Value);
if (!Value) return; // Doesn't change encoding.
@ -244,7 +244,7 @@ namespace {
}
MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType);
return createSparcELFObjectWriter(OS, is64Bit(), OSABI);
}

14
lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h
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@ -20,15 +20,15 @@ namespace llvm {
class StringRef;
class SparcELFMCAsmInfo : public MCAsmInfoELF {
virtual void anchor();
void anchor() override;
public:
explicit SparcELFMCAsmInfo(StringRef TT);
virtual const MCExpr* getExprForPersonalitySymbol(const MCSymbol *Sym,
unsigned Encoding,
MCStreamer &Streamer) const;
virtual const MCExpr* getExprForFDESymbol(const MCSymbol *Sym,
unsigned Encoding,
MCStreamer &Streamer) const;
const MCExpr*
getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding,
MCStreamer &Streamer) const override;
const MCExpr* getExprForFDESymbol(const MCSymbol *Sym,
unsigned Encoding,
MCStreamer &Streamer) const override;
};

2
lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
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@ -42,7 +42,7 @@ public:
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
const MCSubtargetInfo &STI) const override;
// getBinaryCodeForInstr - TableGen'erated function for getting the
// binary encoding for an instruction.

10
lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h
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@ -85,15 +85,15 @@ public:
Sparc::Fixups getFixupKind() const { return getFixupKind(Kind); }
/// @}
void PrintImpl(raw_ostream &OS) const;
void PrintImpl(raw_ostream &OS) const override;
bool EvaluateAsRelocatableImpl(MCValue &Res,
const MCAsmLayout *Layout) const;
void AddValueSymbols(MCAssembler *) const;
const MCSection *FindAssociatedSection() const {
const MCAsmLayout *Layout) const override;
void AddValueSymbols(MCAssembler *) const override;
const MCSection *FindAssociatedSection() const override {
return getSubExpr()->FindAssociatedSection();
}
void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const;
void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override;
static bool classof(const MCExpr *E) {
return E->getKind() == MCExpr::Target;

12
lib/Target/Sparc/SparcAsmPrinter.cpp
View File

@ -46,7 +46,7 @@ namespace {
explicit SparcAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
: AsmPrinter(TM, Streamer) {}
virtual const char *getPassName() const {
const char *getPassName() const override {
return "Sparc Assembly Printer";
}
@ -55,9 +55,9 @@ namespace {
const char *Modifier = nullptr);
void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
virtual void EmitFunctionBodyStart();
virtual void EmitInstruction(const MachineInstr *MI);
virtual void EmitEndOfAsmFile(Module &M);
void EmitFunctionBodyStart() override;
void EmitInstruction(const MachineInstr *MI) override;
void EmitEndOfAsmFile(Module &M) override;
static const char *getRegisterName(unsigned RegNo) {
return SparcInstPrinter::getRegisterName(RegNo);
@ -65,10 +65,10 @@ namespace {
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant, const char *ExtraCode,
raw_ostream &O);
raw_ostream &O) override;
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant, const char *ExtraCode,
raw_ostream &O);
raw_ostream &O) override;
void LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
const MCSubtargetInfo &STI);

6
lib/Target/Sparc/SparcCodeEmitter.cpp
View File

@ -40,7 +40,7 @@ class SparcCodeEmitter : public MachineFunctionPass {
const std::vector<MachineConstantPoolEntry> *MCPEs;
bool IsPIC;
void getAnalysisUsage(AnalysisUsage &AU) const {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineModuleInfo> ();
MachineFunctionPass::getAnalysisUsage(AU);
}
@ -53,9 +53,9 @@ public:
TM(tm), MCE(mce), MCPEs(nullptr),
IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
bool runOnMachineFunction(MachineFunction &MF);
bool runOnMachineFunction(MachineFunction &MF) override;
virtual const char *getPassName() const {
const char *getPassName() const override {
return "Sparc Machine Code Emitter";
}

17
lib/Target/Sparc/SparcFrameLowering.h
View File

@ -31,17 +31,18 @@ public:
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function.
void emitPrologue(MachineFunction &MF) const;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
void emitPrologue(MachineFunction &MF) const override;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;
void
eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const override;
bool hasReservedCallFrame(const MachineFunction &MF) const;
bool hasFP(const MachineFunction &MF) const;
bool hasReservedCallFrame(const MachineFunction &MF) const override;
bool hasFP(const MachineFunction &MF) const override;
void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS = nullptr) const;
RegScavenger *RS = nullptr) const override;
private:
// Remap input registers to output registers for leaf procedure.

10
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -41,7 +41,7 @@ public:
TM(tm) {
}
SDNode *Select(SDNode *N);
SDNode *Select(SDNode *N) override;
// Complex Pattern Selectors.
bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
@ -49,11 +49,11 @@ public:
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
std::vector<SDValue> &OutOps);
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
std::vector<SDValue> &OutOps) override;
virtual const char *getPassName() const {
const char *getPassName() const override {
return "SPARC DAG->DAG Pattern Instruction Selection";
}

50
lib/Target/Sparc/SparcISelLowering.h
View File

@ -55,47 +55,47 @@ namespace llvm {
const SparcSubtarget *Subtarget;
public:
SparcTargetLowering(TargetMachine &TM);
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
/// computeMaskedBitsForTargetNode - Determine which of the bits specified
/// in Mask are known to be either zero or one and return them in the
/// KnownZero/KnownOne bitsets.
virtual void computeMaskedBitsForTargetNode(const SDValue Op,
APInt &KnownZero,
APInt &KnownOne,
const SelectionDAG &DAG,
unsigned Depth = 0) const;
void computeMaskedBitsForTargetNode(const SDValue Op,
APInt &KnownZero,
APInt &KnownOne,
const SelectionDAG &DAG,
unsigned Depth = 0) const override;
virtual MachineBasicBlock *
MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB) const;
MachineBasicBlock *MBB) const override;
virtual const char *getTargetNodeName(unsigned Opcode) const;
const char *getTargetNodeName(unsigned Opcode) const override;
ConstraintType getConstraintType(const std::string &Constraint) const;
ConstraintType getConstraintType(const std::string &Constraint) const override;
ConstraintWeight
getSingleConstraintMatchWeight(AsmOperandInfo &info,
const char *constraint) const;
const char *constraint) const override;
void LowerAsmOperandForConstraint(SDValue Op,
std::string &Constraint,
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const;
SelectionDAG &DAG) const override;
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const override;
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
/// getSetCCResultType - Return the ISD::SETCC ValueType
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
virtual SDValue
SDValue
LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
SDLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
SmallVectorImpl<SDValue> &InVals) const override;
SDValue LowerFormalArguments_32(SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
@ -109,20 +109,20 @@ namespace llvm {
SDLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue
SDValue
LowerCall(TargetLowering::CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const;
SmallVectorImpl<SDValue> &InVals) const override;
SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const;
SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue
SDValue
LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals,
SDLoc dl, SelectionDAG &DAG) const;
SDLoc dl, SelectionDAG &DAG) const override;
SDValue LowerReturn_32(SDValue Chain,
CallingConv::ID CallConv, bool IsVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
@ -156,15 +156,15 @@ namespace llvm {
SDLoc DL,
SelectionDAG &DAG) const;
bool ShouldShrinkFPConstant(EVT VT) const {
bool ShouldShrinkFPConstant(EVT VT) const override {
// Do not shrink FP constpool if VT == MVT::f128.
// (ldd, call _Q_fdtoq) is more expensive than two ldds.
return VT != MVT::f128;
}
virtual void ReplaceNodeResults(SDNode *N,
void ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue>& Results,
SelectionDAG &DAG) const;
SelectionDAG &DAG) const override;
MachineBasicBlock *expandSelectCC(MachineInstr *MI, MachineBasicBlock *BB,
unsigned BROpcode) const;

56
lib/Target/Sparc/SparcInstrInfo.h
View File

@ -45,52 +45,52 @@ public:
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
virtual const SparcRegisterInfo &getRegisterInfo() const { return RI; }
const SparcRegisterInfo &getRegisterInfo() const { return RI; }
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot.
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const override;
/// isStoreToStackSlot - If the specified machine instruction is a direct
/// store to a stack slot, return the virtual or physical register number of
/// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot.
virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
unsigned isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const override;
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify = false) const ;
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify = false) const override ;
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const;
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const override;
virtual void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const override;
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const;
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;
unsigned getGlobalBaseReg(MachineFunction *MF) const;
};

14
lib/Target/Sparc/SparcJITInfo.h
View File

@ -34,27 +34,27 @@ class SparcJITInfo : public TargetJITInfo {
/// overwriting OLD with a branch to NEW. This is used for self-modifying
/// code.
///
virtual void replaceMachineCodeForFunction(void *Old, void *New);
void replaceMachineCodeForFunction(void *Old, void *New) override;
// getStubLayout - Returns the size and alignment of the largest call stub
// on Sparc.
virtual StubLayout getStubLayout();
StubLayout getStubLayout() override;
/// emitFunctionStub - Use the specified JITCodeEmitter object to emit a
/// small native function that simply calls the function at the specified
/// address.
virtual void *emitFunctionStub(const Function *F, void *Fn,
JITCodeEmitter &JCE);
void *emitFunctionStub(const Function *F, void *Fn,
JITCodeEmitter &JCE) override;
/// getLazyResolverFunction - Expose the lazy resolver to the JIT.
virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn);
LazyResolverFn getLazyResolverFunction(JITCompilerFn) override;
/// relocate - Before the JIT can run a block of code that has been emitted,
/// it must rewrite the code to contain the actual addresses of any
/// referenced global symbols.
virtual void relocate(void *Function, MachineRelocation *MR,
unsigned NumRelocs, unsigned char *GOTBase);
void relocate(void *Function, MachineRelocation *MR,
unsigned NumRelocs, unsigned char *GOTBase) override;
/// Initialize - Initialize internal stage for the function being JITted.
void Initialize(const MachineFunction &MF, bool isPIC) {

13
lib/Target/Sparc/SparcRegisterInfo.h
View File

@ -31,25 +31,26 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
SparcRegisterInfo(SparcSubtarget &st);
/// Code Generation virtual methods...
const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF =nullptr) const;
const uint32_t* getCallPreservedMask(CallingConv::ID CC) const;
const MCPhysReg *
getCalleeSavedRegs(const MachineFunction *MF =nullptr) const override;
const uint32_t* getCallPreservedMask(CallingConv::ID CC) const override;
const uint32_t* getRTCallPreservedMask(CallingConv::ID CC) const;
BitVector getReservedRegs(const MachineFunction &MF) const;
BitVector getReservedRegs(const MachineFunction &MF) const override;
const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
unsigned Kind) const;
unsigned Kind) const override;
void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = nullptr) const;
RegScavenger *RS = nullptr) const override;
void processFunctionBeforeFrameFinalized(MachineFunction &MF,
RegScavenger *RS = nullptr) const;
// Debug information queries.
unsigned getFrameRegister(const MachineFunction &MF) const;
unsigned getFrameRegister(const MachineFunction &MF) const override;
};
} // end namespace llvm

4
lib/Target/Sparc/SparcTargetMachine.cpp
View File

@ -77,8 +77,8 @@ public:
return getTM<SparcTargetMachine>();
}
virtual bool addInstSelector();
virtual bool addPreEmitPass();
bool addInstSelector() override;
bool addPreEmitPass() override;
};
} // namespace

20
lib/Target/Sparc/SparcTargetMachine.h
View File

@ -40,28 +40,28 @@ public:
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool is64bit);
virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const TargetFrameLowering *getFrameLowering() const {
const SparcInstrInfo *getInstrInfo() const override { return &InstrInfo; }
const TargetFrameLowering *getFrameLowering() const override {
return &FrameLowering;
}
virtual const SparcSubtarget *getSubtargetImpl() const{ return &Subtarget; }
virtual const SparcRegisterInfo *getRegisterInfo() const {
const SparcSubtarget *getSubtargetImpl() const override{ return &Subtarget; }
const SparcRegisterInfo *getRegisterInfo() const override {
return &InstrInfo.getRegisterInfo();
}
virtual const SparcTargetLowering* getTargetLowering() const {
const SparcTargetLowering* getTargetLowering() const override {
return &TLInfo;
}
virtual const SparcSelectionDAGInfo* getSelectionDAGInfo() const {
const SparcSelectionDAGInfo* getSelectionDAGInfo() const override {
return &TSInfo;
}
virtual SparcJITInfo *getJITInfo() {
SparcJITInfo *getJITInfo() override {
return &JITInfo;
}
virtual const DataLayout *getDataLayout() const { return &DL; }
const DataLayout *getDataLayout() const override { return &DL; }
// Pass Pipeline Configuration
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE);
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE) override;
};
/// SparcV8TargetMachine - Sparc 32-bit target machine

8
lib/Target/Sparc/SparcTargetStreamer.h
View File

@ -31,8 +31,8 @@ class SparcTargetAsmStreamer : public SparcTargetStreamer {
public:
SparcTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
virtual void emitSparcRegisterIgnore(unsigned reg);
virtual void emitSparcRegisterScratch(unsigned reg);
void emitSparcRegisterIgnore(unsigned reg) override;
void emitSparcRegisterScratch(unsigned reg) override;
};
@ -41,8 +41,8 @@ class SparcTargetELFStreamer : public SparcTargetStreamer {
public:
SparcTargetELFStreamer(MCStreamer &S);
MCELFStreamer &getStreamer();
virtual void emitSparcRegisterIgnore(unsigned reg) {}
virtual void emitSparcRegisterScratch(unsigned reg) {}
void emitSparcRegisterIgnore(unsigned reg) override {}
void emitSparcRegisterScratch(unsigned reg) override {}
};
} // end namespace llvm