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When checking that the necessary bits are zero in

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order to reduce ((x<<30)>>24) to x<<6, check the
correct bits.  PR 8547.

llvm-svn: 118665
This commit is contained in:
Dale Johannesen 2010-11-10 01:30:56 +00:00
parent 87c781b411
commit 24a82bdec2
2 changed files with 28 additions and 2 deletions
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4
lib/Transforms/InstCombine/InstCombineShifts.cpp
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@ -131,9 +131,9 @@ static bool CanEvaluateShifted(Value *V, unsigned NumBits, bool isLeftShift,
// We can turn shl(c1)+shr(c2) -> shl(c3)+and(c4), but it isn't
// profitable unless we know the and'd out bits are already zero.
if (CI->getZExtValue() > NumBits) {
unsigned HighBits = CI->getZExtValue() - NumBits;
unsigned LowBits = TypeWidth - CI->getZExtValue();
if (MaskedValueIsZero(I->getOperand(0),
APInt::getHighBitsSet(TypeWidth, HighBits)))
APInt::getLowBitsSet(TypeWidth, NumBits) << LowBits))
return true;
}

26
test/Transforms/InstCombine/pr8547.ll Normal file
View File

@ -0,0 +1,26 @@
; RUN: opt < %s -instcombine -S | FileCheck %s
; Converting the 2 shifts to SHL 6 without the AND is wrong. PR 8547.
@g_2 = global i32 0, align 4
@.str = constant [10 x i8] c"g_2 = %d\0A\00"
declare i32 @printf(i8*, ...)
define i32 @main() nounwind {
codeRepl:
br label %for.cond
for.cond: ; preds = %for.cond, %codeRepl
%storemerge = phi i32 [ 0, %codeRepl ], [ 5, %for.cond ]
store i32 %storemerge, i32* @g_2, align 4
%shl = shl i32 %storemerge, 30
%conv2 = lshr i32 %shl, 24
; CHECK: %0 = shl i32 %storemerge, 6
; CHECK: %conv2 = and i32 %0, 64
%tobool = icmp eq i32 %conv2, 0
br i1 %tobool, label %for.cond, label %codeRepl2
codeRepl2: ; preds = %for.cond
%call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i64 0, i64 0), i32 %conv2) nounwind
ret i32 0
}