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Thumb2 atomic operations
llvm-svn: 91321
This commit is contained in:
Jim Grosbach
parent
d16b19ff3e
commit
266c2d59e6
@ -3055,13 +3055,23 @@ ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
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.createVirtualRegister(ARM::GPRRegisterClass);
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc dl = MI->getDebugLoc();
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bool isThumb2 = Subtarget->isThumb2();
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unsigned ldrOpc, strOpc;
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switch (Size) {
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default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
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case 1: ldrOpc = ARM::LDREXB; strOpc = ARM::STREXB; break;
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case 2: ldrOpc = ARM::LDREXH; strOpc = ARM::STREXH; break;
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case 4: ldrOpc = ARM::LDREX; strOpc = ARM::STREX; break;
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case 1:
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ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
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strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
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break;
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case 2:
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ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
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strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
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break;
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case 4:
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ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
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strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
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break;
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}
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MachineFunction *MF = BB->getParent();
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@ -3088,10 +3098,10 @@ ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
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// bne exitMBB
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BB = loop1MBB;
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AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
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AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::CMPrr))
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AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
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.addReg(dest).addReg(oldval));
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BuildMI(BB, dl, TII->get(ARM::Bcc)).addMBB(exitMBB).addImm(ARMCC::NE)
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.addReg(ARM::CPSR);
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BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
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.addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
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BB->addSuccessor(loop2MBB);
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BB->addSuccessor(exitMBB);
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@ -3102,10 +3112,10 @@ ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
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BB = loop2MBB;
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AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
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.addReg(ptr));
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AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::CMPri))
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AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
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.addReg(scratch).addImm(0));
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BuildMI(BB, dl, TII->get(ARM::Bcc)).addMBB(loop1MBB).addImm(ARMCC::NE)
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.addReg(ARM::CPSR);
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BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
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.addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
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BB->addSuccessor(loop1MBB);
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BB->addSuccessor(exitMBB);
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@ -3130,12 +3140,22 @@ ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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unsigned ptr = MI->getOperand(1).getReg();
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unsigned incr = MI->getOperand(2).getReg();
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DebugLoc dl = MI->getDebugLoc();
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bool isThumb2 = Subtarget->isThumb2();
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unsigned ldrOpc, strOpc;
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switch (Size) {
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default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
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case 1: ldrOpc = ARM::LDREXB; strOpc = ARM::STREXB; break;
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case 2: ldrOpc = ARM::LDREXH; strOpc = ARM::STREXH; break;
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case 4: ldrOpc = ARM::LDREX; strOpc = ARM::STREX; break;
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case 1:
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ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
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strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
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break;
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case 2:
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ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
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strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
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break;
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case 4:
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ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
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strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
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break;
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}
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MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
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@ -3156,8 +3176,8 @@ ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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// loopMBB:
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// ldrex dest, ptr
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// add tmp, dest, incr
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// strex scratch, tmp, ptr
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// <binop> scratch2, dest, incr
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// strex scratch, scratch2, ptr
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// cmp scratch, #0
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// bne- loopMBB
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// fallthrough --> exitMBB
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@ -3169,10 +3189,10 @@ ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
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.addReg(ptr));
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AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::CMPri))
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AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
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.addReg(scratch).addImm(0));
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BuildMI(BB, dl, TII->get(ARM::Bcc)).addMBB(loopMBB).addImm(ARMCC::NE)
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.addReg(ARM::CPSR);
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BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
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.addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
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BB->addSuccessor(loopMBB);
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BB->addSuccessor(exitMBB);
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@ -3189,38 +3209,57 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc dl = MI->getDebugLoc();
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bool isThumb2 = Subtarget->isThumb2();
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switch (MI->getOpcode()) {
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default:
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MI->dump();
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llvm_unreachable("Unexpected instr type to insert");
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case ARM::ATOMIC_LOAD_ADD_I8: return EmitAtomicBinary(MI, BB, 1, ARM::ADDrr);
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case ARM::ATOMIC_LOAD_ADD_I16: return EmitAtomicBinary(MI, BB, 2, ARM::ADDrr);
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case ARM::ATOMIC_LOAD_ADD_I32: return EmitAtomicBinary(MI, BB, 4, ARM::ADDrr);
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case ARM::ATOMIC_LOAD_ADD_I8:
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return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
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case ARM::ATOMIC_LOAD_ADD_I16:
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return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
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case ARM::ATOMIC_LOAD_ADD_I32:
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return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
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case ARM::ATOMIC_LOAD_AND_I8: return EmitAtomicBinary(MI, BB, 1, ARM::ANDrr);
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case ARM::ATOMIC_LOAD_AND_I16: return EmitAtomicBinary(MI, BB, 2, ARM::ANDrr);
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case ARM::ATOMIC_LOAD_AND_I32: return EmitAtomicBinary(MI, BB, 4, ARM::ANDrr);
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case ARM::ATOMIC_LOAD_AND_I8:
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return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
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case ARM::ATOMIC_LOAD_AND_I16:
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return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
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case ARM::ATOMIC_LOAD_AND_I32:
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return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
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case ARM::ATOMIC_LOAD_OR_I8: return EmitAtomicBinary(MI, BB, 1, ARM::ORRrr);
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case ARM::ATOMIC_LOAD_OR_I16: return EmitAtomicBinary(MI, BB, 2, ARM::ORRrr);
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case ARM::ATOMIC_LOAD_OR_I32: return EmitAtomicBinary(MI, BB, 4, ARM::ORRrr);
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case ARM::ATOMIC_LOAD_OR_I8:
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return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
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case ARM::ATOMIC_LOAD_OR_I16:
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return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
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case ARM::ATOMIC_LOAD_OR_I32:
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return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
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case ARM::ATOMIC_LOAD_XOR_I8: return EmitAtomicBinary(MI, BB, 1, ARM::EORrr);
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case ARM::ATOMIC_LOAD_XOR_I16: return EmitAtomicBinary(MI, BB, 2, ARM::EORrr);
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case ARM::ATOMIC_LOAD_XOR_I32: return EmitAtomicBinary(MI, BB, 4, ARM::EORrr);
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case ARM::ATOMIC_LOAD_XOR_I8:
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return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
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case ARM::ATOMIC_LOAD_XOR_I16:
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return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
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case ARM::ATOMIC_LOAD_XOR_I32:
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return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
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case ARM::ATOMIC_LOAD_NAND_I8: return EmitAtomicBinary(MI, BB, 1, ARM::BICrr);
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case ARM::ATOMIC_LOAD_NAND_I16:return EmitAtomicBinary(MI, BB, 2, ARM::BICrr);
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case ARM::ATOMIC_LOAD_NAND_I32:return EmitAtomicBinary(MI, BB, 4, ARM::BICrr);
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case ARM::ATOMIC_LOAD_NAND_I8:
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return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
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case ARM::ATOMIC_LOAD_NAND_I16:
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return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
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case ARM::ATOMIC_LOAD_NAND_I32:
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return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
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case ARM::ATOMIC_LOAD_SUB_I8: return EmitAtomicBinary(MI, BB, 1, ARM::SUBrr);
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case ARM::ATOMIC_LOAD_SUB_I16: return EmitAtomicBinary(MI, BB, 2, ARM::SUBrr);
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case ARM::ATOMIC_LOAD_SUB_I32: return EmitAtomicBinary(MI, BB, 4, ARM::SUBrr);
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case ARM::ATOMIC_LOAD_SUB_I8:
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return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
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case ARM::ATOMIC_LOAD_SUB_I16:
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return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
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case ARM::ATOMIC_LOAD_SUB_I32:
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return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
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case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
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case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
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case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
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case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
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case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
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case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
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case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
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case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
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